OV - exec - Loop 892

0x44fbec LDR	X0, [SP, #280]

0x44fbf0 LDR	X3, [SP, #416]

0x44fbf4 LDR	X2, [SP, #424]

0x44fbf8 LDR	X23, [X0, X6,LSL #3]

0x44fbfc UBFM	X11, X23, #61, #60

0x44fc00 STR	X4, [X3, X23,LSL #3]

0x44fc04 ADD	X14, X11, #8

0x44fc08 STR	X5, [X2, X23,LSL #3]

0x44fc0c LDR	X3, [X8, X14]

0x44fc10 ADD	X24, X8, X14

0x44fc14 LDR	X18, [X8, X23,LSL #3]

0x44fc18 CMP	X18, X3

0x44fc1c B.GE	44fc3c

  (894) 0x44fc20 LDR	X1, [X15, X18,LSL #3]

  (894) 0x44fc24 LDR	X17, [X10, X1,LSL #3]

  (894) 0x44fc28 CMP	X17, #1

  (894) 0x44fc2c B.EQ	450e94

  (894) 0x44fc30 ADD	X18, X18, #1

  (894) 0x44fc34 CMP	X18, X3

  (894) 0x44fc38 B.LT	44fc20

0x44fc3c LDR	X17, [X16, X23,LSL #3]

0x44fc40 ADD	X23, X16, X14

0x44fc44 LDR	X9, [X16, X14]

0x44fc48 CMP	X17, X9

0x44fc4c B.GE	44fc6c

  (893) 0x44fc50 LDR	X14, [X7, X17,LSL #3]

  (893) 0x44fc54 LDR	X24, [X28, X14,LSL #3]

  (893) 0x44fc58 CMP	X24, #1

  (893) 0x44fc5c B.EQ	450e5c

  (893) 0x44fc60 ADD	X17, X17, #1

  (893) 0x44fc64 CMP	X17, X9

  (893) 0x44fc68 B.LT	44fc50

0x44fc6c LDR	X0, [X30, #16]

0x44fc70 ADD	X6, X6, #1

0x44fc74 CMP	X0, X6

0x44fc78 B.GT	44fbec

  (893) 0x450e5c LDR	X18, [X13, X14,LSL #3]

  (893) 0x450e60 ADD	X1, X5, #1

  (893) 0x450e64 ADD	X17, X17, #1

  (893) 0x450e68 LDR	X2, [X12, #8]

  (893) 0x450e6c STR	X18, [X2, X5,LSL #3]

  (893) 0x450e70 ORR	X5, XZR, X1

  (893) 0x450e74 LDR	X9, [X23]

  (893) 0x450e78 CMP	X9, X17

  (893) 0x450e7c B.GT	44fc50

0x450e80 LDR	X0, [X30, #16]

0x450e84 ADD	X6, X6, #1

0x450e88 CMP	X0, X6

0x450e8c B.GT	44fbec

  (894) 0x450e94 LDR	X9, [X26, X1,LSL #3]

  (894) 0x450e98 ADD	X0, X4, #1

  (894) 0x450e9c ADD	X18, X18, #1

  (894) 0x450ea0 LDR	X11, [X25, #8]

  (894) 0x450ea4 STR	X9, [X11, X4,LSL #3]

  (894) 0x450ea8 ORR	X4, XZR, X0

  (894) 0x450eac LDR	X3, [X24]

  (894) 0x450eb0 CMP	X18, X3

  (894) 0x450eb4 B.LT	44fc20

0x450eb8 B	44fc3c

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 646 - 661

--------------------------------------------------------------------------------

646:    for (i=pass_pointer[1]; i < pass_pointer[2]; i++)

647:    {

648:       i1 = pass_array[i];

649:       P_diag_start[i1] = cnt_nz;

650:       P_offd_start[i1] = cnt_nz_offd;

651:       for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

652:       {

653:          j1 = S_diag_j[j];

654:          if (CF_marker[j1] == 1)

655:          {   P_diag_pass[1][cnt_nz++] = fine_to_coarse[j1]; }

656:       }

657:       for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

658:       {

659:          j1 = S_offd_j[j];

660:          if (CF_marker_offd[j1] == 1)

661:          {   P_offd_pass[1][cnt_nz_offd++] = map_S_to_new[j1]; }

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:646-646,par_multi_interp.c:649-651,par_multi_interp.c:657-657
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	3.38
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:646-646,par_multi_interp.c:649-651,par_multi_interp.c:657-657
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	3.38
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:646-661
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:646-661.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:646,649-651,657.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fbec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X3, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [X2, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X8, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44fc3c <hypre_BoomerAMGBuildMultipass+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X16, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X16, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44fc6c <hypre_BoomerAMGBuildMultipass+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44fbec <hypre_BoomerAMGBuildMultipass+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44fbec <hypre_BoomerAMGBuildMultipass+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44fc3c <hypre_BoomerAMGBuildMultipass+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:646-661
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:646-661.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:646,649-651,657.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	4.00	4.00	4.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fbec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X3, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [X2, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X8, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X8, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44fc3c <hypre_BoomerAMGBuildMultipass+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X16, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X16, X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44fc6c <hypre_BoomerAMGBuildMultipass+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44fbec <hypre_BoomerAMGBuildMultipass+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44fbec <hypre_BoomerAMGBuildMultipass+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44fc3c <hypre_BoomerAMGBuildMultipass+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code