OV - exec - Loop 891

0x44f248 ADD	X21, X16, X10

0x44f24c LDR	X8, [X16, X10]

0x44f250 UBFM	X4, X8, #61, #60

0x44f254 LDR	X0, [X17, X8,LSL #3]

0x44f258 ADD	X2, X4, #8

0x44f25c ADD	X15, X20, X4

0x44f260 LDR	X27, [X17, X2]

0x44f264 ADD	X23, X17, X2

0x44f268 CMP	X0, X27

0x44f26c B.GE	44f28c

  (898) 0x44f270 LDR	X13, [X7, X0,LSL #3]

  (898) 0x44f274 LDR	X1, [X12, X13,LSL #3]

  (898) 0x44f278 CMP	X1, #1

  (898) 0x44f27c B.EQ	44f9e4

  (898) 0x44f280 ADD	X0, X0, #1

  (898) 0x44f284 CMP	X0, X27

  (898) 0x44f288 B.LT	44f270

0x44f28c LDR	X1, [X11, X8,LSL #3]

0x44f290 ADD	X4, X11, X2

0x44f294 LDR	X18, [X11, X2]

0x44f298 CMP	X1, X18

0x44f29c B.GE	44f2bc

  (897) 0x44f2a0 LDR	X23, [X24, X1,LSL #3]

  (897) 0x44f2a4 LDR	X13, [X30, X23,LSL #3]

  (897) 0x44f2a8 CMP	X13, #1

  (897) 0x44f2ac B.EQ	44f3fc

  (897) 0x44f2b0 ADD	X1, X1, #1

  (897) 0x44f2b4 CMP	X1, X18

  (897) 0x44f2b8 B.LT	44f2a0

0x44f2bc LDR	X2, [X15]

0x44f2c0 CMP	X2, #1

0x44f2c4 B.EQ	44f420

0x44f2c8 SUB	X6, X6, #1

0x44f2cc CMP	X9, X6

0x44f2d0 B.GT	44f43c

0x44f2d4 UBFM	X10, X6, #61, #60

0x44f2d8 B	44f248

  (897) 0x44f3fc LDR	X0, [X14, X2]

  (897) 0x44f400 ADD	X1, X1, #1

  (897) 0x44f404 ADD	X19, X19, #1

  (897) 0x44f408 ADD	X3, X0, #1

  (897) 0x44f40c STR	X3, [X14, X2]

  (897) 0x44f410 STR	X13, [X15]

  (897) 0x44f414 LDR	X18, [X4]

  (897) 0x44f418 CMP	X1, X18

  (897) 0x44f41c B.LT	44f2a0

0x44f420 LDR	X15, [X16, X9,LSL #3]

0x44f424 UBFM	X27, X9, #61, #60

0x44f428 ADD	X9, X9, #1

0x44f42c STR	X15, [X21]

0x44f430 STR	X8, [X16, X27]

0x44f434 CMP	X9, X6

0x44f438 B.LE	44f248

  (898) 0x44f9e4 LDR	X3, [X28, X2]

  (898) 0x44f9e8 ADD	X0, X0, #1

  (898) 0x44f9ec ADD	X5, X5, #1

  (898) 0x44f9f0 ADD	X18, X3, #1

  (898) 0x44f9f4 STR	X18, [X28, X2]

  (898) 0x44f9f8 STR	X1, [X15]

  (898) 0x44f9fc LDR	X27, [X23]

  (898) 0x44fa00 CMP	X27, X0

  (898) 0x44fa04 B.GT	44f270

0x44fa08 B	44f28c

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 488 - 514

--------------------------------------------------------------------------------

488:    for (i = pass_array_size-1; i > cnt-1; i--)

489:    {

490:      i1 = pass_array[i];

491:      for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

492:      {

493:         j1 = S_diag_j[j];

494:         if (CF_marker[j1] == 1)

495:         {

496:            P_diag_i[i1+1]++;

497:            cnt_nz++;

498:            assigned[i1] = 1;

499:         }

500:      }

501:      for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

502:      {

503:         j1 = S_offd_j[j];

504:         if (CF_marker_offd[j1] == 1)

505:         {

506:            P_offd_i[i1+1]++;

507:            cnt_nz_offd++;

508:            assigned[i1] = 1;

509:         }

510:      }

511:      if (assigned[i1] == 1)

512:      {

513:         pass_array[i++] = pass_array[cnt];

514:         pass_array[cnt++] = i1;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	3.88
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.97
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	3.88
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.97
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:488-514
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-514.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-491,501,511-514.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.97 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	3.88

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44f248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X21, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X16, X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X20, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X17, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44f28c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X11, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44f2bc <hypre_BoomerAMGBuildMultipass+0x95c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44f420 <hypre_BoomerAMGBuildMultipass+0xac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44f43c <hypre_BoomerAMGBuildMultipass+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 44f248 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X27, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X16, X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44f248 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44f28c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:488-514
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-514.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-491,501,511-514.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.97 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	3.88

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44f248

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X21, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X16, X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X20, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X17, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44f28c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X11, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X11, X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44f2bc <hypre_BoomerAMGBuildMultipass+0x95c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44f420 <hypre_BoomerAMGBuildMultipass+0xac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44f43c <hypre_BoomerAMGBuildMultipass+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 44f248 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X27, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X16, X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44f248 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44f28c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code