OV - exec - Loop 774

0x449f50 LDR	X17, [X11]    [2]

0x449f54 ADD	X14, X11, #8

0x449f58 LDR	X28, [X20, X17,LSL #3]    [5]

0x449f5c CMP	X28, X0

0x449f60 B.EQ	449f74

0x449f64 LDR	X28, [X5, X22]    [7]

0x449f68 STR	X17, [X28, X3,LSL #3]    [11]

0x449f6c ADD	X3, X3, #1

0x449f70 STR	X0, [X20, X17,LSL #3]    [5]

0x449f74 LDR	X11, [X11, #8]    [2]

0x449f78 LDR	X17, [X20, X11,LSL #3]    [3]

0x449f7c CMP	X17, X0

0x449f80 B.EQ	449f94

0x449f84 LDR	X28, [X5, X22]    [7]

0x449f88 STR	X11, [X28, X3,LSL #3]    [10]

0x449f8c ADD	X3, X3, #1

0x449f90 STR	X0, [X20, X11,LSL #3]    [3]

0x449f94 LDR	X17, [X14, #8]    [4]

0x449f98 ADD	X11, X14, #24

0x449f9c LDR	X28, [X20, X17,LSL #3]    [1]

0x449fa0 CMP	X28, X0

0x449fa4 B.EQ	449fb8

0x449fa8 LDR	X28, [X5, X22]    [7]

0x449fac STR	X17, [X28, X3,LSL #3]    [9]

0x449fb0 ADD	X3, X3, #1

0x449fb4 STR	X0, [X20, X17,LSL #3]    [1]

0x449fb8 LDR	X14, [X14, #16]    [4]

0x449fbc LDR	X17, [X20, X14,LSL #3]    [6]

0x449fc0 CMP	X17, X0

0x449fc4 B.EQ	449fd8

0x449fc8 LDR	X28, [X5, X22]    [7]

0x449fcc STR	X14, [X28, X3,LSL #3]    [8]

0x449fd0 ADD	X3, X3, #1

0x449fd4 STR	X0, [X20, X14,LSL #3]    [6]

0x449fd8 CMP	X15, X11

0x449fdc B.NE	449f50

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1082 - 1088

--------------------------------------------------------------------------------

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1082-1088
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	4.50
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1082-1088
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	4.50
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1082-1088
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1082-1088.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449f74 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449f94 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X14, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449fb8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449fd8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 449f50 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1082-1088
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1082-1088.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	6.67	6.67	6.67	4.00	4.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449f74 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449f94 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X14, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449fb8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449fd8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 449f50 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code