OV - exec - Loop 3771

0x4f94d0 LD1D	{Z22.D}, P3/Z, [X2, X1,LSL #3]    [1]

0x4f94d4 LD1D	{Z23.D}, P3/Z, [X7, X1,LSL #3]    [2]

0x4f94d8 LD1D	{Z24.D}, P3/Z, [X20, Z22.D,LSL #3]    [3]

0x4f94dc ADD	X1, X1, X27

0x4f94e0 FMLA	Z21.D, P3/M, Z24.D, Z23.D

0x4f94e4 WHILELO	P3.D, X1, X3

0x4f94e8 B.NE	4f94d0

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 337 - 339

--------------------------------------------------------------------------------

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

Coverage (%)	Name	Source Location	Module
►94.29+	GOMP_parallel		libomp.so
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:243	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:216	exec
○	hypre_BoomerAMGCycle	par_cycle.c:461	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec
►5.71+	GOMP_parallel		libomp.so
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:243	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:216	exec
○	hypre_BoomerAMGCycle	par_cycle.c:461	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:337-339
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	2.00
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:337-339
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	2.00
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:337-339
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:337-339.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	0.50	0.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	0.50	0.50	0.50	0.50	1.50	1.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	0.88
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f94d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z22.D}, P3/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P3/Z, [X20, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMLA Z21.D, P3/M, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P3.D, X1, X3	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 4f94d0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:337-339
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:337-339.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	0.50	0.50	0.00	0.00	1.50	1.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	0.50	0.50	0.50	0.50	1.50	1.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	0.88
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f94d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z22.D}, P3/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P3/Z, [X20, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMLA Z21.D, P3/M, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P3.D, X1, X3	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 4f94d0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code