OV - exec - Loop 3687

0x4f5478 ORR	X10, XZR, X9

0x4f547c LDUR	Q19, [X9, #8]    [2]

0x4f5480 LDR	Q17, [X10], #16    [3]

0x4f5484 LDR	Q5, [X9, #16]    [2]

0x4f5488 LDP	Q20, Q7, [X9, #48]    [2]

0x4f548c ADD	X9, X9, #128

0x4f5490 LDUR	Q6, [X10, #8]    [3]

0x4f5494 SUB	V21.2D, V19.2D, V17.2D

0x4f5498 LDR	Q18, [X10, #16]    [3]

0x4f549c LDUR	Q27, [X10, #24]    [3]

0x4f54a0 CMGT	V22.2D, V21.2D, #0

0x4f54a4 SUB	V23.2D, V6.2D, V5.2D

0x4f54a8 LDUR	Q31, [X9, #440]    [1]

0x4f54ac LDUR	Q1, [X9, #456]    [1]

0x4f54b0 SUB	V24.2D, V0.2D, V22.2D

0x4f54b4 CMGT	V25.2D, V23.2D, #0

0x4f54b8 SUB	V28.2D, V27.2D, V18.2D

0x4f54bc LDUR	Q16, [X9, #464]    [1]

0x4f54c0 SUB	V4.2D, V31.2D, V20.2D

0x4f54c4 LDUR	Q22, [X9, #472]    [1]

0x4f54c8 CMGT	V29.2D, V28.2D, #0

0x4f54cc SUB	V6.2D, V1.2D, V7.2D

0x4f54d0 LDUR	Q7, [X9, #480]    [1]

0x4f54d4 SUB	V26.2D, V24.2D, V25.2D

0x4f54d8 CMGT	V17.2D, V4.2D, #0

0x4f54dc LDUR	Q2, [X9, #488]    [1]

0x4f54e0 CMGT	V18.2D, V6.2D, #0

0x4f54e4 SUB	V16.2D, V22.2D, V16.2D

0x4f54e8 LDUR	Q3, [X9, #496]    [1]

0x4f54ec SUB	V30.2D, V26.2D, V29.2D

0x4f54f0 LDUR	Q0, [X9, #504]    [1]

0x4f54f4 CMGT	V23.2D, V16.2D, #0

0x4f54f8 SUB	V24.2D, V2.2D, V7.2D

0x4f54fc SUB	V19.2D, V30.2D, V17.2D

0x4f5500 SUB	V20.2D, V0.2D, V3.2D

0x4f5504 CMGT	V25.2D, V24.2D, #0

0x4f5508 SUB	V5.2D, V19.2D, V18.2D

0x4f550c CMGT	V21.2D, V20.2D, #0

0x4f5510 SUB	V26.2D, V5.2D, V23.2D

0x4f5514 SUB	V27.2D, V26.2D, V25.2D

0x4f5518 SUB	V0.2D, V27.2D, V21.2D

0x4f551c CMP	X9, X4

0x4f5520 B.NE	4f5478

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c: 145 - 148

--------------------------------------------------------------------------------

145:    for (i=0; i < num_rows; i++)

146:    {

147:       adiag = (A_i[i+1] - A_i[i]);

148:       if(adiag > 0) irownnz++;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_IJMatrixAssembleParCSR	IJMatrix_parcsr.c:2826	exec
○	BuildIJLaplacian27pt	amg.c:2272	exec
○	main	amg.c:274	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.79
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks
Function	hypre_CSRMatrixSetRownnz
Source	csr_matrix.c:145-148
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	8.93
Front-end cycles	5.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	51.28
Vector-efficiency ratio load	53.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.79
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks
Function	hypre_CSRMatrixSetRownnz
Source	csr_matrix.c:145-148
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	8.93
Front-end cycles	5.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	51.28
Vector-efficiency ratio load	53.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixSetRownnz
Source file and lines	csr_matrix.c:145-148
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c:145-148.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 51% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 8.93 cycles (1.79x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	5.38
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f5478

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR Q19, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q17, [X10], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q5, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP Q20, Q7, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR Q6, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V21.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q18, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR Q27, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V22.2D, V21.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V23.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q31, [X9, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR Q1, [X9, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V24.2D, V0.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V25.2D, V23.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V28.2D, V27.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q16, [X9, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V4.2D, V31.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q22, [X9, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V29.2D, V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V6.2D, V1.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q7, [X9, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V26.2D, V24.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q2, [X9, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V18.2D, V6.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V16.2D, V22.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q3, [X9, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V30.2D, V26.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q0, [X9, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V23.2D, V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V24.2D, V2.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V19.2D, V30.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V20.2D, V0.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V25.2D, V24.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V5.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V21.2D, V20.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V26.2D, V5.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V27.2D, V26.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V0.2D, V27.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f5478 <hypre_CSRMatrixSetRownnz+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixSetRownnz
Source file and lines	csr_matrix.c:145-148
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matrix.c:145-148.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 51% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 8.93 cycles (1.79x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	5.38
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f5478

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X10, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR Q19, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q17, [X10], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q5, [X9, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP Q20, Q7, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67
ADD X9, X9, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR Q6, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V21.2D, V19.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q18, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR Q27, [X10, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V22.2D, V21.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V23.2D, V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q31, [X9, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR Q1, [X9, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V24.2D, V0.2D, V22.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V25.2D, V23.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V28.2D, V27.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q16, [X9, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V4.2D, V31.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q22, [X9, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V29.2D, V28.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V6.2D, V1.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q7, [X9, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V26.2D, V24.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V17.2D, V4.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q2, [X9, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V18.2D, V6.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V16.2D, V22.2D, V16.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q3, [X9, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB V30.2D, V26.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDUR Q0, [X9, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMGT V23.2D, V16.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V24.2D, V2.2D, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V19.2D, V30.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V20.2D, V0.2D, V3.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V25.2D, V24.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V5.2D, V19.2D, V18.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMGT V21.2D, V20.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V26.2D, V5.2D, V23.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V27.2D, V26.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB V0.2D, V27.2D, V21.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f5478 <hypre_CSRMatrixSetRownnz+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code