OV - exec - Loop 3

0x40fa20 ORR	X4, XZR, X3

0x40fa24 STR	Q0, [X4], #16    [3]

0x40fa28 STR	Q0, [X3, #16]    [2]

0x40fa2c STR	Q0, [X4, #16]    [3]

0x40fa30 STP	Q0, Q0, [X3, #48]    [2]

0x40fa34 STP	Q0, Q0, [X3, #80]    [2]

0x40fa38 ADD	X3, X3, #128

0x40fa3c STUR	Q0, [X3, #496]    [1]

0x40fa40 CMP	X16, X3

0x40fa44 B.NE	40fa20

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/test/amg.c: 317 - 318

--------------------------------------------------------------------------------

317:    for (i = 0; i < local_num_rows; i++)

318:       values[i] = 1.0;

Coverage (%)	Name	Source Location	Module
►100.00+	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P6, P7, P10, P11,
Function	main
Source	amg.c:317-318
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	P6, P7, P10, P11,
Function	main
Source	amg.c:317-318
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	66.67
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	amg.c:317-318
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/test/amg.c:317-318.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 66% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	3.00	3.00	0.00	0.00	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	3.00	3.00	0.00	0.00	3.00	3.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40fa20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
ORR X4, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR Q0, [X4], #16	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X3, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X3, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X3, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X3, X3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STUR Q0, [X3, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 40fa20 <main+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	main
Source file and lines	amg.c:317-318
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/test/amg.c:317-318.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 66% register length (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 128 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	3.00	3.00	0.00	0.00	3.00	3.00	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	3.00	3.00	0.00	0.00	3.00	3.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40fa20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
ORR X4, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR Q0, [X4], #16	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X3, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STR Q0, [X4, #16]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X3, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
STP Q0, Q0, [X3, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ADD X3, X3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STUR Q0, [X3, #496]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 40fa20 <main+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code