OV - exec - Loop 2671

	Loop Id: 2671	Module: exec	Source: ams.c:720-722	Coverage: 0.1%

0x4af42c LDR	X7, [X26, X19,LSL #3]    [14]

0x4af430 LDR	D20, [X24, X7,LSL #3]    [8]

0x4af434 FCMPE	D20, #0

0x4af438 B.GE	4af448

0x4af43c LDR	D4, [X23, X19,LSL #3]    [12]

0x4af440 FNEG	D5, D4

0x4af444 STR	D5, [X23, X19,LSL #3]    [12]

0x4af448 ADD	X13, X19, #1

0x4af44c LDR	X3, [X26, X13,LSL #3]    [1]

0x4af450 LDR	D21, [X24, X3,LSL #3]    [6]

0x4af454 FCMPE	D21, #0

0x4af458 B.GE	4af468

0x4af45c LDR	D22, [X23, X13,LSL #3]    [16]

0x4af460 FNEG	D23, D22

0x4af464 STR	D23, [X23, X13,LSL #3]    [16]

0x4af468 ADD	X12, X13, #1

0x4af46c LDR	X2, [X26, X12,LSL #3]    [21]

0x4af470 LDR	D24, [X24, X2,LSL #3]    [10]

0x4af474 FCMPE	D24, #0

0x4af478 B.GE	4af488

0x4af47c LDR	D25, [X23, X12,LSL #3]    [22]

0x4af480 FNEG	D26, D25

0x4af484 STR	D26, [X23, X12,LSL #3]    [22]

0x4af488 ADD	X17, X13, #2

0x4af48c LDR	X18, [X26, X17,LSL #3]    [5]

0x4af490 LDR	D0, [X24, X18,LSL #3]    [2]

0x4af494 FCMPE	D0, #0

0x4af498 B.GE	4af4a8

0x4af49c LDR	D27, [X23, X17,LSL #3]    [7]

0x4af4a0 FNEG	D28, D27

0x4af4a4 STR	D28, [X23, X17,LSL #3]    [7]

0x4af4a8 ADD	X30, X13, #3

0x4af4ac LDR	X14, [X26, X30,LSL #3]    [19]

0x4af4b0 LDR	D29, [X24, X14,LSL #3]    [18]

0x4af4b4 FCMPE	D29, #0

0x4af4b8 B.GE	4af4c8

0x4af4bc LDR	D30, [X23, X30,LSL #3]    [20]

0x4af4c0 FNEG	D31, D30

0x4af4c4 STR	D31, [X23, X30,LSL #3]    [20]

0x4af4c8 ADD	X16, X13, #4

0x4af4cc LDR	X5, [X26, X16,LSL #3]    [3]

0x4af4d0 LDR	D2, [X24, X5,LSL #3]    [11]

0x4af4d4 FCMPE	D2, #0

0x4af4d8 B.GE	4af4e8

0x4af4dc LDR	D1, [X23, X16,LSL #3]    [4]

0x4af4e0 FNEG	D6, D1

0x4af4e4 STR	D6, [X23, X16,LSL #3]    [4]

0x4af4e8 ADD	X4, X13, #5

0x4af4ec LDR	X9, [X26, X4,LSL #3]    [9]

0x4af4f0 LDR	D7, [X24, X9,LSL #3]    [17]

0x4af4f4 FCMPE	D7, #0

0x4af4f8 B.GE	4af508

0x4af4fc LDR	D16, [X23, X4,LSL #3]    [15]

0x4af500 FNEG	D17, D16

0x4af504 STR	D17, [X23, X4,LSL #3]    [15]

0x4af508 ADD	X0, X13, #6

0x4af50c LDR	X1, [X26, X0,LSL #3]    [23]

0x4af510 LDR	D18, [X24, X1,LSL #3]    [24]

0x4af514 FCMPE	D18, #0

0x4af518 B.GE	4af528

0x4af51c LDR	D19, [X23, X0,LSL #3]    [13]

0x4af520 FNEG	D3, D19

0x4af524 STR	D3, [X23, X0,LSL #3]    [13]

0x4af528 ADD	X19, X13, #7

0x4af52c CMP	X27, X19

0x4af530 B.GT	4af42c

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 720 - 722

--------------------------------------------------------------------------------

720:    for (i = 0; i < num_rows; i++)

721:       if (A_diag_data[A_diag_I[i]] < 0)

722:          l1_norm[i] = -l1_norm[i];

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:1358	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P10, P11, P12,
Function	hypre_ParCSRComputeL1Norms
Source	ams.c:720-722
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.67
Front-end cycles	8.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P10, P11, P12,
Function	hypre_ParCSRComputeL1Norms
Source	ams.c:720-722
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.67
Front-end cycles	8.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	66.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1Norms
Source file and lines	ams.c:720-722
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:720-722.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 2.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	4.50	4.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4af42c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X7, [X26, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af448 <hypre_ParCSRComputeL1Norms+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D4, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D5, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X24, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af468 <hypre_ParCSRComputeL1Norms+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X12, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af488 <hypre_ParCSRComputeL1Norms+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D26, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X17, X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4a8 <hypre_ParCSRComputeL1Norms+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X30, X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4c8 <hypre_ParCSRComputeL1Norms+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D31, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X16, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X26, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4e8 <hypre_ParCSRComputeL1Norms+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D6, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X4, X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X9, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D7, [X24, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af508 <hypre_ParCSRComputeL1Norms+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D16, [X23, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D17, [X23, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X0, X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D18, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af528 <hypre_ParCSRComputeL1Norms+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D3, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X13, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4af42c <hypre_ParCSRComputeL1Norms+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRComputeL1Norms
Source file and lines	ams.c:720-722
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	66
loop length	264
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	4.50	4.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4af42c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X7, [X26, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af448 <hypre_ParCSRComputeL1Norms+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D4, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D5, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X13, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X24, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af468 <hypre_ParCSRComputeL1Norms+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X12, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af488 <hypre_ParCSRComputeL1Norms+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D26, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X17, X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X26, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4a8 <hypre_ParCSRComputeL1Norms+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X30, X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4c8 <hypre_ParCSRComputeL1Norms+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D31, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X16, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X26, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af4e8 <hypre_ParCSRComputeL1Norms+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D6, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X4, X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X9, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D7, [X24, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af508 <hypre_ParCSRComputeL1Norms+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D16, [X23, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D17, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D17, [X23, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X0, X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D18, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4af528 <hypre_ParCSRComputeL1Norms+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D3, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X13, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4af42c <hypre_ParCSRComputeL1Norms+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code