OV - exec - Function hypre_IJMatrixAssembleParCSR._omp

	Function: hypre_IJMatrixAssembleParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage: 0.36%

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x4e1704 STP	X29, X30, [SP, #976]!

0x4e1708 ADD	X29, SP, #0

0x4e170c STR	X21, [SP, #32]

0x4e1710 LDR	X21, [X0, #24]

0x4e1714 STP	X19, X20, [SP, #16]

0x4e1718 ORR	X20, XZR, X0

0x4e171c BL	40f400

0x4e1720 SBFM	X19, X0, #0, #31

0x4e1724 BL	40f150

0x4e1728 SDIV	X9, X21, X19

0x4e172c SBFM	X2, X0, #0, #31

0x4e1730 MSUB	X1, X9, X19, X21

0x4e1734 CMP	X2, X1

0x4e1738 B.LT	4e17fc

0x4e173c MADD	X30, X9, X2, X1

0x4e1740 ADD	X11, X9, X30

0x4e1744 CMP	X30, X11

0x4e1748 B.GE	4e17b0

0x4e174c LDP	X10, X3, [X20]

0x4e1750 LDR	X7, [X20, #16]

0x4e1754 ADD	X5, X10, #8

0x4e1758 LDR	X6, [X20, #32]

0x4e175c HINT	#0

      (3409) 0x4e1760 LDR	X0, [X10, X30,LSL #3]

      (3409) 0x4e1764 LDR	X12, [X5, X30,LSL #3]

      (3409) 0x4e1768 UBFM	X4, X0, #61, #60

      (3409) 0x4e176c ADD	X8, X7, X4

      (3409) 0x4e1770 ADD	X13, X3, X4

      (3409) 0x4e1774 CMP	X0, X12

      (3409) 0x4e1778 B.GE	4e17a4

    (3408) 0x4e177c HINT	#0

    (3408) 0x4e1780 LDR	X14, [X3, X0,LSL #3]

    (3408) 0x4e1784 SUB	X15, X14, X6

    (3408) 0x4e1788 STR	X15, [X3, X0,LSL #3]

    (3408) 0x4e178c CMP	X30, X15

    (3408) 0x4e1790 B.EQ	4e17c0

    (3408) 0x4e1794 LDR	X16, [X5, X30,LSL #3]

    (3408) 0x4e1798 ADD	X0, X0, #1

    (3408) 0x4e179c CMP	X16, X0

    (3408) 0x4e17a0 B.GT	4e1780

      (3409) 0x4e17a4 ADD	X30, X30, #1

      (3409) 0x4e17a8 CMP	X11, X30

      (3409) 0x4e17ac B.NE	4e1760

(3410) 0x4e17b0 LDP	X19, X20, [SP, #16]

(3410) 0x4e17b4 LDR	X21, [SP, #32]

(3410) 0x4e17b8 LDP	X29, X30, [SP], #48

(3410) 0x4e17bc RET

  (3407) 0x4e17c0 LDR	D1, [X7, X0,LSL #3]

  (3407) 0x4e17c4 LDR	D0, [X8]

  (3407) 0x4e17c8 LDR	X17, [X13]

  (3407) 0x4e17cc STR	D1, [X8]

  (3407) 0x4e17d0 STR	D0, [X7, X0,LSL #3]

  (3407) 0x4e17d4 STR	X17, [X3, X0,LSL #3]

  (3407) 0x4e17d8 ADD	X0, X0, #1

  (3407) 0x4e17dc STR	X30, [X13]

  (3407) 0x4e17e0 LDR	X18, [X5, X30,LSL #3]

  (3407) 0x4e17e4 CMP	X0, X18

  (3407) 0x4e17e8 B.LT	4e1780

  (3407) 0x4e17ec ADD	X30, X30, #1

  (3407) 0x4e17f0 CMP	X11, X30

  (3407) 0x4e17f4 B.NE	4e1760

(3410) 0x4e17f8 B	4e17b0

0x4e17fc ADD	X9, X9, #1

0x4e1800 MOVZ	X1, #0

0x4e1804 B	4e173c

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libomp.so
○	hypre_IJMatrixAssembleParCSR	IJMatrix_parcsr.c:2817	exec
○	BuildIJLaplacian27pt	amg.c:2272	exec
○	main	amg.c:274	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e1704

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f400 <@plt_start@+0x400>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f150 <@plt_start@+0x150>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4e17fc <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4e17b0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4e173c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

10% of peak load performance is reached (10.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (10.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e1704

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f400 <@plt_start@+0x400>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f150 <@plt_start@+0x150>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4e17fc <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4e17b0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4e173c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR._omp_fn.1–	0.36	0.05
▼Loop 3410 - IJMatrix_parcsr.c:2798-2812 - exec–	0	0
▼Loop 3407 - IJMatrix_parcsr.c:2802-2812 - exec–	0.06	0.01
▼Loop 3408 - IJMatrix_parcsr.c:2802-2811 - exec–	0.26	0.04
○Loop 3409 - IJMatrix_parcsr.c:2802-2811 - exec	0.03	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code