OV - exec - Function hypre

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/utilities/random.c: 76 - 116

--------------------------------------------------------------------------------

76:    high = Seed / q;

77:    low = Seed % q;

78:    test = a * low - r * high;

[...]

85:       Seed = test + m;

[...]

115:    return ((HYPRE_Real)(hypre_RandI()) / m);

116: }

0x506344 ADRP	X5,

0x506348 MOVZ	X0, #64377

0x50634c LDR	X4, [X5, #752]

0x506350 MOVK	X0, #8163

0x506354 MOVZ	X1, #62237

0x506358 MOVK	X0, #1455

0x50635c MOVK	X1, #1

0x506360 MOVK	X0, #16807

0x506364 MOVN	X7, #2835

0x506368 MOVZ	X3, #32

0x50636c MOVZ	X6, #16807

0x506370 MOVK	X3, #15872

0x506374 ORR	X2, XZR, #6016

0x506378 SMULH	X8, X4, X0

0x50637c FMOV	D0, X3

0x506380 SBFM	X9, X8, #15, #63

0x506384 SUB	X10, X9, X4,ASR #63

0x506388 MSUB	X11, X10, X1, X4

0x50638c MADD	X12, X10, X7, XZR

0x506390 MADD	X13, X11, X6, X12

0x506394 CMP	X13, #0

0x506398 ADD	X14, X13, X2

0x50639c CSEL	X15, X14, X13, #13

0x5063a0 SCVTF	D1, X15

0x5063a4 STR	X15, [X5, #752]

0x5063a8 FMUL	D0, D1, D0

0x5063ac RET

0x5063b0 HINT	#0

0x5063b4 HINT	#0

0x5063b8 HINT	#0

0x5063bc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2179	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	random.c:76-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/utilities/random.c:76-78,85,115-116.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 8 bytes. The binary function is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 506344

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X5, <52e344>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #64377	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X5, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVK X0, #8163	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #62237	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #1455	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X7, #2835	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #15872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, #6016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMULH X8, X4, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
FMOV D0, X3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X9, X8, #15, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X9, X4,ASR #63	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MSUB X11, X10, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X11, X6, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X14, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X14, X13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D1, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR X15, [X5, #752]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	random.c:76-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/utilities/random.c:76-78,85,115-116.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 8 bytes. The binary function is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 506344

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X5, <52e344>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #64377	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X5, #752]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVK X0, #8163	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #62237	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #1455	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X7, #2835	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #15872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, #6016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMULH X8, X4, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
FMOV D0, X3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X9, X8, #15, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X9, X4,ASR #63	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MSUB X11, X10, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X11, X6, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X14, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X14, X13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D1, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR X15, [X5, #752]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
○hypre_Rand	0.16	0.02

Report Configuration

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code