OV - exec - Loop 576

0x46a4c0 ADD	X18, X18, #1

0x46a4c4 CMP	X18, X0

0x46a4c8 B.GE	46a4e4

0x46a4cc LDR	X3, [X14, X18,LSL #3]    [1]

0x46a4d0 TBNZ	X3, #63, 46a4c0

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 498 - 500

--------------------------------------------------------------------------------

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P0, P1,
Function	.omp_outlined..2#0x469780
Source	par_strength.c:498-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	0.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P0, P1,
Function	.omp_outlined..2#0x469780
Source	par_strength.c:498-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	0.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x469780
Source file and lines	par_strength.c:498-500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:498-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a4cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 46a4e4 <.omp_outlined..2+0xd64>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X3, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ X3, #63, 46a4c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x469780
Source file and lines	par_strength.c:498-500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:498-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a4cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 46a4e4 <.omp_outlined..2+0xd64>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X3, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ X3, #63, 46a4c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code