OV - exec - Loop 51

0x48aa80 LDUR	X14, [X29, #496]

  (50) 0x48aa84 STR	X30, [X5, X20,LSL #3]

  (50) 0x48aa88 STR	X28, [X7, X20,LSL #3]

  (50) 0x48aa8c ORR	X28, XZR, X24

  (50) 0x48aa90 ORR	X30, XZR, X6

  (50) 0x48aa94 ORR	X20, XZR, X26

  (50) 0x48aa98 CMP	X26, X14

  (50) 0x48aa9c B.EQ	48ac98

  (50) 0x48aaa0 LDUR	X8, [X29, #504]

  (50) 0x48aaa4 LDR	X8, [X8]

  (50) 0x48aaa8 CBZ	X8, 48aab4

  (50) 0x48aab4 LDR	X8, [X15]

  (50) 0x48aab8 CBZ	X8, 48ab80

  (50) 0x48ab80 ORR	X24, XZR, X28

  (50) 0x48ab84 ADD	X26, X20, #1

  (50) 0x48ab88 LDR	X27, [X2, X20,LSL #3]

  (50) 0x48ab8c LDR	X8, [X2, X26,LSL #3]

  (50) 0x48ab90 CMP	X27, X8

  (50) 0x48ab94 B.GE	48aa84

0x48ab98 B	48abb8

0x48abb8 LDUR	X8, [X29, #456]

0x48abbc LDR	X13, [X8]

0x48abc0 LDUR	X8, [X29, #464]

0x48abc4 LDR	X14, [X8]

0x48abc8 LDUR	X8, [X29, #472]

0x48abcc LDR	X19, [X8]

0x48abd0 LDUR	X8, [X29, #480]

0x48abd4 LDR	X8, [X8]

0x48abd8 B	48abf0

0x48abe0 LDR	X9, [X2, X26,LSL #3]

0x48abe4 ADD	X27, X27, #1

0x48abe8 CMP	X27, X9

0x48abec B.GE	48aa80

0x48abf0 LDR	X10, [X3, X27,LSL #3]

0x48abf4 ADD	X9, X10, #1

0x48abf8 LDR	X12, [X4, X10,LSL #3]

0x48abfc LDR	X25, [X4, X9,LSL #3]

0x48ac00 B	48ac08

  (52) 0x48ac04 ADD	X12, X12, #1

  (52) 0x48ac08 CMP	X12, X25

  (52) 0x48ac0c B.GE	48ac40

  (52) 0x48ac10 LDR	X16, [X13, X12,LSL #3]

  (52) 0x48ac14 LDR	X21, [X0, X16,LSL #3]

  (52) 0x48ac18 CMP	X21, X30

  (52) 0x48ac1c B.GE	48ac04

  (52) 0x48ac20 STR	X6, [X0, X16,LSL #3]

  (52) 0x48ac24 ADD	X6, X6, #1

  (52) 0x48ac28 LDR	X25, [X4, X9,LSL #3]

  (52) 0x48ac2c B	48ac04

0x48ac40 LDR	X12, [X11]

0x48ac44 CBZ	X12, 48abe0

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

[...]

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x48a8e0
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x48a8e0
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x48a8e0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144,170,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 48abe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48abb8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48abf0 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48aa80 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48ac08 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 48abe0 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x48a8e0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144,170,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 48abe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48abb8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48abf0 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48aa80 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48ac08 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 48abe0 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code