OV - exec - Loop 438

0x48cac0 LDP	X30, X21, [SP, #88]

  (437) 0x48cac4 LDUR	X8, [X29, #440]

  (437) 0x48cac8 ORR	X19, XZR, X3

  (437) 0x48cacc ORR	X22, XZR, X2

  (437) 0x48cad0 CMP	X26, X8

  (437) 0x48cad4 B.GE	48ce18

  (437) 0x48cad8 LDUR	X8, [X29, #432]

  (437) 0x48cadc LDR	X8, [X8]

  (437) 0x48cae0 CBZ	X8, 48cb04

  (437) 0x48cb04 LDUR	X8, [X29, #424]

  (437) 0x48cb08 LDR	X8, [X8]

  (437) 0x48cb0c CBZ	X8, 48cc80

  (437) 0x48cc80 ORR	X3, XZR, X19

  (437) 0x48cc84 LDR	X4, [X15, X26,LSL #3]

  (437) 0x48cc88 ADD	X26, X26, #1

  (437) 0x48cc8c LDR	X8, [X15, X26,LSL #3]

  (437) 0x48cc90 CMP	X4, X8

  (437) 0x48cc94 B.GE	48cac4

0x48cc98 B	48ccb8

0x48ccb8 LDR	X8, [SP, #56]

0x48ccbc LDR	X5, [X8]

0x48ccc0 LDR	X8, [SP, #64]

0x48ccc4 LDR	X6, [X8]

0x48ccc8 LDR	X8, [SP, #72]

0x48cccc LDR	X7, [X8]

0x48ccd0 LDR	X8, [SP, #80]

0x48ccd4 LDR	X30, [X8]

0x48ccd8 B	48ccf0

0x48cce0 LDR	X8, [X15, X26,LSL #3]

0x48cce4 ADD	X4, X4, #1

0x48cce8 CMP	X4, X8

0x48ccec B.GE	48cac0

0x48ccf0 LDR	X9, [X16, X4,LSL #3]

0x48ccf4 LDR	D0, [X17, X4,LSL #3]

0x48ccf8 ADD	X8, X9, #1

0x48ccfc LDR	X10, [X18, X9,LSL #3]

0x48cd00 LDR	X27, [X18, X8,LSL #3]

0x48cd04 CMP	X10, X27

0x48cd08 B.GE	48cd78

0x48cd0c LDUR	X11, [X29, #456]

0x48cd10 LDR	X24, [X25]

0x48cd14 LDR	X23, [X11]

0x48cd18 LDUR	X11, [X29, #496]

0x48cd1c LDR	X11, [X11]

0x48cd20 B	48cd40

  (439) 0x48cd24 LDR	D1, [X23, X10,LSL #3]

  (439) 0x48cd28 LDR	D2, [X24, X21,LSL #3]

  (439) 0x48cd2c FMADD	D1, D1, D0, D2

  (439) 0x48cd30 STR	D1, [X24, X21,LSL #3]

  (439) 0x48cd34 ADD	X10, X10, #1

  (439) 0x48cd38 CMP	X10, X27

  (439) 0x48cd3c B.GE	48cd78

  (439) 0x48cd40 LDR	X12, [X5, X10,LSL #3]

  (439) 0x48cd44 LDR	X21, [X0, X12,LSL #3]

  (439) 0x48cd48 CMP	X21, X22

  (439) 0x48cd4c B.GE	48cd24

  (439) 0x48cd50 LDR	D1, [X23, X10,LSL #3]

  (439) 0x48cd54 STR	X2, [X0, X12,LSL #3]

  (439) 0x48cd58 STR	X12, [X11, X2,LSL #3]

  (439) 0x48cd5c LDR	X27, [X18, X8,LSL #3]

  (439) 0x48cd60 FMUL	D1, D1, D0

  (439) 0x48cd64 STR	D1, [X24, X2,LSL #3]

  (439) 0x48cd68 ADD	X2, X2, #1

  (439) 0x48cd6c ADD	X10, X10, #1

  (439) 0x48cd70 CMP	X10, X27

  (439) 0x48cd74 B.LT	48cd40

0x48cd78 LDR	X10, [X28]

0x48cd7c CBZ	X10, 48cce0

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 968

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

[...]

886:       if (num_cols_offd_A)

[...]

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x48c890
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-968
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	3.75
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.20
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	5.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x48c890
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-968
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	3.75
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.20
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..9#0x48c890
Source file and lines	par_csr_matop.c:865-968
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-878,886,917,937-940,946-948,956-968.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.67 to 1.33 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	0.00	0.00
cycles	3.00	3.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.75
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

26% of peak load performance is reached (25.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 48cce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 48ccb8 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48ccf0 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48cac0 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48cd78 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48cd40 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 48cce0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..9#0x48c890
Source file and lines	par_csr_matop.c:865-968
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-878,886,917,937-940,946-948,956-968.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.67 to 1.33 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	0.00	0.00
cycles	3.00	3.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	6.67	6.67	6.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.75
Overall L1	6.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

26% of peak load performance is reached (25.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 48cce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 48ccb8 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48ccf0 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48cac0 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 48cd78 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 48cd40 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 48cce0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code