OV - exec - Loop 3821

  (3820) 0x4ab688 ADD	X8, X8, #1

  (3820) 0x4ab68c CMP	X8, X22

  (3820) 0x4ab690 B.EQ	4ab824

  (3820) 0x4ab694 LDR	X16, [X26, X8,LSL #3]

  (3820) 0x4ab698 LDR	X14, [X10, X8,LSL #3]

  (3820) 0x4ab69c CMP	X14, X16

  (3820) 0x4ab6a0 B.LE	4ab688

0x4ab6a4 SUB	W15, W14, W16

0x4ab6a8 ADD	X13, X16, #1

0x4ab6ac TBZ	W15, #0, 4ab6cc

0x4ab6cc CMP	X14, X13

0x4ab6d0 B.EQ	4ab688

0x4ab6d4 UBFM	X15, X16, #61, #60

0x4ab6d8 SUB	X14, X14, X16

0x4ab6dc ADD	X13, X11, X15

0x4ab6e0 ADD	X15, X12, X15

  (3822) 0x4ab6e4 LDUR	X16, [X15, #504]

  (3822) 0x4ab6e8 LDUR	D0, [X13, #504]

  (3822) 0x4ab6ec LDR	D1, [X21, X8,LSL #3]

  (3822) 0x4ab6f0 SUBS	X14, X14, #2

  (3822) 0x4ab6f4 LDR	D2, [X9, X16,LSL #3]

  (3822) 0x4ab6f8 FMADD	D0, D1, D0, D2

  (3822) 0x4ab6fc STR	D0, [X9, X16,LSL #3]

  (3822) 0x4ab700 LDR	X16, [X15], #16

  (3822) 0x4ab704 LDR	D1, [X21, X8,LSL #3]

  (3822) 0x4ab708 LDR	D0, [X13], #16

  (3822) 0x4ab70c LDR	D2, [X9, X16,LSL #3]

  (3822) 0x4ab710 FMADD	D0, D1, D0, D2

  (3822) 0x4ab714 STR	D0, [X9, X16,LSL #3]

  (3822) 0x4ab718 B.NE	4ab6e4

0x4ab71c B	4ab688

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 608 - 615

--------------------------------------------------------------------------------

608:       for (i = 0; i < num_rows; i++)

609:       {

610:          if ( num_vectors==1 )

611:          {

612:             for (jj = A_i[i]; jj < A_i[i+1]; jj++)

613:             {

614:                j = A_j[jj];

615:                y_data[j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module
►92.31+	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:432	exec
○	hypre_BoomerAMGCycle	par_cycle.c:431	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec
►7.69+	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:432	exec
○	hypre_BoomerAMGCycle	par_cycle.c:431	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P2, P3, P4, P5,
Function	hypre_CSRMatrixMatvecT
Source	csr_matvec.c:612-612
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	0.44
Front-end cycles	1.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P2, P3, P4, P5,
Function	hypre_CSRMatrixMatvecT
Source	csr_matvec.c:612-612
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	0.44
Front-end cycles	1.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecT
Source file and lines	csr_matvec.c:608-615
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:608-615.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:612.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.75 to 0.44 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.75 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 4ab6cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
SUB W15, W14, W16	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X13, X16, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
TBZ W15, #0, 4ab6cc <hypre_CSRMatrixMatvecT+0x39c>	1	0.50	0.50	0	0	0	0	1	0.50
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.EQ 4ab688 <hypre_CSRMatrixMatvecT+0x358>	1	0.50	0.50	0	0	0	0	1	0.50
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUB X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X13, X11, X15	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X15, X12, X15	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B 4ab688 <hypre_CSRMatrixMatvecT+0x358>	1	0.50	0.50	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecT
Source file and lines	csr_matvec.c:608-615
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:608-615.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:612.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.75 to 0.44 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.75 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 4ab6cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
SUB W15, W14, W16	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X13, X16, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
TBZ W15, #0, 4ab6cc <hypre_CSRMatrixMatvecT+0x39c>	1	0.50	0.50	0	0	0	0	1	0.50
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.EQ 4ab688 <hypre_CSRMatrixMatvecT+0x358>	1	0.50	0.50	0	0	0	0	1	0.50
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUB X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X13, X11, X15	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X15, X12, X15	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B 4ab688 <hypre_CSRMatrixMatvecT+0x358>	1	0.50	0.50	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code