OV - exec - Loop 3027

	Loop Id: 3027	Module: exec	Source: ams.c:602-611	Coverage: 0.06%

0x4783c8 CMP	X12, X27

0x4783cc B.EQ	478988

0x4783d0 ORR	X15, XZR, X12

0x4783d4 ORR	X1, XZR, X8

0x4783d8 UBFM	X8, X12, #61, #60

0x4783dc ADD	X12, X12, #1

0x4783e0 MOVI	D1, #0

0x4783e4 ADD	X16, X20, X8

0x4783e8 ADD	X17, X9, X8

0x4783ec LDR	X8, [X19, X12,LSL #3]

0x4783f0 SUBS	X18, X8, X1

0x4783f4 STR	XZR, [X16]

0x4783f8 B.LE	478578

0x4783fc CMP	X13, #8

0x478400 MOVI	D1, #0

0x478404 CSEL	X0, X13, X14, #8

0x478408 CMP	X18, X0

0x47840c B.CC	478500

0x478410 ADD	X2, X28, X8,LSL #3

0x478414 ADD	X0, X28, X1,LSL #3

0x478418 CMP	X16, X2

0x47841c CCMP	X0, X17, #2, #3

0x478420 B.CC	478500

0x478424 UDIV	X0, X18, X13

0x478428 UBFM	X4, X1, #61, #60

0x47842c ORR	X2, XZR, XZR

0x478430 ORR	Z1.D, Z0.D, Z0.D

0x478434 ORR	Z2.D, Z0.D, Z0.D

0x478438 MADD	X3, X0, X13, XZR

0x47843c SUB	X0, X18, X3

0x478440 ADD	X18, X1, X3

0x478444 ADD	X1, X28, X4

0x478448 ADDVL	X4, X4, #1

0x47844c ADD	X4, X28, X4

0x478450 HINT	#0

0x478454 HINT	#0

0x478458 HINT	#0

0x47845c HINT	#0

  (3030) 0x478460 LD1D	{Z3.D}, P0/Z, [X1, X2,LSL #3]

  (3030) 0x478464 LD1D	{Z4.D}, P0/Z, [X4, X2,LSL #3]

  (3030) 0x478468 ADD	X2, X2, X13

  (3030) 0x47846c CMP	X3, X2

  (3030) 0x478470 FABS	Z3.D, P0/M, Z3.D

  (3030) 0x478474 FABS	Z4.D, P0/M, Z4.D

  (3030) 0x478478 FADD	Z1.D, Z1.D, Z3.D

  (3030) 0x47847c FADD	Z2.D, Z2.D, Z4.D

  (3030) 0x478480 B.NE	478460

0x478484 FADD	Z1.D, Z2.D, Z1.D

0x478488 FADDV	D1, P0, Z1.D

0x47848c STR	D1, [X20, X15,LSL #3]

0x478490 CBZ	X0, 478578

0x4784ac ORR	X0, XZR, X18

0x4784b0 HINT	#0

0x4784b4 HINT	#0

0x4784b8 HINT	#0

0x4784bc HINT	#0

  (3028) 0x4784c0 LDR	D2, [X28, X0,LSL #3]

  (3028) 0x4784c4 ADD	X0, X0, #1

  (3028) 0x4784c8 SUBS	X1, X1, #1

  (3028) 0x4784cc FABS	D2, D2

  (3028) 0x4784d0 FADD	D1, D1, D2

  (3028) 0x4784d4 STR	D1, [X20, X15,LSL #3]

  (3028) 0x4784d8 B.NE	4784c0

0x4784dc ORN	X18, XZR, X18

0x4784e0 ADD	X18, X8, X18

0x4784e4 CMP	X18, #3

0x4784e8 B.CC	478578

0x4784ec B	478524

0x478500 ORR	X18, XZR, X1

0x478504 SUB	W0, W8, W18

0x478508 ANDS	X1, X0, #4160

0x47850c B.NE	4784ac

0x478510 ORR	X0, XZR, X18

0x478514 ORN	X18, XZR, X18

0x478518 ADD	X18, X8, X18

0x47851c CMP	X18, #3

0x478520 B.CC	478578

0x478524 SUB	X18, X8, X0

0x478528 ADD	X0, X10, X0,LSL #3

  (3029) 0x47852c LDUR	D2, [X0, #496]

  (3029) 0x478530 SUBS	X18, X18, #4

  (3029) 0x478534 FABS	D2, D2

  (3029) 0x478538 FADD	D1, D1, D2

  (3029) 0x47853c STR	D1, [X20, X15,LSL #3]

  (3029) 0x478540 LDUR	D2, [X0, #504]

  (3029) 0x478544 FABS	D2, D2

  (3029) 0x478548 FADD	D1, D1, D2

  (3029) 0x47854c STR	D1, [X20, X15,LSL #3]

  (3029) 0x478550 LDR	D2, [X0]

  (3029) 0x478554 FABS	D2, D2

  (3029) 0x478558 FADD	D1, D1, D2

  (3029) 0x47855c STR	D1, [X20, X15,LSL #3]

  (3029) 0x478560 LDR	D2, [X0, #8]

  (3029) 0x478564 ADD	X0, X0, #32

  (3029) 0x478568 FABS	D2, D2

  (3029) 0x47856c FADD	D1, D1, D2

  (3029) 0x478570 STR	D1, [X20, X15,LSL #3]

  (3029) 0x478574 B.NE	47852c

0x478578 CBZ	X26, 4783c8

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 602 - 611

--------------------------------------------------------------------------------

602:       for (i = 0; i < num_rows; i++)

603:       {

604:          l1_norm[i] = 0.0;

605:          if (cf_marker == NULL)

606:          {

607:             /* Add the l1 norm of the diag part of the ith row */

608:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

609:                l1_norm[i] += fabs(A_diag_data[j]);

610:             /* Add the l1 norm of the offd part of the ith row */

611:             if (num_cols_offd)

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:1358	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec

Path /

Metric	Value
CQA speedup if no scalar integer	3.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	hypre_ParCSRComputeL1Norms
Source	ams.c:602-604,ams.c:608-608,ams.c:611-611
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	5.00
Front-end cycles	7.00
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	56.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.86
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.59
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.90
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	16.67
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.76
Vector-efficiency ratio all	34.68
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.82

Metric	Value
CQA speedup if no scalar integer	3.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	hypre_ParCSRComputeL1Norms
Source	ams.c:602-604,ams.c:608-608,ams.c:611-611
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	5.00
Front-end cycles	7.00
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	56.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.86
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.59
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	12.90
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	16.67
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.76
Vector-efficiency ratio all	34.68
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.82

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1Norms
Source file and lines	ams.c:602-611
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:602-611.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:602-604,608,611.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 2.50 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.25 to 5.00 cycles (1.85x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
16% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 8 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.25	9.25	9.25	9.25	2.50	2.50	1.50	1.50	1.00	1.00	1.00	0.50	0.50
cycles	5.00	5.00	9.25	9.25	9.25	9.25	2.50	2.50	1.50	1.50	1.00	1.00	1.00	0.50	0.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.00
Overall L1	9.25

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

0% of peak load performance is reached (0.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4783c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X12, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 478988 <hypre_ParCSRComputeL1Norms+0x1118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X16, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X18, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR XZR, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSEL X0, X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478500 <hypre_ParCSRComputeL1Norms+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X28, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X28, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X0, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 478500 <hypre_ParCSRComputeL1Norms+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X0, X18, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X3, X0, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X0, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
FADD Z1.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D1, P0, Z1.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
STR D1, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X0, 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 478524 <hypre_ParCSRComputeL1Norms+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W8, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4784ac <hypre_ParCSRComputeL1Norms+0xc3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X26, 4783c8 <hypre_ParCSRComputeL1Norms+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRComputeL1Norms
Source file and lines	ams.c:602-611
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 2.50 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
16% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 8 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.25	9.25	9.25	9.25	2.50	2.50	1.50	1.50	1.00	1.00	1.00	0.50	0.50
cycles	5.00	5.00	9.25	9.25	9.25	9.25	2.50	2.50	1.50	1.50	1.00	1.00	1.00	0.50	0.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	7.00
Overall L1	9.25

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

0% of peak load performance is reached (0.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4783c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X12, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 478988 <hypre_ParCSRComputeL1Norms+0x1118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X16, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X18, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR XZR, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LE 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CSEL X0, X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478500 <hypre_ParCSRComputeL1Norms+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X28, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X28, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X0, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 478500 <hypre_ParCSRComputeL1Norms+0xc90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X0, X18, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR Z2.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X3, X0, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X0, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X4, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X28, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
FADD Z1.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FADDV D1, P0, Z1.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2
STR D1, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X0, 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 478524 <hypre_ParCSRComputeL1Norms+0xcb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W8, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4784ac <hypre_ParCSRComputeL1Norms+0xc3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 478578 <hypre_ParCSRComputeL1Norms+0xd08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X26, 4783c8 <hypre_ParCSRComputeL1Norms+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code