OV - exec - Loop 2928

0x475d80 LD1D	{Z0.D}, P0/Z, [X15, X9,LSL #3]    [4]

0x475d84 LD1D	{Z1.D}, P0/Z, [X11, X9,LSL #3]    [6]

0x475d88 LD1D	{Z2.D}, P0/Z, [X14, X9,LSL #3]    [5]

0x475d8c FDIV	Z0.D, P0/M, Z0.D, Z2.D

0x475d90 LD1D	{Z3.D}, P0/Z, [X12, X9,LSL #3]    [2]

0x475d94 FDIV	Z1.D, P0/M, Z1.D, Z3.D

0x475d98 LD1D	{Z2.D}, P0/Z, [X28, X9,LSL #3]    [3]

0x475d9c LD1D	{Z3.D}, P0/Z, [X13, X9,LSL #3]    [1]

0x475da0 FADD	Z0.D, Z2.D, Z0.D

0x475da4 FADD	Z1.D, Z3.D, Z1.D

0x475da8 ST1D	{Z0.D}, P0, [X28, X9,LSL #3]    [3]

0x475dac ST1D	{Z1.D}, P0, [X13, X9,LSL #3]    [1]

0x475db0 ADD	X9, X9, X27

0x475db4 CMP	X8, X9

0x475db8 B.NE	475d80

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 78 - 79

--------------------------------------------------------------------------------

78:          for (i = 0; i < num_rows; i++)

79:             u_data[i] += v_data[i] / l1_norms[i];

Coverage (%)	Name	Source Location	Module
►95.08+	hypre_BoomerAMGCycle	par_cycle.c:322	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec
►4.92+	hypre_BoomerAMGCycle	par_cycle.c:322	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	hypre_ParCSRRelax
Source	ams.c:78-79
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	1.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P10, P11,
Function	hypre_ParCSRRelax
Source	ams.c:78-79
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	1.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelax
Source file and lines	ams.c:78-79
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:78-79.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: divide

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	2.00	2.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	2.00	2.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.88
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 475d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P0/Z, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z3.D}, P0/Z, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z2.D}, P0/Z, [X28, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X28, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z1.D}, P0, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 475d80 <hypre_ParCSRRelax+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRRelax
Source file and lines	ams.c:78-79
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:78-79.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: divide

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	2.00	2.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	2.00	2.00	1.00	1.00	4.00	4.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.88
Data deps.	1.00
Overall L1	4.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 475d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P0/Z, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z3.D}, P0/Z, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
LD1D {Z2.D}, P0/Z, [X28, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X28, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z1.D}, P0, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X9, X9, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 475d80 <hypre_ParCSRRelax+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code