OV - exec - Loop 1242

0x438300 LDUR	X15, [X3, #504]    [6]

0x438304 LDR	D0, [X26, X9,LSL #3]    [3]

0x438308 LDUR	D3, [X1, #504]    [5]

0x43830c SUBS	X0, X0, #2

0x438310 FMUL	D0, D3, D0

0x438314 LDR	X15, [X21, X15,LSL #3]    [2]

0x438318 LDR	D3, [X27, X15,LSL #3]    [4]

0x43831c FADD	D2, D0, D2

0x438320 FADD	D1, D0, D1

0x438324 FADD	D3, D3, D0

0x438328 STR	D3, [X27, X15,LSL #3]    [4]

0x43832c LDR	X15, [X3], #16    [6]

0x438330 LDR	D0, [X26, X9,LSL #3]    [3]

0x438334 LDR	D3, [X1], #16    [5]

0x438338 FMUL	D0, D3, D0

0x43833c LDR	X15, [X21, X15,LSL #3]    [7]

0x438340 LDR	D3, [X27, X15,LSL #3]    [1]

0x438344 FADD	D2, D0, D2

0x438348 FADD	D1, D0, D1

0x43834c FADD	D3, D3, D0

0x438350 STR	D3, [X27, X15,LSL #3]    [1]

0x438354 B.NE	438300

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1816 - 1822

--------------------------------------------------------------------------------

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..22#0x437c60
Source	par_multi_interp.c:1816-1822
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	2.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..22#0x437c60
Source	par_multi_interp.c:1816-1822
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	1.00
Front-end cycles	2.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..22#0x437c60
Source file and lines	par_multi_interp.c:1816-1822
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1816-1822.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.75
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDUR X15, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D3, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUBS X0, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D0, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR X15, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X15, [X3], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X1], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D0, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR X15, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 438300 <.omp_outlined..22+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..22#0x437c60
Source file and lines	par_multi_interp.c:1816-1822
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1816-1822.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	4.00	4.00	4.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	2.75
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDUR X15, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D3, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUBS X0, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D0, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR X15, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X15, [X3], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X1], #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D0, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR X15, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D3, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X27, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 438300 <.omp_outlined..22+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code