OV - exec - Loop 1042

0x4aa0ec STR	D0, [X12, X20,LSL #3]

0x4aa0f0 ORR	X20, XZR, X18

0x4aa0f4 CMP	X18, X19

0x4aa0f8 B.EQ	4ab304

0x4aa0fc ADD	X18, X20, #1

0x4aa100 ORR	X3, XZR, X14

0x4aa104 MOVI	D0, #0

0x4aa108 LDR	X14, [X8, X18,LSL #3]

0x4aa10c SUBS	X1, X14, X3

0x4aa110 B.LE	4aa0ec

0x4aa114 MOVI	D0, #0

0x4aa118 CMP	X1, #2

0x4aa11c B.CS	4aa128

0x4aa120 ORR	X0, XZR, X3

0x4aa124 B	4aa17c

0x4aa128 AND	X2, X1, #8127

0x4aa12c UBFM	X4, X3, #61, #60

0x4aa130 MOVI	D0, #0

0x4aa134 MOVI	D1, #0

0x4aa138 ADD	X0, X3, X2

0x4aa13c ADD	X3, X13, X4

0x4aa140 ADD	X4, X15, X4

0x4aa144 ORR	X5, XZR, X2

  (1043) 0x4aa148 LDP	X6, X7, [X3, #1016]

  (1043) 0x4aa14c LDP	D2, D3, [X4, #1016]

  (1043) 0x4aa150 SUBS	X5, X5, #2

  (1043) 0x4aa154 ADD	X3, X3, #16

  (1043) 0x4aa158 ADD	X4, X4, #16

  (1043) 0x4aa15c LDR	D4, [X10, X6,LSL #3]

  (1043) 0x4aa160 LDR	D5, [X10, X7,LSL #3]

  (1043) 0x4aa164 FMADD	D0, D4, D2, D0

  (1043) 0x4aa168 FMADD	D1, D5, D3, D1

  (1043) 0x4aa16c B.NE	4aa148

0x4aa170 FADD	D0, D1, D0

0x4aa174 CMP	X1, X2

0x4aa178 B.EQ	4aa0ec

0x4aa17c SUB	W1, W14, W0

0x4aa180 ANDS	X2, X1, #4160

0x4aa184 B.EQ	4aa1bc

0x4aa188 ORR	X1, XZR, X0

  (1045) 0x4aa18c LDR	X3, [X11, X1,LSL #3]

  (1045) 0x4aa190 LDR	D1, [X9, X1,LSL #3]

  (1045) 0x4aa194 ADD	X1, X1, #1

  (1045) 0x4aa198 SUBS	X2, X2, #1

  (1045) 0x4aa19c LDR	D2, [X10, X3,LSL #3]

  (1045) 0x4aa1a0 FMADD	D0, D2, D1, D0

  (1045) 0x4aa1a4 B.NE	4aa18c

0x4aa1a8 ORN	X0, XZR, X0

0x4aa1ac ADD	X0, X14, X0

0x4aa1b0 CMP	X0, #3

0x4aa1b4 B.CC	4aa0ec

0x4aa1b8 B	4aa1d0

0x4aa1bc ORR	X1, XZR, X0

0x4aa1c0 ORN	X0, XZR, X0

0x4aa1c4 ADD	X0, X14, X0

0x4aa1c8 CMP	X0, #3

0x4aa1cc B.CC	4aa0ec

0x4aa1d0 UBFM	X2, X1, #61, #60

0x4aa1d4 SUB	X0, X14, X1

0x4aa1d8 ADD	X1, X16, X2

0x4aa1dc ADD	X2, X17, X2

  (1044) 0x4aa1e0 LDP	X3, X4, [X2, #1008]

  (1044) 0x4aa1e4 LDP	D2, D3, [X1, #1008]

  (1044) 0x4aa1e8 SUBS	X0, X0, #4

  (1044) 0x4aa1ec LDR	D1, [X10, X3,LSL #3]

  (1044) 0x4aa1f0 FMADD	D0, D1, D2, D0

  (1044) 0x4aa1f4 LDR	D1, [X10, X4,LSL #3]

  (1044) 0x4aa1f8 FMADD	D0, D1, D3, D0

  (1044) 0x4aa1fc LDP	X3, X4, [X2], #32

  (1044) 0x4aa200 LDR	D2, [X10, X3,LSL #3]

  (1044) 0x4aa204 LDP	D1, D3, [X1], #32

  (1044) 0x4aa208 FMADD	D0, D2, D1, D0

  (1044) 0x4aa20c LDR	D1, [X10, X4,LSL #3]

  (1044) 0x4aa210 FMADD	D0, D1, D3, D0

  (1044) 0x4aa214 B.NE	4aa1e0

0x4aa218 B	4aa0ec

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 256 - 263

--------------------------------------------------------------------------------

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..18#0x4a9fb0
Source	csr_matvec.c:256-256,csr_matvec.c:259-259,csr_matvec.c:263-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.50
Front-end cycles	5.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.14
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.29
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.52
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..18#0x4a9fb0
Source	csr_matvec.c:256-256,csr_matvec.c:259-259,csr_matvec.c:263-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.50
Front-end cycles	5.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.14
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.29
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.52
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..18#0x4a9fb0
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256,259,263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.50 cycles (4.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	7.00	7.00	7.00	7.00	1.50	1.50	1.50	1.50	0.83	0.50	0.67	0.00	0.00
cycles	5.00	5.00	7.00	7.00	7.00	7.00	1.50	1.50	1.50	1.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.63
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4aa0fc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
STR D0, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ORR X20, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4ab304 <.omp_outlined..18+0x1354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X14, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUBS X1, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CS 4aa128 <.omp_outlined..18+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 4aa17c <.omp_outlined..18+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X2, X1, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X4, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X0, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X13, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X15, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W1, W14, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X2, X1, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4aa1bc <.omp_outlined..18+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X0, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4aa1d0 <.omp_outlined..18+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X0, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..18#0x4a9fb0
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256,259,263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.50 cycles (4.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	7.00	7.00	7.00	7.00	1.50	1.50	1.50	1.50	0.83	0.50	0.67	0.00	0.00
cycles	5.00	5.00	7.00	7.00	7.00	7.00	1.50	1.50	1.50	1.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.63
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

1% of peak load performance is reached (1.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4aa0fc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
STR D0, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ORR X20, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4ab304 <.omp_outlined..18+0x1354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X14, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUBS X1, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CS 4aa128 <.omp_outlined..18+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 4aa17c <.omp_outlined..18+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X2, X1, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X4, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X0, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X13, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X15, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D0, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W1, W14, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X2, X1, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4aa1bc <.omp_outlined..18+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X0, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4aa1d0 <.omp_outlined..18+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X0, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.CC 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 4aa0ec <.omp_outlined..18+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code