OV - exec - Function .omp_outlined..21#0x4a3c60

	Function: .omp_outlined..21#0x4a3c60	Module: exec	Source: IJVector_parcsr.c:440-443	Coverage: 0.03%

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c: 440 - 443

--------------------------------------------------------------------------------

440: #pragma omp parallel for private(j) HYPRE_SMP_SCHEDULE

441: #endif

442:       for (j = 0; j < num_values; j++)

443:          data[j] = values[j];

0x4a3c60 SUB	SP, SP, #96

0x4a3c64 STP	X29, X30, [SP, #48]

0x4a3c68 STP	X22, X21, [SP, #64]

0x4a3c6c STP	X20, X19, [SP, #80]

0x4a3c70 ADD	X29, SP, #48

0x4a3c74 LDR	X8, [X2]

0x4a3c78 SUBS	X22, X8, #1

0x4a3c7c B.LT	4a3e00

0x4a3c80 LDR	W19, [X0]

0x4a3c84 LDR	X21, [X3]

0x4a3c88 LDR	X20, [X4]

0x4a3c8c MOVZ	W8, #1

0x4a3c90 ADRP	X0,

0x4a3c94 ADD	X0, X0, #4008

0x4a3c98 ADD	X3, SP, #20

0x4a3c9c SUB	X4, X29, #8

0x4a3ca0 STP	X22, XZR, [X29, #1008]

0x4a3ca4 SUB	X5, X29, #16

0x4a3ca8 ADD	X6, SP, #24

0x4a3cac MOVZ	W2, #34

0x4a3cb0 STR	X8, [SP, #24]

0x4a3cb4 STR	WZR, [SP, #20]

0x4a3cb8 STR	X8, [SP]

0x4a3cbc MOVZ	W7, #1

0x4a3cc0 ORR	W1, WZR, W19

0x4a3cc4 BL	40f860

0x4a3cc8 LDP	X8, X9, [X29, #1008]

0x4a3ccc CMP	X8, X22

0x4a3cd0 CSEL	X8, X8, X22, #11

0x4a3cd4 CMP	X9, X8

0x4a3cd8 B.GT	4a3df0

0x4a3cdc SUB	X10, X8, X9

0x4a3ce0 MOVZ	W11, #16

0x4a3ce4 ADD	X12, X10, #1

0x4a3ce8 CNTW	X10, ALL

0x4a3cec CMP	X10, #16

0x4a3cf0 CSEL	X11, X10, X11, #8

0x4a3cf4 CMP	X12, X11

0x4a3cf8 B.CC	4a3d68

0x4a3cfc UBFM	X16, X9, #61, #60

0x4a3d00 RDVL	X11, #1

0x4a3d04 ADD	X13, X16, X21

0x4a3d08 ADD	X14, X16, X20

0x4a3d0c UBFM	X11, X11, #4, #63

0x4a3d10 SUB	X13, X13, X14

0x4a3d14 CMP	X13, X11,LSL #5

0x4a3d18 B.CC	4a3d68

0x4a3d1c UDIV	X13, X12, X10

0x4a3d20 ADDVL	X17, X16, #1

0x4a3d24 ORR	X11, XZR, XZR

0x4a3d28 ADD	X14, X20, X16

0x4a3d2c ADD	X15, X21, X16

0x4a3d30 PTRUE	P0.D, ALL

0x4a3d34 ADD	X16, X21, X17

0x4a3d38 ADD	X17, X20, X17

0x4a3d3c MADD	X13, X13, X10, XZR

0x4a3d40 SUB	X12, X12, X13

0x4a3d44 ADD	X9, X9, X13

(533) 0x4a3d48 LD1D	{Z0.D}, P0/Z, [X14, X11,LSL #3]

(533) 0x4a3d4c LD1D	{Z1.D}, P0/Z, [X17, X11,LSL #3]

(533) 0x4a3d50 ST1D	{Z0.D}, P0, [X15, X11,LSL #3]

(533) 0x4a3d54 ST1D	{Z1.D}, P0, [X16, X11,LSL #3]

(533) 0x4a3d58 ADD	X11, X11, X10

(533) 0x4a3d5c CMP	X13, X11

(533) 0x4a3d60 B.NE	4a3d48

0x4a3d64 CBZ	X12, 4a3df0

0x4a3d68 SUB	W10, W8, W9

0x4a3d6c ADD	W11, W10, #1

0x4a3d70 SUB	X10, X8, X9

0x4a3d74 ANDS	X11, X11, #4160

0x4a3d78 B.EQ	4a3d94

0x4a3d7c HINT	#0

(532) 0x4a3d80 LDR	D0, [X20, X9,LSL #3]

(532) 0x4a3d84 SUBS	X11, X11, #1

(532) 0x4a3d88 STR	D0, [X21, X9,LSL #3]

(532) 0x4a3d8c ADD	X9, X9, #1

(532) 0x4a3d90 B.NE	4a3d80

0x4a3d94 CMP	X10, #3

0x4a3d98 B.CC	4a3df0

0x4a3d9c UBFM	X10, X9, #61, #60

0x4a3da0 SUB	X8, X8, X9

0x4a3da4 ADD	X11, X10, #16

0x4a3da8 ADD	X10, X21, X11

0x4a3dac ADD	X11, X20, X11

0x4a3db0 ADD	X8, X8, #1

0x4a3db4 HINT	#0

0x4a3db8 HINT	#0

0x4a3dbc HINT	#0

(531) 0x4a3dc0 LDUR	D0, [X11, #496]

(531) 0x4a3dc4 SUBS	X8, X8, #4

(531) 0x4a3dc8 STUR	D0, [X10, #496]

(531) 0x4a3dcc LDUR	D0, [X11, #504]

(531) 0x4a3dd0 STUR	D0, [X10, #504]

(531) 0x4a3dd4 LDR	D0, [X11]

(531) 0x4a3dd8 STR	D0, [X10]

(531) 0x4a3ddc LDR	D0, [X11, #8]

(531) 0x4a3de0 ADD	X11, X11, #32

(531) 0x4a3de4 STR	D0, [X10, #8]

(531) 0x4a3de8 ADD	X10, X10, #32

(531) 0x4a3dec B.NE	4a3dc0

0x4a3df0 ORR	W1, WZR, W19

0x4a3df4 ADRP	X0,

0x4a3df8 ADD	X0, X0, #4032

0x4a3dfc BL	40f770

0x4a3e00 LDP	X20, X19, [SP, #80]

0x4a3e04 LDP	X22, X21, [SP, #64]

0x4a3e08 LDP	X29, X30, [SP, #48]

0x4a3e0c ADD	SP, SP, #96

0x4a3e10 RET

0x4a3e14 HINT	#0

0x4a3e18 HINT	#0

0x4a3e1c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJVector_parcsr.c:440-443
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c:440-443.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 1.00 cycles (14.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.50 to 7.62 cycles (1.90x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.50 to 1.00 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 92 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.50	14.50	14.50	14.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	3.50	3.50
cycles	5.00	5.00	14.50	14.50	14.50	14.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	3.50	3.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.13
Overall L1	14.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

6% of peak load performance is reached (6.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a3c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X22, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a3e00 <.omp_outlined..21+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eec90>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4008	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X22, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f860 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X11, X10, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a3d68 <.omp_outlined..21+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X16, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X11, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X11,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 4a3d68 <.omp_outlined..21+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X13, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADDVL X17, X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X13, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X12, 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W10, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X11, X11, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a3d94 <.omp_outlined..21+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eedf4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f770 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	IJVector_parcsr.c:440-443
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c:440-443.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.50 to 1.00 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 92 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	14.50	14.50	14.50	14.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	3.50	3.50
cycles	5.00	5.00	14.50	14.50	14.50	14.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	3.50	3.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.13
Overall L1	14.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

6% of peak load performance is reached (6.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a3c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X22, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a3e00 <.omp_outlined..21+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eec90>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4008	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X22, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f860 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X8, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X11, X10, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a3d68 <.omp_outlined..21+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X16, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X11, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X11,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.CC 4a3d68 <.omp_outlined..21+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X13, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADDVL X17, X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X13, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X12, 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W10, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X11, X11, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a3d94 <.omp_outlined..21+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a3df0 <.omp_outlined..21+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eedf4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f770 <@plt_start@+0x520>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..21#0x4a3c60–	0.03	0
○Loop 533 - IJVector_parcsr.c:443-443 - exec	0.03	0
○Loop 532 - IJVector_parcsr.c:442-443 - exec	0	0
○Loop 531 - IJVector_parcsr.c:442-443 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code