OV - exec - Loop 786

0x435c8c LDUR	X10, [X29, #456]

0x435c90 ADD	X18, X18, #1

0x435c94 CMP	X18, X10

0x435c98 B.GE	435ec4

0x435c9c LDUR	X10, [X29, #424]

0x435ca0 LDR	X1, [X10, X18,LSL #3]

0x435ca4 STR	X8, [X11, X1,LSL #3]

0x435ca8 STR	X9, [X12, X1,LSL #3]

0x435cac ADD	X2, X1, #1

0x435cb0 LDR	X3, [X13, X1,LSL #3]

0x435cb4 LDR	X10, [X13, X2,LSL #3]

0x435cb8 CMP	X3, X10

0x435cbc B.GE	435dc0

0x435cc0 LDP	X10, X5, [X29, #984]

0x435cc4 LDR	X4, [X10]

0x435cc8 LDP	X6, X10, [X29, #1000]

0x435ccc LDR	X5, [X5]

0x435cd0 LDR	X10, [X10]

0x435cd4 LDR	X7, [X6]

0x435cd8 SUB	X6, X10, #8

0x435cdc SUB	X7, X7, #8

0x435ce0 B	435cf4

  (790) 0x435ce4 LDR	X10, [X13, X2,LSL #3]

  (790) 0x435ce8 ADD	X3, X3, #1

  (790) 0x435cec CMP	X3, X10

  (790) 0x435cf0 B.GE	435dc0

  (790) 0x435cf4 LDR	X10, [X14, X3,LSL #3]

  (790) 0x435cf8 LDR	X20, [X21]

  (790) 0x435cfc LDR	X19, [X15, X10,LSL #3]

  (790) 0x435d00 SUB	X20, X20, #1

  (790) 0x435d04 CMP	X19, X20

  (790) 0x435d08 B.NE	435ce4

  (790) 0x435d0c ADD	X26, X10, #1

  (790) 0x435d10 LDR	X19, [X4, X26,LSL #3]

  (790) 0x435d14 CMP	X19, #1

  (790) 0x435d18 B.LT	435d64

  (790) 0x435d1c LDR	X25, [X11, X10,LSL #3]

  (790) 0x435d20 ADD	X28, X19, X25

  (790) 0x435d24 B	435d34

    (792) 0x435d28 ADD	X25, X25, #1

    (792) 0x435d2c CMP	X25, X28

    (792) 0x435d30 B.GE	435d64

    (792) 0x435d34 LDR	X19, [X21]

    (792) 0x435d38 LDR	X19, [X6, X19,LSL #3]

    (792) 0x435d3c LDR	X20, [X19, X25,LSL #3]

    (792) 0x435d40 LDR	X19, [X22, X20,LSL #3]

    (792) 0x435d44 CMP	X19, X1

    (792) 0x435d48 B.EQ	435d28

    (792) 0x435d4c LDR	X19, [X4, X2,LSL #3]

    (792) 0x435d50 ADD	X8, X8, #1

    (792) 0x435d54 ADD	X19, X19, #1

    (792) 0x435d58 STR	X19, [X4, X2,LSL #3]

    (792) 0x435d5c STR	X1, [X22, X20,LSL #3]

    (792) 0x435d60 B	435d28

  (790) 0x435d64 LDR	X19, [X5, X26,LSL #3]

  (790) 0x435d68 CMP	X19, #1

  (790) 0x435d6c B.LT	435ce4

  (790) 0x435d70 LDR	X10, [X12, X10,LSL #3]

  (790) 0x435d74 ADD	X25, X19, X10

  (790) 0x435d78 B	435d8c

    (791) 0x435d80 ADD	X10, X10, #1

    (791) 0x435d84 CMP	X10, X25

    (791) 0x435d88 B.GE	435ce4

    (791) 0x435d8c LDR	X19, [X21]

    (791) 0x435d90 LDR	X19, [X7, X19,LSL #3]

    (791) 0x435d94 LDR	X20, [X19, X10,LSL #3]

    (791) 0x435d98 LDR	X19, [X23, X20,LSL #3]

    (791) 0x435d9c CMP	X19, X1

    (791) 0x435da0 B.EQ	435d80

    (791) 0x435da4 LDR	X19, [X5, X2,LSL #3]

    (791) 0x435da8 ADD	X9, X9, #1

    (791) 0x435dac ADD	X19, X19, #1

    (791) 0x435db0 STR	X19, [X5, X2,LSL #3]

    (791) 0x435db4 STR	X1, [X23, X20,LSL #3]

    (791) 0x435db8 B	435d80

0x435dc0 LDR	X3, [X16, X1,LSL #3]

0x435dc4 LDR	X10, [X16, X2,LSL #3]

0x435dc8 CMP	X3, X10

0x435dcc B.GE	435c8c

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 976

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..12#0x435a10
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	1.25
Front-end cycles	3.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.20
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..12#0x435a10
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	1.25
Front-end cycles	3.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.20
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..12#0x435a10
Source file and lines	par_multi_interp.c:939-976
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 1.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	5.00	5.00	5.00	1.00	1.00
cycles	2.00	2.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	5.00	5.00	5.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Overall L1	5.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 435c8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435ec4 <.omp_outlined..12+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435dc0 <.omp_outlined..12+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X5, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X10, [X29, #1000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 435cf4 <.omp_outlined..12+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435c8c <.omp_outlined..12+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..12#0x435a10
Source file and lines	par_multi_interp.c:939-976
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 1.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	5.00	5.00	5.00	1.00	1.00
cycles	2.00	2.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	5.00	5.00	5.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Overall L1	5.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 435c8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435ec4 <.omp_outlined..12+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435dc0 <.omp_outlined..12+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X5, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X10, [X29, #1000]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 435cf4 <.omp_outlined..12+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 435c8c <.omp_outlined..12+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code