OV - exec - Loop 777

0x436140 LDP	X10, X24, [X29, #968]

0x436144 ADD	X24, X24, #1

0x436148 CMP	X24, X10

0x43614c B.GE	4363a4

0x436150 LDR	X18, [X26, X24,LSL #3]

0x436154 STUR	X24, [X29, #464]

0x436158 ADD	X17, X18, #1

0x43615c LDR	X0, [X11, X18,LSL #3]

0x436160 LDR	X10, [X11, X17,LSL #3]

0x436164 CMP	X0, X10

0x436168 B.GE	4362a4

0x43616c LDUR	X10, [X29, #408]

0x436170 ORN	X4, XZR, X18

0x436174 LDR	X1, [X10]

0x436178 LDUR	X10, [X29, #472]

0x43617c LDR	X2, [X10]

0x436180 LDUR	X10, [X29, #496]

0x436184 LDR	X3, [X10]

0x436188 LDUR	X10, [X29, #416]

0x43618c LDR	X5, [X10]

0x436190 LDUR	X10, [X29, #480]

0x436194 SUB	X26, X3, #8

0x436198 LDR	X6, [X10]

0x43619c LDUR	X10, [X29, #488]

0x4361a0 LDR	X7, [X10]

0x4361a4 SUB	X30, X7, #8

0x4361a8 B	4361bc

  (781) 0x4361ac LDR	X10, [X11, X17,LSL #3]

  (781) 0x4361b0 ADD	X0, X0, #1

  (781) 0x4361b4 CMP	X0, X10

  (781) 0x4361b8 B.GE	4362a0

  (781) 0x4361bc LDR	X10, [X12, X0,LSL #3]

  (781) 0x4361c0 LDR	X20, [X21]

  (781) 0x4361c4 LDR	X19, [X13, X10,LSL #3]

  (781) 0x4361c8 SUB	X20, X20, #1

  (781) 0x4361cc CMP	X19, X20

  (781) 0x4361d0 B.NE	4361ac

  (781) 0x4361d4 ADD	X25, X10, #1

  (781) 0x4361d8 LDR	X19, [X2, X25,LSL #3]

  (781) 0x4361dc CMP	X19, #1

  (781) 0x4361e0 B.LT	436240

  (781) 0x4361e4 LDR	X28, [X1, X10,LSL #3]

  (781) 0x4361e8 ADD	X20, X19, X28

  (781) 0x4361ec B	43620c

    (783) 0x436200 ADD	X28, X28, #1

    (783) 0x436204 CMP	X28, X20

    (783) 0x436208 B.GE	436240

    (783) 0x43620c LDR	X19, [X21]

    (783) 0x436210 LDR	X24, [X26, X19,LSL #3]

    (783) 0x436214 LDR	X24, [X24, X28,LSL #3]

    (783) 0x436218 LDR	X27, [X22, X24,LSL #3]

    (783) 0x43621c CMP	X27, X4

    (783) 0x436220 B.EQ	436200

    (783) 0x436224 LDR	X19, [X3, X19,LSL #3]

    (783) 0x436228 STR	X24, [X19, X8,LSL #3]

    (783) 0x43622c ADD	X8, X8, #1

    (783) 0x436230 STR	X4, [X22, X24,LSL #3]

    (783) 0x436234 B	436200

  (781) 0x436240 LDR	X19, [X6, X25,LSL #3]

  (781) 0x436244 CMP	X19, #1

  (781) 0x436248 B.LT	4361ac

  (781) 0x43624c LDR	X10, [X5, X10,LSL #3]

  (781) 0x436250 ADD	X20, X19, X10

  (781) 0x436254 B	43626c

    (782) 0x436260 ADD	X10, X10, #1

    (782) 0x436264 CMP	X10, X20

    (782) 0x436268 B.GE	4361ac

    (782) 0x43626c LDR	X19, [X21]

    (782) 0x436270 LDR	X24, [X30, X19,LSL #3]

    (782) 0x436274 LDR	X24, [X24, X10,LSL #3]

    (782) 0x436278 LDR	X25, [X23, X24,LSL #3]

    (782) 0x43627c CMP	X25, X4

    (782) 0x436280 B.EQ	436260

    (782) 0x436284 LDR	X19, [X7, X19,LSL #3]

    (782) 0x436288 STR	X24, [X19, X9,LSL #3]

    (782) 0x43628c ADD	X9, X9, #1

    (782) 0x436290 STR	X4, [X23, X24,LSL #3]

    (782) 0x436294 B	436260

0x4362a0 LDUR	X26, [X29, #424]

0x4362a4 LDR	X0, [X14, X18,LSL #3]

0x4362a8 LDR	X4, [X14, X17,LSL #3]

0x4362ac CMP	X0, X4

0x4362b0 B.GE	436140

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1104

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..12#0x435a10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.83
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	6.83
CQA cycles if fully vectorized	1.71
Front-end cycles	4.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.83
P10 cycles	6.50
P11 cycles	6.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.59
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..12#0x435a10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.83
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	6.83
CQA cycles if fully vectorized	1.71
Front-end cycles	4.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.83
P10 cycles	6.50
P11 cycles	6.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.59
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..12#0x435a10
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1104.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.83 to 1.71 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	0.50	0.50
cycles	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Overall L1	6.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.83 cycles. At this rate:

24% of peak load performance is reached (23.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X10, X24, [X29, #968]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4363a4 <.omp_outlined..12+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X26, X24,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X24, [X29, #464]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4362a4 <.omp_outlined..12+0x894>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORN X4, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X26, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4361bc <.omp_outlined..12+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X26, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 436140 <.omp_outlined..12+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..12#0x435a10
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1104.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.83 to 1.71 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	0.50	0.50
cycles	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Overall L1	6.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.83 cycles. At this rate:

24% of peak load performance is reached (23.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.17 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X10, X24, [X29, #968]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4363a4 <.omp_outlined..12+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X26, X24,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X24, [X29, #464]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4362a4 <.omp_outlined..12+0x894>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORN X4, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X26, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4361bc <.omp_outlined..12+0x7ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X26, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 436140 <.omp_outlined..12+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

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ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code