OV - exec - Loop 700

	Loop Id: 700	Module: exec	Source: par_strength.c:1253-1278 [...]	Coverage: 0.02%

0x4690a0 TBZ	W9, #0, 4690b8

0x4690a4 LDR	X8, [X10, X8,LSL #3]

0x4690a8 CMP	X8, #1

0x4690ac B.LT	4690b8

0x4690b0 ADD	X8, X11, #1

0x4690b4 STR	X8, [X29, #24]

0x4690b8 LDR	X2, [X23]

0x4690bc ORR	X1, XZR, X22

0x4690c0 ADD	X0, X29, #24

0x4690c4 BL	4b1100

0x4690c8 LDP	X9, X8, [SP]

0x4690cc CMP	X8, X9

0x4690d0 B.GE	469134

0x4690d4 LDR	X9, [X21]

0x4690d8 LDR	X10, [X20]

0x4690dc LDR	X11, [X19]

0x4690e0 MOVN	X12, #0

0x4690e4 B	4690fc

  (701) 0x4690e8 STR	X12, [X10, X8,LSL #3]

  (701) 0x4690ec LDR	X13, [SP]

  (701) 0x4690f0 ADD	X8, X8, #1

  (701) 0x4690f4 CMP	X8, X13

  (701) 0x4690f8 B.GE	469134

  (701) 0x4690fc LDR	X13, [X9, X8,LSL #3]

  (701) 0x469100 CMP	X13, #1

  (701) 0x469104 B.LT	4690e8

  (701) 0x469108 LDR	X13, [X29, #24]

  (701) 0x46910c STR	X13, [X10, X8,LSL #3]

  (701) 0x469110 LDR	X13, [X29, #24]

  (701) 0x469114 STR	X8, [X11, X13,LSL #3]

  (701) 0x469118 LDR	X13, [X29, #24]

  (701) 0x46911c ADD	X13, X13, #1

  (701) 0x469120 STR	X13, [X29, #24]

  (701) 0x469124 LDR	X13, [SP]

  (701) 0x469128 ADD	X8, X8, #1

  (701) 0x46912c CMP	X8, X13

  (701) 0x469130 B.LT	4690fc

0x469134 LDP	X20, X19, [SP, #64]

0x469138 LDP	X22, X21, [SP, #48]

0x46913c LDR	X23, [SP, #32]

0x469140 LDP	X29, X30, [SP, #16]

0x469144 ADD	SP, SP, #80

0x469148 RET

0x46914c ORR	X11, XZR, XZR

0x469150 AND	X12, X9, #8127

0x469154 B	46916c

0x469160 ADD	X8, X8, #2

0x469164 SUBS	X12, X12, #2

0x469168 B.EQ	4690a0

0x46916c LDR	X13, [X10, X8,LSL #3]

0x469170 CMP	X13, #1

0x469174 B.LT	469180

0x469178 ADD	X11, X11, #1

0x46917c STR	X11, [X29, #24]

0x469180 ADD	X13, X10, X8,LSL #3

0x469184 LDR	X13, [X13, #8]

0x469188 CMP	X13, #1

0x46918c B.LT	469160

0x469190 ADD	X11, X11, #1

0x469194 STR	X11, [X29, #24]

0x469198 B	469160

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

[...]

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1,
Function	.omp_outlined..6#0x469040
Source	par_strength.c:1253-1253,par_strength.c:1261-1263,par_strength.c:1266-1268
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	5.25
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.17
P10 cycles	4.83
P11 cycles	5.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.64
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1,
Function	.omp_outlined..6#0x469040
Source	par_strength.c:1253-1253,par_strength.c:1261-1263,par_strength.c:1266-1268
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	5.25
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.17
P10 cycles	4.83
P11 cycles	5.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.64
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..6#0x469040
Source file and lines	par_strength.c:1253-1278
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1261-1278.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1261-1263,1266-1268.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	5.50	5.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

24% of peak load performance is reached (23.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 469160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
TBZ W9, #0, 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4b1100 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [SP]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 469134 <.omp_outlined..6+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4690fc <.omp_outlined..6+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X12, X9, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 46916c <.omp_outlined..6+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUBS X12, X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4690a0 <.omp_outlined..6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 469180 <.omp_outlined..6+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X13, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X13, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 469160 <.omp_outlined..6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 469160 <.omp_outlined..6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..6#0x469040
Source file and lines	par_strength.c:1253-1278
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 0.50 cycles (11.00x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	5.50	5.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

24% of peak load performance is reached (23.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 469160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
TBZ W9, #0, 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4b1100 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [SP]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 469134 <.omp_outlined..6+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4690fc <.omp_outlined..6+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND X12, X9, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 46916c <.omp_outlined..6+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUBS X12, X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4690a0 <.omp_outlined..6+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 469180 <.omp_outlined..6+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X13, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X13, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 469160 <.omp_outlined..6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X29, #24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 469160 <.omp_outlined..6+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code