OV - exec - Loop 68

	Loop Id: 68	Module: exec	Source: ams.c:3382-3394	Coverage: 0.04%

0x47c544 ADD	X14, X14, #1

0x47c548 CMP	X3, X9

0x47c54c B.EQ	47c7a0

0x47c550 ORR	X4, XZR, X3

0x47c554 STR	XZR, [X10, X3,LSL #3]

0x47c558 ADD	X3, X3, #1

0x47c55c ORR	X5, XZR, X1

0x47c560 MOVI	D0, #0

0x47c564 LDR	X1, [X11, X3,LSL #3]

0x47c568 CMP	X1, X5

0x47c56c B.LE	47c62c

0x47c570 SUB	W6, W1, W5

0x47c574 MOVI	D0, #0

0x47c578 ANDS	X7, X6, #4160

0x47c57c B.EQ	47c5b4

0x47c580 ORR	X6, XZR, X5

  (73) 0x47c584 LDR	D1, [X15, X6,LSL #3]

  (73) 0x47c588 ADD	X6, X6, #1

  (73) 0x47c58c SUBS	X7, X7, #1

  (73) 0x47c590 FABS	D1, D1

  (73) 0x47c594 FADD	D0, D0, D1

  (73) 0x47c598 STR	D0, [X10, X4,LSL #3]

  (73) 0x47c59c B.NE	47c584

0x47c5a0 ORN	X5, XZR, X5

0x47c5a4 ADD	X5, X1, X5

0x47c5a8 CMP	X5, #3

0x47c5ac B.CS	47c5c8

0x47c5b0 B	47c62c

0x47c5b4 ORR	X6, XZR, X5

0x47c5b8 ORN	X5, XZR, X5

0x47c5bc ADD	X5, X1, X5

0x47c5c0 CMP	X5, #3

0x47c5c4 B.CC	47c62c

0x47c5c8 SUB	X5, X1, X6

0x47c5cc ADD	X6, X0, X6,LSL #3

0x47c5d0 HINT	#0

0x47c5d4 HINT	#0

0x47c5d8 HINT	#0

0x47c5dc HINT	#0

  (72) 0x47c5e0 LDUR	D1, [X6, #496]

  (72) 0x47c5e4 SUBS	X5, X5, #4

  (72) 0x47c5e8 FABS	D1, D1

  (72) 0x47c5ec FADD	D0, D0, D1

  (72) 0x47c5f0 STR	D0, [X10, X4,LSL #3]

  (72) 0x47c5f4 LDUR	D1, [X6, #504]

  (72) 0x47c5f8 FABS	D1, D1

  (72) 0x47c5fc FADD	D0, D0, D1

  (72) 0x47c600 STR	D0, [X10, X4,LSL #3]

  (72) 0x47c604 LDR	D1, [X6]

  (72) 0x47c608 FABS	D1, D1

  (72) 0x47c60c FADD	D0, D0, D1

  (72) 0x47c610 STR	D0, [X10, X4,LSL #3]

  (72) 0x47c614 LDR	D1, [X6, #8]

  (72) 0x47c618 ADD	X6, X6, #32

  (72) 0x47c61c FABS	D1, D1

  (72) 0x47c620 FADD	D0, D0, D1

  (72) 0x47c624 STR	D0, [X10, X4,LSL #3]

  (72) 0x47c628 B.NE	47c5e0

0x47c62c CBZ	X12, 47c544

0x47c630 LDR	X23, [X13, X4,LSL #3]

0x47c634 LDR	X5, [X13, X3,LSL #3]

0x47c638 SUBS	X6, X5, X23

0x47c63c B.LE	47c544

0x47c640 CMP	X25, #8

0x47c644 MOVZ	W7, #8

0x47c648 CSEL	X7, X25, X7, #8

0x47c64c CMP	X6, X7

0x47c650 B.CC	47c720

0x47c654 UBFM	X7, X14, #61, #60

0x47c658 ADD	X30, X16, X5,LSL #3

0x47c65c ADD	X24, X16, X23,LSL #3

0x47c660 ADD	X22, X17, X7

0x47c664 ADD	X7, X18, X7

0x47c668 CMP	X22, X30

0x47c66c CCMP	X24, X7, #2, #3

0x47c670 B.CC	47c720

0x47c674 UDIV	X7, X6, X25

0x47c678 UBFM	X24, X23, #61, #60

0x47c67c ORR	X30, XZR, XZR

0x47c680 MADD	X22, X7, X25, XZR

0x47c684 SUB	X7, X6, X22

0x47c688 ADD	X6, X23, X22

0x47c68c ADD	X23, X16, X24

0x47c690 ADDVL	X24, X24, #1

0x47c694 ADD	X24, X16, X24

0x47c698 HINT	#0

0x47c69c HINT	#0

  (71) 0x47c6a0 LD1D	{Z1.D}, P0/Z, [X23, X30,LSL #3]

  (71) 0x47c6a4 LD1D	{Z2.D}, P0/Z, [X24, X30,LSL #3]

  (71) 0x47c6a8 ADD	X30, X30, X25

  (71) 0x47c6ac CMP	X22, X30

  (71) 0x47c6b0 FABS	Z1.D, P0/M, Z1.D

  (71) 0x47c6b4 FABS	Z2.D, P0/M, Z2.D

  (71) 0x47c6b8 FADDA	D0, P0, D0, Z1.D

  (71) 0x47c6bc FADDA	D0, P0, D0, Z2.D

  (71) 0x47c6c0 B.NE	47c6a0

0x47c6c4 STR	D0, [X10, X4,LSL #3]

0x47c6c8 CBZ	X7, 47c544

0x47c6cc SUB	W7, W5, W6

0x47c6d0 ANDS	X22, X7, #4160

0x47c6d4 B.EQ	47c730

0x47c6d8 ORR	X7, XZR, X6

0x47c6dc HINT	#0

  (69) 0x47c6e0 LDR	D1, [X16, X7,LSL #3]

  (69) 0x47c6e4 ADD	X7, X7, #1

  (69) 0x47c6e8 SUBS	X22, X22, #1

  (69) 0x47c6ec FABS	D1, D1

  (69) 0x47c6f0 FADD	D0, D0, D1

  (69) 0x47c6f4 STR	D0, [X10, X4,LSL #3]

  (69) 0x47c6f8 B.NE	47c6e0

0x47c6fc ORN	X6, XZR, X6

0x47c700 ADD	X6, X5, X6

0x47c704 CMP	X6, #3

0x47c708 B.CC	47c544

0x47c70c B	47c744

0x47c720 ORR	X6, XZR, X23

0x47c724 SUB	W7, W5, W6

0x47c728 ANDS	X22, X7, #4160

0x47c72c B.NE	47c6d8

0x47c730 ORR	X7, XZR, X6

0x47c734 ORN	X6, XZR, X6

0x47c738 ADD	X6, X5, X6

0x47c73c CMP	X6, #3

0x47c740 B.CC	47c544

0x47c744 SUB	X5, X5, X7

0x47c748 ADD	X6, X2, X7,LSL #3

  (70) 0x47c74c LDUR	D1, [X6, #496]

  (70) 0x47c750 SUBS	X5, X5, #4

  (70) 0x47c754 FABS	D1, D1

  (70) 0x47c758 FADD	D0, D0, D1

  (70) 0x47c75c STR	D0, [X10, X4,LSL #3]

  (70) 0x47c760 LDUR	D1, [X6, #504]

  (70) 0x47c764 FABS	D1, D1

  (70) 0x47c768 FADD	D0, D0, D1

  (70) 0x47c76c STR	D0, [X10, X4,LSL #3]

  (70) 0x47c770 LDR	D1, [X6]

  (70) 0x47c774 FABS	D1, D1

  (70) 0x47c778 FADD	D0, D0, D1

  (70) 0x47c77c STR	D0, [X10, X4,LSL #3]

  (70) 0x47c780 LDR	D1, [X6, #8]

  (70) 0x47c784 ADD	X6, X6, #32

  (70) 0x47c788 FABS	D1, D1

  (70) 0x47c78c FADD	D0, D0, D1

  (70) 0x47c790 STR	D0, [X10, X4,LSL #3]

  (70) 0x47c794 B.NE	47c74c

0x47c798 B	47c544

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3394

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.70 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38 - 1.48
Bottlenecks	P6, P8,
Function	.omp_outlined.#0x47b720
Source	ams.c:3382-3384,ams.c:3388-3388,ams.c:3391-3393
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50 - 20.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	13.50 - 20.00
CQA cycles if fully vectorized	3.38 - 10.00
Front-end cycles	9.75
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	13.50
P2 cycles	13.50
P3 cycles	13.50
P4 cycles	13.50
P5 cycles	0.75
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	5.00 - 20.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	78.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00 - 2.96
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.70 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38 - 1.48
Bottlenecks	P6, P8,
Function	.omp_outlined.#0x47b720
Source	ams.c:3382-3384,ams.c:3388-3388,ams.c:3391-3393
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50 - 20.00
CQA cycles if no scalar integer	5.00 - 20.00
CQA cycles if FP arith vectorized	13.50 - 20.00
CQA cycles if fully vectorized	3.38 - 10.00
Front-end cycles	9.75
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	13.50
P2 cycles	13.50
P3 cycles	13.50
P4 cycles	13.50
P5 cycles	0.75
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	5.00 - 20.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	78.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00 - 2.96
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x47b720
Source file and lines	ams.c:3382-3394
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388,3391-3393.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	13.50	13.50	13.50	13.50	0.75	0.75	0.75	0.75	1.67	1.67	1.67	0.50	0.50
cycles	8.50	8.50	13.50	13.50	13.50	13.50	0.75	0.75	0.75	0.75	1.67	1.67	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	9.75
Overall L1	13.50-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47c550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c7a0 <.omp_outlined.+0x1080>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X1, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W6, W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ANDS X7, X6, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c5b4 <.omp_outlined.+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X5, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 47c5c8 <.omp_outlined.+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X5, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X12, 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X6, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ W7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X7, X25, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c720 <.omp_outlined.+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X7, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X16, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X24, X7, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 47c720 <.omp_outlined.+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X7, X6, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X24, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X22, X7, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X7, X6, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X24, X24, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X24, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
STR D0, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X7, 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W7, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X22, X7, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c730 <.omp_outlined.+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X7, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47c744 <.omp_outlined.+0x1024>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W7, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X22, X7, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47c6d8 <.omp_outlined.+0xfb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X7, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X2, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x47b720
Source file and lines	ams.c:3382-3394
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	85
loop length	340
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	13.50	13.50	13.50	13.50	0.75	0.75	0.75	0.75	1.67	1.67	1.67	0.50	0.50
cycles	8.50	8.50	13.50	13.50	13.50	13.50	0.75	0.75	0.75	0.75	1.67	1.67	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	9.75
Overall L1	13.50-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47c550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c7a0 <.omp_outlined.+0x1080>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X1, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W6, W1, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ANDS X7, X6, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c5b4 <.omp_outlined.+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X5, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 47c5c8 <.omp_outlined.+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X5, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c62c <.omp_outlined.+0xf0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X12, 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X6, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ W7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X7, X25, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c720 <.omp_outlined.+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X7, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X16, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X17, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X24, X7, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 47c720 <.omp_outlined.+0x1000>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X7, X6, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X24, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X30, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X22, X7, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X7, X6, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X24, X24, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X24, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
STR D0, [X10, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBZ X7, 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W7, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X22, X7, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 47c730 <.omp_outlined.+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X7, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 47c744 <.omp_outlined.+0x1024>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W7, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X22, X7, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 47c6d8 <.omp_outlined.+0xfb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X7, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X6, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X5, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X2, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 47c544 <.omp_outlined.+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code