OV - exec - Loop 625

0x466fcc LDR	X3, [X19, X24,LSL #3]    [2]

0x466fd0 STR	X3, [X6, X24,LSL #3]    [1]

0x466fd4 LDR	X3, [X18, X11,LSL #3]    [3]

0x466fd8 ADD	X24, X24, #1

0x466fdc CMP	X24, X3

0x466fe0 B.GE	467010

0x466fe4 LDR	D5, [X17, X24,LSL #3]    [5]

0x466fe8 FCMP	D5, D4

0x466fec B.LT	466fcc

0x466ff0 STR	X28, [X6, X24,LSL #3]    [1]

0x466ff4 LDUR	X3, [X29, #488]    [4]

0x466ff8 SUB	X3, X3, #1

0x466ffc STUR	X3, [X29, #488]    [4]

0x467000 LDR	X3, [X18, X11,LSL #3]    [3]

0x467004 ADD	X24, X24, #1

0x467008 CMP	X24, X3

0x46700c B.LT	466fe4

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 451 - 460

--------------------------------------------------------------------------------

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.58
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks
Function	.omp_outlined..2#0x4664a0
Source	par_strength.c:451-460
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.58
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.58
CQA cycles if fully vectorized	0.40
Front-end cycles	1.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.63
P2 cycles	0.63
P3 cycles	0.63
P4 cycles	0.63
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.58
P10 cycles	1.42
P11 cycles	1.50
P12 cycles	0.75
P13 cycles	0.75
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.50
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.67
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..2#0x4664a0
Source	par_strength.c:451-460
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.42
Front-end cycles	1.38
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P10,
Function	.omp_outlined..2#0x4664a0
Source	par_strength.c:451-460
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.38
Front-end cycles	1.13
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.17
P11 cycles	1.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x4664a0
Source file and lines	par_strength.c:451-460
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:451-460.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.58 to 0.40 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.63	0.63	0.63	0.63	1.00	0.00	0.00	0.00	1.58	1.42	1.50	0.75	0.75
cycles	1.00	1.00	0.63	0.63	0.63	0.63	1.00	0.00	0.00	0.00	1.58	1.42	1.50	0.75	0.75

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	1.58

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.58 cycles. At this rate:

15% of peak load performance is reached (15.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..2#0x4664a0
Source file and lines	par_strength.c:451-460
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:451-460.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.67 to 1.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.67 to 0.42 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	1.00	0.00	0.00	0.00	1.67	1.67	1.67	1.00	1.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	1.00	0.00	0.00	0.00	1.67	1.67	1.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.38
Data deps.	1.00
Overall L1	1.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 466fe4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR D5, [X17, X24,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D5, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.LT 466fcc <.omp_outlined..2+0xb2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X28, [X6, X24,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X3, [X29, #488]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
STUR X3, [X29, #488]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X18, X11,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.LT 466fe4 <.omp_outlined..2+0xb44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x4664a0
Source file and lines	par_strength.c:451-460
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:451-460.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.50	0.50	0.50	0.50	1.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50
cycles	1.00	1.00	0.50	0.50	0.50	0.50	1.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 466fe4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X3, [X19, X24,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [X6, X24,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X18, X11,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X24, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.GE 467010 <.omp_outlined..2+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X17, X24,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D5, D4	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.LT 466fcc <.omp_outlined..2+0xb2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code