OV - exec - Loop 580

  (582) 0x421d58 ORR	W1, WZR, W19

  (582) 0x421d5c ADRP	X0,

  (582) 0x421d60 ADD	X0, X0, #928

  (582) 0x421d64 BL	40f410

  (582) 0x421d68 LDP	X20, X19, [SP, #128]

  (582) 0x421d6c LDP	X22, X21, [SP, #112]

  (582) 0x421d70 LDP	X24, X23, [SP, #96]

  (582) 0x421d74 LDP	X26, X25, [SP, #80]

  (582) 0x421d78 LDP	X28, X27, [SP, #64]

  (582) 0x421d7c LDP	X29, X30, [SP, #48]

  (582) 0x421d80 ADD	SP, SP, #144

  (582) 0x421d84 RET

  (582) 0x421d88 FMOV	D0, #1.0000000

  (582) 0x421d8c MOVN	X10, #0

  (582) 0x421d90 MOVZ	W11, #1

  (582) 0x421d94 B	421dbc

  (582) 0x421da0 LDR	X13, [X22, X12,LSL #3]

  (582) 0x421da4 CMP	X13, #1

  (582) 0x421da8 B.LT	421dd0

  (582) 0x421dac STR	X11, [X22, X12,LSL #3]

  (582) 0x421db0 CMP	X9, X8

  (582) 0x421db4 ADD	X9, X9, #1

  (582) 0x421db8 B.EQ	421d58

  (582) 0x421dbc LDR	X12, [X20, X9,LSL #3]

  (582) 0x421dc0 LDR	D1, [X21, X12,LSL #3]

  (582) 0x421dc4 FCMP	D1, D0

  (582) 0x421dc8 B.PL	421da0

0x421dcc STR	X10, [X22, X12,LSL #3]

0x421dd0 ADD	X13, X12, #1

0x421dd4 LDR	X14, [X23, X12,LSL #3]

0x421dd8 LDR	X15, [X23, X13,LSL #3]

0x421ddc B	421de4

  (581) 0x421de0 ADD	X14, X14, #1

  (581) 0x421de4 CMP	X14, X15

  (581) 0x421de8 B.GE	421e08

  (581) 0x421dec LDR	X16, [X24, X14,LSL #3]

  (581) 0x421df0 LDR	X16, [X22, X16,LSL #3]

  (581) 0x421df4 CMP	X16, #1

  (581) 0x421df8 B.LT	421de0

  (581) 0x421dfc STR	X10, [X22, X12,LSL #3]

  (581) 0x421e00 LDR	X15, [X23, X13,LSL #3]

  (581) 0x421e04 B	421de0

0x421e08 LDR	X14, [X25, X12,LSL #3]

0x421e0c LDR	X15, [X25, X13,LSL #3]

0x421e10 B	421e24

0x421e24 CMP	X14, X15

0x421e28 B.GE	421db0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2435 - 2473

--------------------------------------------------------------------------------

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

2436: #endif

2437:      for (ig = 0; ig < graph_size; ig++) {

2438:        i = graph_array[ig];

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P10,
Function	.omp_outlined..21
Source	par_coarsen.c:2446-2446,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	1.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P10,
Function	.omp_outlined..21
Source	par_coarsen.c:2446-2446,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	1.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..21
Source file and lines	par_coarsen.c:2435-2473
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465-2473.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.83

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421e24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X10, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 421de4 <.omp_outlined..21+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X25, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 421e24 <.omp_outlined..21+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421db0 <.omp_outlined..21+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..21
Source file and lines	par_coarsen.c:2435-2473
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465-2473.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.83

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421e24

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X10, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X23, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X23, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 421de4 <.omp_outlined..21+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X25, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 421e24 <.omp_outlined..21+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 421db0 <.omp_outlined..21+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code