OV - exec - Loop 579

0x49d1a0 LD1D	{Z2.D}, P0/Z, [X14, X12,LSL #3]    [1]

0x49d1a4 LD1D	{Z3.D}, P0/Z, [X15, X12,LSL #3]    [2]

0x49d1a8 ADD	X12, X12, X17

0x49d1ac CMP	X13, X12

0x49d1b0 ADD	Z0.D, Z2.D, Z0.D

0x49d1b4 ADD	Z1.D, Z3.D, Z1.D

0x49d1b8 B.NE	49d1a0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3275 - 3275

--------------------------------------------------------------------------------

3275:             value_start[my_thread_num] += ncols[ii];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	.omp_outlined..21#0x49d090
Source	IJMatrix_parcsr.c:3275-3275
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	1.79
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	85.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	.omp_outlined..21#0x49d090
Source	IJMatrix_parcsr.c:3275-3275
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	1.79
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	85.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..21#0x49d090
Source file and lines	IJMatrix_parcsr.c:3275-3275
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 1.79 cycles (1.12x speedup).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	0.88
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 49d1a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z2.D}, P0/Z, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
ADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
B.NE 49d1a0 <.omp_outlined..21+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..21#0x49d090
Source file and lines	IJMatrix_parcsr.c:3275-3275
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3275.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 1.79 cycles (1.12x speedup).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	0.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	0.88
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 49d1a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z2.D}, P0/Z, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
ADD Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
B.NE 49d1a0 <.omp_outlined..21+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code