OV - exec - Loop 56

0x4869e0 LDUR	X14, [X29, #496]

  (55) 0x4869e4 STR	X30, [X5, X20,LSL #3]

  (55) 0x4869e8 STR	X28, [X7, X20,LSL #3]

  (55) 0x4869ec ORR	X28, XZR, X24

  (55) 0x4869f0 ORR	X30, XZR, X6

  (55) 0x4869f4 ORR	X20, XZR, X26

  (55) 0x4869f8 CMP	X26, X14

  (55) 0x4869fc B.EQ	486bf8

  (55) 0x486a00 LDUR	X8, [X29, #504]

  (55) 0x486a04 LDR	X8, [X8]

  (55) 0x486a08 CBZ	X8, 486a14

  (55) 0x486a0c ADD	X6, X30, #1

  (55) 0x486a10 STR	X30, [X0, X20,LSL #3]

  (55) 0x486a14 LDR	X8, [X15]

  (55) 0x486a18 CBZ	X8, 486ae0

  (55) 0x486a1c LDUR	X8, [X29, #488]

  (55) 0x486a20 LDR	X13, [X8, X20,LSL #3]

  (55) 0x486a24 LDR	X8, [X23, X20,LSL #3]

  (55) 0x486a28 CMP	X13, X8

  (55) 0x486a2c B.GE	486ae0

  (55) 0x486a30 LDR	X8, [SP, #72]

  (55) 0x486a34 LDUR	X9, [X29, #448]

  (55) 0x486a38 ORR	X24, XZR, X28

  (55) 0x486a3c LDR	X8, [X8]

  (55) 0x486a40 LDR	X14, [X9]

  (55) 0x486a44 B	486a58

    (59) 0x486a48 LDR	X9, [X23, X20,LSL #3]

    (59) 0x486a4c ADD	X13, X13, #1

    (59) 0x486a50 CMP	X13, X9

    (59) 0x486a54 B.GE	486b00

    (59) 0x486a58 LDR	X10, [X17, X13,LSL #3]

    (59) 0x486a5c ADD	X9, X10, #1

    (59) 0x486a60 LDR	X19, [X18, X10,LSL #3]

    (59) 0x486a64 LDR	X12, [X18, X9,LSL #3]

    (59) 0x486a68 B	486a70

      (61) 0x486a6c ADD	X19, X19, #1

      (61) 0x486a70 CMP	X19, X12

      (61) 0x486a74 B.GE	486aa0

      (61) 0x486a78 LDR	X16, [X22]

      (61) 0x486a7c LDR	X25, [X8, X19,LSL #3]

      (61) 0x486a80 ADD	X25, X16, X25

      (61) 0x486a84 LDR	X16, [X0, X25,LSL #3]

      (61) 0x486a88 CMP	X16, X28

      (61) 0x486a8c B.GE	486a6c

      (61) 0x486a90 STR	X24, [X0, X25,LSL #3]

      (61) 0x486a94 ADD	X24, X24, #1

      (61) 0x486a98 LDR	X12, [X18, X9,LSL #3]

      (61) 0x486a9c B	486a6c

    (59) 0x486aa0 LDR	X10, [X1, X10,LSL #3]

    (59) 0x486aa4 LDR	X12, [X1, X9,LSL #3]

    (59) 0x486aa8 B	486ab0

      (60) 0x486aac ADD	X10, X10, #1

      (60) 0x486ab0 CMP	X10, X12

      (60) 0x486ab4 B.GE	486a48

      (60) 0x486ab8 LDR	X19, [X14, X10,LSL #3]

      (60) 0x486abc LDR	X16, [X0, X19,LSL #3]

      (60) 0x486ac0 CMP	X16, X30

      (60) 0x486ac4 B.GE	486aac

      (60) 0x486ac8 STR	X6, [X0, X19,LSL #3]

      (60) 0x486acc ADD	X6, X6, #1

      (60) 0x486ad0 LDR	X12, [X1, X9,LSL #3]

      (60) 0x486ad4 B	486aac

  (55) 0x486ae0 ORR	X24, XZR, X28

  (55) 0x486ae4 ADD	X26, X20, #1

  (55) 0x486ae8 LDR	X27, [X2, X20,LSL #3]

  (55) 0x486aec LDR	X8, [X2, X26,LSL #3]

  (55) 0x486af0 CMP	X27, X8

  (55) 0x486af4 B.GE	4869e4

0x486af8 B	486b18

  (55) 0x486b00 LDUR	X14, [X29, #496]

  (55) 0x486b04 ADD	X26, X20, #1

  (55) 0x486b08 LDR	X27, [X2, X20,LSL #3]

  (55) 0x486b0c LDR	X8, [X2, X26,LSL #3]

  (55) 0x486b10 CMP	X27, X8

  (55) 0x486b14 B.GE	4869e4

0x486b18 LDUR	X8, [X29, #456]

0x486b1c LDR	X13, [X8]

0x486b20 LDUR	X8, [X29, #464]

0x486b24 LDR	X14, [X8]

0x486b28 LDUR	X8, [X29, #472]

0x486b2c LDR	X19, [X8]

0x486b30 LDUR	X8, [X29, #480]

0x486b34 LDR	X8, [X8]

0x486b38 B	486b50

0x486b40 LDR	X9, [X2, X26,LSL #3]

0x486b44 ADD	X27, X27, #1

0x486b48 CMP	X27, X9

0x486b4c B.GE	4869e0

0x486b50 LDR	X10, [X3, X27,LSL #3]

0x486b54 ADD	X9, X10, #1

0x486b58 LDR	X12, [X4, X10,LSL #3]

0x486b5c LDR	X25, [X4, X9,LSL #3]

0x486b60 B	486b68

  (58) 0x486b64 ADD	X12, X12, #1

  (58) 0x486b68 CMP	X12, X25

  (58) 0x486b6c B.GE	486ba0

  (58) 0x486b70 LDR	X16, [X13, X12,LSL #3]

  (58) 0x486b74 LDR	X21, [X0, X16,LSL #3]

  (58) 0x486b78 CMP	X21, X30

  (58) 0x486b7c B.GE	486b64

  (58) 0x486b80 STR	X6, [X0, X16,LSL #3]

  (58) 0x486b84 ADD	X6, X6, #1

  (58) 0x486b88 LDR	X25, [X4, X9,LSL #3]

  (58) 0x486b8c B	486b64

0x486ba0 LDR	X12, [X11]

0x486ba4 CBZ	X12, 486b40

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x486840
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x486840
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x486840
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 486b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b18 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b50 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 4869e0 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b68 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 486b40 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x486840
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 486b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b18 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b50 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 4869e0 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 486b68 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 486b40 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code