OV - exec - Loop 461

0x488a20 LDP	X30, X21, [SP, #88]

  (460) 0x488a24 LDUR	X8, [X29, #440]

  (460) 0x488a28 ORR	X19, XZR, X3

  (460) 0x488a2c ORR	X22, XZR, X2

  (460) 0x488a30 CMP	X26, X8

  (460) 0x488a34 B.GE	488d78

  (460) 0x488a38 LDUR	X8, [X29, #432]

  (460) 0x488a3c LDR	X8, [X8]

  (460) 0x488a40 CBZ	X8, 488a64

  (460) 0x488a44 LDUR	X8, [X29, #416]

  (460) 0x488a48 ADD	X2, X22, #1

  (460) 0x488a4c STR	X22, [X0, X26,LSL #3]

  (460) 0x488a50 LDR	D0, [X8]

  (460) 0x488a54 LDUR	X8, [X29, #408]

  (460) 0x488a58 STR	D0, [X8, X22,LSL #3]

  (460) 0x488a5c LDR	X8, [SP, #112]

  (460) 0x488a60 STR	X26, [X8, X22,LSL #3]

  (460) 0x488a64 LDUR	X8, [X29, #424]

  (460) 0x488a68 LDR	X8, [X8]

  (460) 0x488a6c CBZ	X8, 488be0

  (460) 0x488a70 LDR	X8, [SP, #104]

  (460) 0x488a74 LDR	X4, [X8, X26,LSL #3]

  (460) 0x488a78 LDR	X8, [X1, X26,LSL #3]

  (460) 0x488a7c CMP	X4, X8

  (460) 0x488a80 B.GE	488c00

  (460) 0x488a84 LDR	X8, [SP, #40]

  (460) 0x488a88 ORR	X3, XZR, X19

  (460) 0x488a8c LDR	X5, [X8]

  (460) 0x488a90 LDR	X8, [SP, #48]

  (460) 0x488a94 LDR	X6, [X8]

  (460) 0x488a98 B	488ab0

    (464) 0x488aa0 LDR	X8, [X1, X26,LSL #3]

    (464) 0x488aa4 ADD	X4, X4, #1

    (464) 0x488aa8 CMP	X4, X8

    (464) 0x488aac B.GE	488be4

    (464) 0x488ab0 LDUR	X8, [X29, #472]

    (464) 0x488ab4 LDR	X7, [X8, X4,LSL #3]

    (464) 0x488ab8 LDUR	X8, [X29, #464]

    (464) 0x488abc LDR	D0, [X8, X4,LSL #3]

    (464) 0x488ac0 ADD	X8, X7, #1

    (464) 0x488ac4 LDR	X9, [X13, X7,LSL #3]

    (464) 0x488ac8 LDR	X24, [X13, X8,LSL #3]

    (464) 0x488acc CMP	X9, X24

    (464) 0x488ad0 B.GE	488b50

    (464) 0x488ad4 LDUR	X11, [X29, #480]

    (464) 0x488ad8 LDR	X10, [X30]

    (464) 0x488adc LDR	X27, [X11]

    (464) 0x488ae0 LDUR	X11, [X29, #488]

    (464) 0x488ae4 LDR	X23, [X11]

    (464) 0x488ae8 B	488b08

      (466) 0x488aec LDR	D1, [X10, X9,LSL #3]

      (466) 0x488af0 LDR	D2, [X27, X12,LSL #3]

      (466) 0x488af4 FMADD	D1, D0, D1, D2

      (466) 0x488af8 STR	D1, [X27, X12,LSL #3]

      (466) 0x488afc ADD	X9, X9, #1

      (466) 0x488b00 CMP	X9, X24

      (466) 0x488b04 B.GE	488b50

      (466) 0x488b08 LDR	X11, [X20]

      (466) 0x488b0c LDR	X12, [X5, X9,LSL #3]

      (466) 0x488b10 ADD	X11, X12, X11

      (466) 0x488b14 LDR	X12, [X0, X11,LSL #3]

      (466) 0x488b18 CMP	X12, X19

      (466) 0x488b1c B.GE	488aec

      (466) 0x488b20 STR	X3, [X0, X11,LSL #3]

      (466) 0x488b24 LDR	D1, [X10, X9,LSL #3]

      (466) 0x488b28 LDR	X12, [X20]

      (466) 0x488b2c SUB	X11, X11, X12

      (466) 0x488b30 FMUL	D1, D0, D1

      (466) 0x488b34 STR	X11, [X23, X3,LSL #3]

      (466) 0x488b38 LDR	X24, [X13, X8,LSL #3]

      (466) 0x488b3c STR	D1, [X27, X3,LSL #3]

      (466) 0x488b40 ADD	X3, X3, #1

      (466) 0x488b44 ADD	X9, X9, #1

      (466) 0x488b48 CMP	X9, X24

      (466) 0x488b4c B.LT	488b08

    (464) 0x488b50 LDR	X9, [X14, X7,LSL #3]

    (464) 0x488b54 LDR	X23, [X14, X8,LSL #3]

    (464) 0x488b58 CMP	X9, X23

    (464) 0x488b5c B.GE	488aa0

    (464) 0x488b60 LDUR	X11, [X29, #496]

    (464) 0x488b64 LDR	X10, [X21]

    (464) 0x488b68 LDR	X7, [X25]

    (464) 0x488b6c LDR	X24, [X11]

    (464) 0x488b70 B	488b9c

      (465) 0x488b80 LDR	D1, [X10, X9,LSL #3]

      (465) 0x488b84 LDR	D2, [X7, X12,LSL #3]

      (465) 0x488b88 FMADD	D1, D0, D1, D2

      (465) 0x488b8c STR	D1, [X7, X12,LSL #3]

      (465) 0x488b90 ADD	X9, X9, #1

      (465) 0x488b94 CMP	X9, X23

      (465) 0x488b98 B.GE	488aa0

      (465) 0x488b9c LDR	X11, [X6, X9,LSL #3]

      (465) 0x488ba0 LDR	X12, [X0, X11,LSL #3]

      (465) 0x488ba4 CMP	X12, X22

      (465) 0x488ba8 B.GE	488b80

      (465) 0x488bac LDR	D1, [X10, X9,LSL #3]

      (465) 0x488bb0 STR	X2, [X0, X11,LSL #3]

      (465) 0x488bb4 STR	X11, [X24, X2,LSL #3]

      (465) 0x488bb8 LDR	X23, [X14, X8,LSL #3]

      (465) 0x488bbc FMUL	D1, D0, D1

      (465) 0x488bc0 STR	D1, [X7, X2,LSL #3]

      (465) 0x488bc4 ADD	X2, X2, #1

      (465) 0x488bc8 ADD	X9, X9, #1

      (465) 0x488bcc CMP	X9, X23

      (465) 0x488bd0 B.LT	488b9c

    (464) 0x488bd4 B	488aa0

  (460) 0x488be0 ORR	X3, XZR, X19

  (460) 0x488be4 LDR	X4, [X15, X26,LSL #3]

  (460) 0x488be8 ADD	X26, X26, #1

  (460) 0x488bec LDR	X8, [X15, X26,LSL #3]

  (460) 0x488bf0 CMP	X4, X8

  (460) 0x488bf4 B.GE	488a24

0x488bf8 B	488c18

  (460) 0x488c00 ORR	X3, XZR, X19

  (460) 0x488c04 LDR	X4, [X15, X26,LSL #3]

  (460) 0x488c08 ADD	X26, X26, #1

  (460) 0x488c0c LDR	X8, [X15, X26,LSL #3]

  (460) 0x488c10 CMP	X4, X8

  (460) 0x488c14 B.GE	488a24

0x488c18 LDR	X8, [SP, #56]

0x488c1c LDR	X5, [X8]

0x488c20 LDR	X8, [SP, #64]

0x488c24 LDR	X6, [X8]

0x488c28 LDR	X8, [SP, #72]

0x488c2c LDR	X7, [X8]

0x488c30 LDR	X8, [SP, #80]

0x488c34 LDR	X30, [X8]

0x488c38 B	488c50

0x488c40 LDR	X8, [X15, X26,LSL #3]

0x488c44 ADD	X4, X4, #1

0x488c48 CMP	X4, X8

0x488c4c B.GE	488a20

0x488c50 LDR	X9, [X16, X4,LSL #3]

0x488c54 LDR	D0, [X17, X4,LSL #3]

0x488c58 ADD	X8, X9, #1

0x488c5c LDR	X10, [X18, X9,LSL #3]

0x488c60 LDR	X27, [X18, X8,LSL #3]

0x488c64 CMP	X10, X27

0x488c68 B.GE	488cd8

0x488c6c LDUR	X11, [X29, #456]

0x488c70 LDR	X24, [X25]

0x488c74 LDR	X23, [X11]

0x488c78 LDUR	X11, [X29, #496]

0x488c7c LDR	X11, [X11]

0x488c80 B	488ca0

  (463) 0x488c84 LDR	D1, [X23, X10,LSL #3]

  (463) 0x488c88 LDR	D2, [X24, X21,LSL #3]

  (463) 0x488c8c FMADD	D1, D0, D1, D2

  (463) 0x488c90 STR	D1, [X24, X21,LSL #3]

  (463) 0x488c94 ADD	X10, X10, #1

  (463) 0x488c98 CMP	X10, X27

  (463) 0x488c9c B.GE	488cd8

  (463) 0x488ca0 LDR	X12, [X5, X10,LSL #3]

  (463) 0x488ca4 LDR	X21, [X0, X12,LSL #3]

  (463) 0x488ca8 CMP	X21, X22

  (463) 0x488cac B.GE	488c84

  (463) 0x488cb0 LDR	D1, [X23, X10,LSL #3]

  (463) 0x488cb4 STR	X2, [X0, X12,LSL #3]

  (463) 0x488cb8 STR	X12, [X11, X2,LSL #3]

  (463) 0x488cbc LDR	X27, [X18, X8,LSL #3]

  (463) 0x488cc0 FMUL	D1, D0, D1

  (463) 0x488cc4 STR	D1, [X24, X2,LSL #3]

  (463) 0x488cc8 ADD	X2, X2, #1

  (463) 0x488ccc ADD	X10, X10, #1

  (463) 0x488cd0 CMP	X10, X27

  (463) 0x488cd4 B.LT	488ca0

0x488cd8 LDR	X10, [X28]

0x488cdc CBZ	X10, 488c40

0x488ce0 LDR	X9, [X6, X9,LSL #3]

0x488ce4 LDR	X24, [X6, X8,LSL #3]

0x488ce8 CMP	X9, X24

0x488cec B.GE	488c40

0x488cf0 LDUR	X11, [X29, #480]

0x488cf4 LDUR	X10, [X29, #448]

0x488cf8 LDR	X27, [X11]

0x488cfc LDUR	X11, [X29, #488]

0x488d00 LDR	X10, [X10]

0x488d04 LDR	X23, [X11]

0x488d08 B	488d28

  (462) 0x488d0c LDR	D1, [X10, X9,LSL #3]

  (462) 0x488d10 LDR	D2, [X27, X12,LSL #3]

  (462) 0x488d14 FMADD	D1, D0, D1, D2

  (462) 0x488d18 STR	D1, [X27, X12,LSL #3]

  (462) 0x488d1c ADD	X9, X9, #1

  (462) 0x488d20 CMP	X9, X24

  (462) 0x488d24 B.GE	488c40

  (462) 0x488d28 LDR	X12, [X30, X9,LSL #3]

  (462) 0x488d2c LDR	X11, [X20]

  (462) 0x488d30 LDR	X12, [X7, X12,LSL #3]

  (462) 0x488d34 ADD	X11, X12, X11

  (462) 0x488d38 LDR	X12, [X0, X11,LSL #3]

  (462) 0x488d3c CMP	X12, X19

  (462) 0x488d40 B.GE	488d0c

  (462) 0x488d44 STR	X3, [X0, X11,LSL #3]

  (462) 0x488d48 LDR	D1, [X10, X9,LSL #3]

  (462) 0x488d4c LDR	X12, [X20]

  (462) 0x488d50 SUB	X11, X11, X12

  (462) 0x488d54 FMUL	D1, D0, D1

  (462) 0x488d58 STR	X11, [X23, X3,LSL #3]

  (462) 0x488d5c LDR	X24, [X6, X8,LSL #3]

  (462) 0x488d60 STR	D1, [X27, X3,LSL #3]

  (462) 0x488d64 ADD	X3, X3, #1

  (462) 0x488d68 ADD	X9, X9, #1

  (462) 0x488d6c CMP	X9, X24

  (462) 0x488d70 B.LT	488d28

0x488d74 B	488c40

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	5.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x4887f0
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.86
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	5.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x4887f0
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.86
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..9#0x4887f0
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.67 cycles (5.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.25
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

25% of peak load performance is reached (24.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 488c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 488c18 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488c50 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488a20 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488cd8 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488ca0 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X6, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488d28 <.omp_outlined..9+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..9#0x4887f0
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.67 cycles (5.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.25
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

25% of peak load performance is reached (24.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 488c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 488c18 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488c50 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488a20 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488cd8 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488ca0 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X6, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 488d28 <.omp_outlined..9+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 488c40 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code