OV - exec - Loop 439

0x420c60 LDUR	X11, [X29, #416]

0x420c64 STR	X9, [X11, X8,LSL #3]

0x420c68 ADD	X8, X8, #1

0x420c6c LDUR	X11, [X29, #456]

0x420c70 ADD	X9, X9, #1

0x420c74 CMP	X9, X11

0x420c78 B.GE	420cd0

  (440) 0x420c7c UBFM	X11, X9, #61, #60

  (440) 0x420c80 STR	XZR, [X0, X11]

  (440) 0x420c84 LDUR	X12, [X29, #504]

  (440) 0x420c88 ADD	X11, X12, X11

  (440) 0x420c8c LDP	X11, X12, [X11]

  (440) 0x420c90 CMP	X12, X11

  (440) 0x420c94 B.NE	420c60

  (440) 0x420c98 LDUR	X11, [X29, #472]

  (440) 0x420c9c ADD	X11, X11, X9,LSL #3

  (440) 0x420ca0 LDP	X11, X12, [X11]

  (440) 0x420ca4 CMP	X12, X11

  (440) 0x420ca8 B.NE	420c60

  (440) 0x420cac STR	X10, [X0, X9,LSL #3]

  (440) 0x420cb0 LDUR	X11, [X29, #424]

  (440) 0x420cb4 STR	XZR, [X11, X9,LSL #3]

  (440) 0x420cb8 LDUR	X11, [X29, #456]

  (440) 0x420cbc ADD	X9, X9, #1

  (440) 0x420cc0 CMP	X9, X11

  (440) 0x420cc4 B.LT	420c7c

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2232 - 2243

--------------------------------------------------------------------------------

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

2241:          }

2242:          else

2243:             graph_array[cnt++] = i;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2232,par_coarsen.c:2243-2243
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.17
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2232,par_coarsen.c:2243-2243
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.17
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	0.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2243
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232-2243.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232,2243.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.88
Overall L1	1.17

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.17 cycles. At this rate:

14% of peak load performance is reached (13.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420cd0 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2243
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232-2243.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232,2243.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.88
Overall L1	1.17

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.17 cycles. At this rate:

14% of peak load performance is reached (13.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 420cd0 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code