OV - exec - Loop 421

0x4208dc UBFM	X11, X9, #61, #60

0x4208e0 STR	XZR, [X0, X11]    [2]

0x4208e4 LDUR	X12, [X29, #504]    [1]

0x4208e8 ADD	X11, X12, X11

0x4208ec LDP	X11, X12, [X11]    [6]

0x4208f0 CMP	X12, X11

0x4208f4 B.NE	4208c0

0x4208f8 LDUR	X11, [X29, #472]    [1]

0x4208fc ADD	X11, X11, X9,LSL #3

0x420900 LDP	X11, X12, [X11]    [4]

0x420904 CMP	X12, X11

0x420908 B.NE	4208c0

0x42090c STR	X10, [X0, X9,LSL #3]    [5]

0x420910 LDUR	X11, [X29, #424]    [1]

0x420914 STR	XZR, [X11, X9,LSL #3]    [3]

0x420918 LDUR	X11, [X29, #456]    [1]

0x42091c ADD	X9, X9, #1

0x420920 CMP	X9, X11

0x420924 B.LT	4208dc

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2232 - 2240

--------------------------------------------------------------------------------

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:598	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start		exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2240
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.17
CQA cycles if no scalar integer	3.17
CQA cycles if FP arith vectorized	3.17
CQA cycles if fully vectorized	0.79
Front-end cycles	2.38
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.17
P10 cycles	2.83
P11 cycles	3.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2240
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.17
CQA cycles if no scalar integer	3.17
CQA cycles if FP arith vectorized	3.17
CQA cycles if fully vectorized	0.79
Front-end cycles	2.38
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.17
P10 cycles	2.83
P11 cycles	3.00
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2240
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232-2240.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.17 to 0.79 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	1.50	1.50
cycles	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	1.50	1.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Data deps.	1.00
Overall L1	3.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.17 cycles. At this rate:

21% of peak load performance is reached (20.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4208dc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
UBFM X11, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X0, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X12, [X29, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X11, X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X11, X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X10, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4208dc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2240
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232-2240.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.17 to 0.79 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	1.50	1.50
cycles	1.50	1.50	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	3.17	2.83	3.00	1.50	1.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Data deps.	1.00
Overall L1	3.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.17 cycles. At this rate:

21% of peak load performance is reached (20.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4208dc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
UBFM X11, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X0, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X12, [X29, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X11, X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X11, X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X10, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4208dc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code