OV - exec - Loop 40

  (38) 0x4a1ecc CMP	X14, X28

  (38) 0x4a1ed0 B.GE	4a1f6c

  (38) 0x4a1ed4 STR	X8, [X9, X14,LSL #3]

  (38) 0x4a1ed8 ORR	X15, XZR, X14

  (38) 0x4a1edc LDR	X14, [X19]

  (38) 0x4a1ee0 CBZ	X14, 4a1eec

  (38) 0x4a1ee4 ADD	X8, X8, #1

  (38) 0x4a1ee8 STR	X15, [X20, X15,LSL #3]

  (38) 0x4a1eec ADD	X14, X15, #1

  (38) 0x4a1ef0 LDR	X16, [X10, X15,LSL #3]

  (38) 0x4a1ef4 LDR	X1, [X10, X14,LSL #3]

  (38) 0x4a1ef8 CMP	X16, X1

  (38) 0x4a1efc B.GE	4a1ecc

0x4a1f00 LDR	X17, [X25]

0x4a1f04 B	4a1f18

0x4a1f0c ADD	X16, X16, #1

0x4a1f10 CMP	X16, X1

0x4a1f14 B.GE	4a1ecc

0x4a1f18 LDR	X18, [X11, X16,LSL #3]

0x4a1f1c LDR	X0, [X12, X18,LSL #3]

0x4a1f20 LDR	X2, [X13, X18,LSL #3]

0x4a1f24 CMP	X0, X2

0x4a1f28 B.LT	4a1f4c

0x4a1f2c B	4a1f0c

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 214 - 225

--------------------------------------------------------------------------------

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P0, P1,
Function	.omp_outlined.#0x4a1da0
Source	csr_matop.c:222-225
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P0, P1,
Function	.omp_outlined.#0x4a1da0
Source	csr_matop.c:222-225
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4a1da0
Source file and lines	csr_matop.c:214-225
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:214-225.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:222-225.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a1f0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 4a1f18 <.omp_outlined.+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 4a1ecc <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X18, [X11, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 4a1f4c <.omp_outlined.+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 4a1f0c <.omp_outlined.+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4a1da0
Source file and lines	csr_matop.c:214-225
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:214-225.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:222-225.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a1f0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 4a1f18 <.omp_outlined.+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 4a1ecc <.omp_outlined.+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X18, [X11, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X12, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 4a1f4c <.omp_outlined.+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 4a1f0c <.omp_outlined.+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code