OV - exec - Loop 201

0x43bd80 LDR	X9, [X11, X1,LSL #3]

0x43bd84 ADD	X2, X2, #1

0x43bd88 CMP	X2, X9

0x43bd8c B.GE	43bee4

0x43bd90 LDR	X9, [X12, X2,LSL #3]

0x43bd94 LDR	X14, [X10, X9,LSL #3]

0x43bd98 TBNZ	X14, #63, 43bdc0

0x43bd9c LDR	X14, [X22, X9,LSL #3]

0x43bda0 LDR	X0, [X8, X18,LSL #3]

0x43bda4 CMP	X14, X0

0x43bda8 B.GE	43bd80

0x43bdac STR	X19, [X22, X9,LSL #3]

0x43bdb0 ADD	X19, X19, #1

0x43bdb4 B	43bd80

0x43bdc0 CMN	X14, #3

0x43bdc4 B.EQ	43bd80

0x43bdc8 ADD	X6, X9, #1

0x43bdcc LDR	X0, [X11, X9,LSL #3]

0x43bdd0 LDR	X7, [X11, X6,LSL #3]

0x43bdd4 B	43bde4

  (204) 0x43bde0 ADD	X0, X0, #1

  (204) 0x43bde4 CMP	X0, X7

  (204) 0x43bde8 B.GE	43be18

  (204) 0x43bdec LDR	X14, [X12, X0,LSL #3]

  (204) 0x43bdf0 LDR	X20, [X10, X14,LSL #3]

  (204) 0x43bdf4 TBNZ	X20, #63, 43bde0

  (204) 0x43bdf8 LDR	X20, [X22, X14,LSL #3]

  (204) 0x43bdfc LDR	X30, [X8, X18,LSL #3]

  (204) 0x43be00 CMP	X20, X30

  (204) 0x43be04 B.GE	43bde0

  (204) 0x43be08 STR	X19, [X22, X14,LSL #3]

  (204) 0x43be0c ADD	X19, X19, #1

  (204) 0x43be10 LDR	X7, [X11, X6,LSL #3]

  (204) 0x43be14 B	43bde0

0x43be18 LDUR	X14, [X29, #488]

0x43be1c LDR	X14, [X14]

0x43be20 CMP	X14, #2

0x43be24 B.LT	43bd80

0x43be28 LDR	X7, [X3, X9,LSL #3]

0x43be2c LDR	X0, [X3, X6,LSL #3]

0x43be30 CMP	X7, X0

0x43be34 B.GE	43bd80

0x43be38 LDUR	X9, [X29, #344]

0x43be3c LDR	X20, [X9]

0x43be40 LDUR	X9, [X29, #464]

0x43be44 LDR	X30, [X9]

0x43be48 LDUR	X9, [X29, #456]

0x43be4c LDR	X9, [X9]

0x43be50 CBNZ	X4, 43be6c

0x43be54 B	43beb0

  (202) 0x43be60 ADD	X7, X7, #1

  (202) 0x43be64 CMP	X7, X0

  (202) 0x43be68 B.GE	43bd80

  (202) 0x43be6c LDR	X14, [X20, X7,LSL #3]

  (202) 0x43be70 LDR	X14, [X4, X14,LSL #3]

  (202) 0x43be74 LDR	X16, [X5, X14,LSL #3]

  (202) 0x43be78 TBNZ	X16, #63, 43be60

  (202) 0x43be7c LDR	X16, [X23, X14,LSL #3]

  (202) 0x43be80 LDR	X17, [X30, X18,LSL #3]

  (202) 0x43be84 CMP	X16, X17

  (202) 0x43be88 B.GE	43be60

  (202) 0x43be8c MOVZ	W16, #1

  (202) 0x43be90 STR	X16, [X9, X14,LSL #3]

  (202) 0x43be94 STR	X21, [X23, X14,LSL #3]

  (202) 0x43be98 ADD	X21, X21, #1

  (202) 0x43be9c LDR	X0, [X3, X6,LSL #3]

  (202) 0x43bea0 B	43be60

  (203) 0x43bea4 ADD	X7, X7, #1

  (203) 0x43bea8 CMP	X7, X0

  (203) 0x43beac B.GE	43bd80

  (203) 0x43beb0 LDR	X14, [X20, X7,LSL #3]

  (203) 0x43beb4 LDR	X16, [X5, X14,LSL #3]

  (203) 0x43beb8 TBNZ	X16, #63, 43bea4

  (203) 0x43bebc LDR	X16, [X23, X14,LSL #3]

  (203) 0x43bec0 LDR	X17, [X30, X18,LSL #3]

  (203) 0x43bec4 CMP	X16, X17

  (203) 0x43bec8 B.GE	43bea4

  (203) 0x43becc MOVZ	W16, #1

  (203) 0x43bed0 STR	X16, [X9, X14,LSL #3]

  (203) 0x43bed4 STR	X21, [X23, X14,LSL #3]

  (203) 0x43bed8 ADD	X21, X21, #1

  (203) 0x43bedc LDR	X0, [X3, X6,LSL #3]

  (203) 0x43bee0 B	43bea4

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1264 - 1303

--------------------------------------------------------------------------------

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	.omp_outlined.#0x43b900
Source	par_lr_interp.c:1264-1272,par_lr_interp.c:1275-1277,par_lr_interp.c:1289-1293
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.17
CQA cycles if no scalar integer	6.17
CQA cycles if FP arith vectorized	6.17
CQA cycles if fully vectorized	1.54
Front-end cycles	4.50
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.17
P10 cycles	5.83
P11 cycles	6.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.35
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	.omp_outlined.#0x43b900
Source	par_lr_interp.c:1264-1272,par_lr_interp.c:1275-1277,par_lr_interp.c:1289-1293
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.17
CQA cycles if no scalar integer	6.17
CQA cycles if FP arith vectorized	6.17
CQA cycles if fully vectorized	1.54
Front-end cycles	4.50
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.17
P10 cycles	5.83
P11 cycles	6.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.35
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x43b900
Source file and lines	par_lr_interp.c:1264-1303
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264-1303.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264-1272,1275-1277,1289-1293.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.17 to 1.54 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	0.50	0.50
cycles	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.17 cycles. At this rate:

22% of peak load performance is reached (22.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.30 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43bd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X9, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bee4 <.omp_outlined.+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X14, #63, 43bdc0 <.omp_outlined.+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43bde4 <.omp_outlined.+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X3, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X4, 43be6c <.omp_outlined.+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 43beb0 <.omp_outlined.+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x43b900
Source file and lines	par_lr_interp.c:1264-1303
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264-1303.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1264-1272,1275-1277,1289-1293.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.17 to 1.54 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	0.50	0.50
cycles	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.17 cycles. At this rate:

22% of peak load performance is reached (22.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.30 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43bd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X9, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bee4 <.omp_outlined.+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X12, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X14, #63, 43bdc0 <.omp_outlined.+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [X22, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X6, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43bde4 <.omp_outlined.+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X3, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 43bd80 <.omp_outlined.+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X4, 43be6c <.omp_outlined.+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 43beb0 <.omp_outlined.+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code