OV - exec - Loop 1746

0x4a28a0 ST1B	{Z0.B}, P0, [X0, X8]    [1]

0x4a28a4 INCP	X8, P0.B

0x4a28a8 WHILELO	P0.B, X8, X2

0x4a28ac B.MI	4a28a0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 476 - 476

--------------------------------------------------------------------------------

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.50
Bottlenecks
Function	.omp_outlined..7#0x4a2740
Source	csr_matop.c:476-476
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	5
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.50
Bottlenecks
Function	.omp_outlined..7#0x4a2740
Source	csr_matop.c:476-476
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	0.25
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	5
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..7#0x4a2740
Source file and lines	csr_matop.c:476-476
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:476.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 32 bytes.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	5.00

Cycles summary

Front-end	0.50
Data deps.	5.00
Overall L1	5.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a28a0

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ST1B {Z0.B}, P0, [X0, X8]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCP X8, P0.B	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.B, X8, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.MI 4a28a0 <.omp_outlined..7+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..7#0x4a2740
Source file and lines	csr_matop.c:476-476
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:476.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 32 bytes.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	0.25	0.25	0.25	0.25	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	5.00

Cycles summary

Front-end	0.50
Data deps.	5.00
Overall L1	5.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a28a0

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ST1B {Z0.B}, P0, [X0, X8]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCP X8, P0.B	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.B, X8, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.MI 4a28a0 <.omp_outlined..7+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code