OV - exec - Loop 173

	Loop Id: 173	Module: exec	Source: par_lr_interp.c:1609-1675 [...]	Coverage: 0.04%

0x43ca40 LDR	D3, [X17, X3,LSL #3]

0x43ca44 LDR	D4, [X8, X13,LSL #3]

0x43ca48 FADD	D3, D3, D4

0x43ca4c STR	D3, [X8, X13,LSL #3]

0x43ca50 ADD	X3, X3, #1

0x43ca54 CMP	X3, X19

0x43ca58 B.EQ	43ceac

0x43ca5c LDR	X21, [X0, X3,LSL #3]

0x43ca60 LDR	X13, [X22, X21,LSL #3]

0x43ca64 CMP	X13, X5

0x43ca68 B.GE	43ca40

0x43ca6c CMP	X13, X6

0x43ca70 B.NE	43cac4

0x43ca74 LDUR	X13, [X29, #496]

0x43ca78 ADD	X14, X21, #1

0x43ca7c LDR	D4, [X13]

0x43ca80 LDUR	X13, [X29, #432]

0x43ca84 LDR	X16, [X13, X21,LSL #3]

0x43ca88 LDR	X20, [X13, X14,LSL #3]

0x43ca8c LDR	D3, [X17, X16,LSL #3]

0x43ca90 ADD	X2, X16, #1

0x43ca94 FCMP	D3, #0

0x43ca98 FCSEL	D3, D1, D0, #4

0x43ca9c CMP	X2, X20

0x43caa0 B.GE	43cbc8

0x43caa4 ORN	W13, WZR, W16

0x43caa8 ADD	W15, W20, W13

0x43caac SUB	X13, X20, #2

0x43cab0 TBNZ	W15, #0, 43caf8

0x43cab4 ORR	X15, XZR, X2

0x43cab8 CMP	X13, X16

0x43cabc B.NE	43cb3c

0x43cac0 B	43cbc8

0x43cac4 LDR	X13, [X10, X21,LSL #3]

0x43cac8 CMN	X13, #3

0x43cacc B.EQ	43ca50

0x43cad0 CMP	X25, #1

0x43cad4 B.EQ	43caec

0x43cad8 LDUR	X14, [X29, #296]

0x43cadc LDR	X13, [X14, X27,LSL #3]

0x43cae0 LDR	X14, [X14, X21,LSL #3]

0x43cae4 CMP	X13, X14

0x43cae8 B.NE	43ca50

0x43caec LDR	D3, [X17, X3,LSL #3]

0x43caf0 FADD	D2, D2, D3

0x43caf4 B	43ca50

0x43caf8 LDUR	X15, [X29, #448]

0x43cafc LDR	X15, [X15, X2,LSL #3]

0x43cb00 LDR	X17, [X22, X15,LSL #3]

0x43cb04 CMP	X17, X5

0x43cb08 CCMP	X15, X27, #4, #11

0x43cb0c B.NE	43cb2c

0x43cb10 LDUR	X17, [X29, #456]

0x43cb14 LDR	D5, [X17, X2,LSL #3]

0x43cb18 FMUL	D6, D3, D5

0x43cb1c FCMP	D6, #0

0x43cb20 B.PL	43cb30

0x43cb24 FADD	D4, D4, D5

0x43cb28 B	43cb30

0x43cb2c LDUR	X17, [X29, #456]

0x43cb30 ADD	X15, X16, #2

0x43cb34 CMP	X13, X16

0x43cb38 B.EQ	43cbc8

0x43cb3c SUB	X13, X20, X15

0x43cb40 UBFM	X17, X15, #61, #60

0x43cb44 LDP	X18, X15, [X29, #880]

0x43cb48 ADD	X15, X15, X17

0x43cb4c ADD	X18, X18, X17

0x43cb50 B	43cb70

  (177) 0x43cb60 SUBS	X13, X13, #2

  (177) 0x43cb64 ADD	X15, X15, #16

  (177) 0x43cb68 ADD	X18, X18, #16

  (177) 0x43cb6c B.EQ	43cbc4

  (177) 0x43cb70 LDUR	X17, [X15, #504]

  (177) 0x43cb74 LDR	X0, [X22, X17,LSL #3]

  (177) 0x43cb78 CMP	X0, X5

  (177) 0x43cb7c CCMP	X17, X27, #4, #11

  (177) 0x43cb80 B.NE	43cb98

  (177) 0x43cb84 LDUR	D5, [X18, #504]

  (177) 0x43cb88 FMUL	D6, D3, D5

  (177) 0x43cb8c FCMP	D6, #0

  (177) 0x43cb90 B.PL	43cb98

  (177) 0x43cb94 FADD	D4, D4, D5

  (177) 0x43cb98 LDR	X17, [X15]

  (177) 0x43cb9c LDR	X0, [X22, X17,LSL #3]

  (177) 0x43cba0 CMP	X0, X5

  (177) 0x43cba4 CCMP	X17, X27, #4, #11

  (177) 0x43cba8 B.NE	43cb60

  (177) 0x43cbac LDR	D5, [X18]

  (177) 0x43cbb0 FMUL	D6, D3, D5

  (177) 0x43cbb4 FCMP	D6, #0

  (177) 0x43cbb8 B.PL	43cb60

  (177) 0x43cbbc FADD	D4, D4, D5

  (177) 0x43cbc0 B	43cb60

0x43cbc4 LDUR	X17, [X29, #456]

0x43cbc8 CMP	X30, #2

0x43cbcc B.LT	43cc04

0x43cbd0 LDR	X18, [X26, X21,LSL #3]

0x43cbd4 LDR	X13, [X26, X14,LSL #3]

0x43cbd8 CMP	X13, X18

0x43cbdc B.LE	43cc04

0x43cbe0 LDUR	X15, [X29, #352]

0x43cbe4 SUB	W17, W13, W18

0x43cbe8 LDR	X15, [X15]

0x43cbec TBNZ	W17, #0, 43cce8

0x43cbf0 ORR	X0, XZR, X18

0x43cbf4 ADD	X17, X18, #1

0x43cbf8 CMP	X13, X17

0x43cbfc LDUR	X17, [X29, #456]

0x43cc00 B.NE	43cd24

0x43cc04 LDR	D5, [X17, X3,LSL #3]

0x43cc08 FCMP	D4, #0

0x43cc0c B.EQ	43cdac

0x43cc10 FDIV	D4, D5, D4

0x43cc14 CMP	X2, X20

0x43cc18 B.GE	43cca0

0x43cc1c LDUR	X13, [X29, #440]

0x43cc20 LDP	X15, X18, [X29, #880]

0x43cc24 UBFM	X17, X16, #61, #60

0x43cc28 ORN	X16, XZR, X16

0x43cc2c ADD	X16, X16, X20

0x43cc30 LDR	X13, [X13]

0x43cc34 ADD	X15, X15, X17

0x43cc38 ADD	X18, X18, X17

0x43cc3c B	43cc50

  (175) 0x43cc40 ADD	X15, X15, #8

  (175) 0x43cc44 SUBS	X16, X16, #1

  (175) 0x43cc48 ADD	X18, X18, #8

  (175) 0x43cc4c B.EQ	43cc9c

  (175) 0x43cc50 LDR	X0, [X18]

  (175) 0x43cc54 LDR	X2, [X22, X0,LSL #3]

  (175) 0x43cc58 CMP	X2, X5

  (175) 0x43cc5c B.LT	43cc7c

  (175) 0x43cc60 LDR	D5, [X15]

  (175) 0x43cc64 FMUL	D6, D3, D5

  (175) 0x43cc68 FCMP	D6, #0

  (175) 0x43cc6c B.PL	43cc7c

  (175) 0x43cc70 LDR	D6, [X13, X2,LSL #3]

  (175) 0x43cc74 FMADD	D5, D4, D5, D6

  (175) 0x43cc78 STR	D5, [X13, X2,LSL #3]

  (175) 0x43cc7c CMP	X0, X27

  (175) 0x43cc80 B.NE	43cc40

  (175) 0x43cc84 LDR	D5, [X15]

  (175) 0x43cc88 FMUL	D6, D3, D5

  (175) 0x43cc8c FCMP	D6, #0

  (175) 0x43cc90 B.PL	43cc40

  (175) 0x43cc94 FMADD	D2, D4, D5, D2

  (175) 0x43cc98 B	43cc40

0x43cc9c LDUR	X17, [X29, #456]

0x43cca0 LDUR	X0, [X29, #448]

0x43cca4 CMP	X30, #2

0x43cca8 B.LT	43ca50

0x43ccac LDR	X15, [X26, X21,LSL #3]

0x43ccb0 LDR	X14, [X26, X14,LSL #3]

0x43ccb4 CMP	X14, X15

0x43ccb8 B.LE	43ca50

0x43ccbc LDUR	X13, [X29, #352]

0x43ccc0 SUB	W17, W14, W15

0x43ccc4 LDR	X16, [X13]

0x43ccc8 LDUR	X13, [X29, #416]

0x43cccc LDR	X13, [X13]

0x43ccd0 TBNZ	W17, #0, 43cdb8

0x43ccd4 ORR	X18, XZR, X15

0x43ccd8 ADD	X15, X15, #1

0x43ccdc CMP	X14, X15

0x43cce0 B.EQ	43cdf8

0x43cce4 B	43ce00

0x43cce8 LDR	X17, [SP, #216]

0x43ccec LDR	X17, [X17, X18,LSL #3]

0x43ccf0 LDR	X17, [X23, X17,LSL #3]

0x43ccf4 CMP	X17, X1

0x43ccf8 B.LT	43cd10

0x43ccfc LDR	D5, [X15, X18,LSL #3]

0x43cd00 FMUL	D6, D3, D5

0x43cd04 FCMP	D6, #0

0x43cd08 B.PL	43cd10

0x43cd0c FADD	D4, D4, D5

0x43cd10 ADD	X0, X18, #1

0x43cd14 ADD	X17, X18, #1

0x43cd18 CMP	X13, X17

0x43cd1c LDUR	X17, [X29, #456]

0x43cd20 B.EQ	43cc04

0x43cd24 LDR	X18, [SP, #208]

0x43cd28 UBFM	X17, X0, #61, #60

0x43cd2c SUB	X13, X13, X0

0x43cd30 ADD	X15, X15, X17

0x43cd34 ADD	X15, X15, #8

0x43cd38 ADD	X18, X18, X17

0x43cd3c B	43cd50

  (176) 0x43cd40 SUBS	X13, X13, #2

  (176) 0x43cd44 ADD	X15, X15, #16

  (176) 0x43cd48 ADD	X18, X18, #16

  (176) 0x43cd4c B.EQ	43cd9c

  (176) 0x43cd50 LDUR	X17, [X18, #504]

  (176) 0x43cd54 LDR	X17, [X23, X17,LSL #3]

  (176) 0x43cd58 CMP	X17, X1

  (176) 0x43cd5c B.LT	43cd74

  (176) 0x43cd60 LDUR	D5, [X15, #504]

  (176) 0x43cd64 FMUL	D6, D3, D5

  (176) 0x43cd68 FCMP	D6, #0

  (176) 0x43cd6c B.PL	43cd74

  (176) 0x43cd70 FADD	D4, D4, D5

  (176) 0x43cd74 LDR	X17, [X18]

  (176) 0x43cd78 LDR	X17, [X23, X17,LSL #3]

  (176) 0x43cd7c CMP	X17, X1

  (176) 0x43cd80 B.LT	43cd40

  (176) 0x43cd84 LDR	D5, [X15]

  (176) 0x43cd88 FMUL	D6, D3, D5

  (176) 0x43cd8c FCMP	D6, #0

  (176) 0x43cd90 B.PL	43cd40

  (176) 0x43cd94 FADD	D4, D4, D5

  (176) 0x43cd98 B	43cd40

0x43cd9c LDUR	X17, [X29, #456]

0x43cda0 LDR	D5, [X17, X3,LSL #3]

0x43cda4 FCMP	D4, #0

0x43cda8 B.NE	43cc10

0x43cdac LDUR	X0, [X29, #448]

0x43cdb0 FADD	D2, D2, D5

0x43cdb4 B	43ca50

0x43cdb8 LDR	X17, [SP, #216]

0x43cdbc LDR	X17, [X17, X15,LSL #3]

0x43cdc0 LDR	X18, [X23, X17,LSL #3]

0x43cdc4 CMP	X18, X1

0x43cdc8 B.LT	43cde8

0x43cdcc LDR	D5, [X16, X15,LSL #3]

0x43cdd0 FMUL	D6, D3, D5

0x43cdd4 FCMP	D6, #0

0x43cdd8 B.PL	43cde8

0x43cddc LDR	D6, [X13, X18,LSL #3]

0x43cde0 FMADD	D5, D4, D5, D6

0x43cde4 STR	D5, [X13, X18,LSL #3]

0x43cde8 ADD	X18, X15, #1

0x43cdec ADD	X15, X15, #1

0x43cdf0 CMP	X14, X15

0x43cdf4 B.NE	43ce00

0x43cdf8 LDUR	X17, [X29, #456]

0x43cdfc B	43ca50

0x43ce00 UBFM	X17, X18, #61, #60

0x43ce04 SUB	X14, X14, X18

0x43ce08 ADD	X15, X16, X17

0x43ce0c LDR	X16, [SP, #208]

0x43ce10 ADD	X15, X15, #8

0x43ce14 ADD	X16, X16, X17

0x43ce18 B	43ce30

  (174) 0x43ce20 SUBS	X14, X14, #2

  (174) 0x43ce24 ADD	X15, X15, #16

  (174) 0x43ce28 ADD	X16, X16, #16

  (174) 0x43ce2c B.EQ	43cdf8

  (174) 0x43ce30 LDUR	X17, [X16, #504]

  (174) 0x43ce34 LDR	X18, [X23, X17,LSL #3]

  (174) 0x43ce38 CMP	X18, X1

  (174) 0x43ce3c B.LT	43ce5c

  (174) 0x43ce40 LDUR	D5, [X15, #504]

  (174) 0x43ce44 FMUL	D6, D3, D5

  (174) 0x43ce48 FCMP	D6, #0

  (174) 0x43ce4c B.PL	43ce5c

  (174) 0x43ce50 LDR	D6, [X13, X18,LSL #3]

  (174) 0x43ce54 FMADD	D5, D4, D5, D6

  (174) 0x43ce58 STR	D5, [X13, X18,LSL #3]

  (174) 0x43ce5c LDR	X17, [X16]

  (174) 0x43ce60 LDR	X18, [X23, X17,LSL #3]

  (174) 0x43ce64 CMP	X18, X1

  (174) 0x43ce68 B.LT	43ce20

  (174) 0x43ce6c LDR	D5, [X15]

  (174) 0x43ce70 FMUL	D6, D3, D5

  (174) 0x43ce74 FCMP	D6, #0

  (174) 0x43ce78 B.PL	43ce20

  (174) 0x43ce7c LDR	D6, [X13, X18,LSL #3]

  (174) 0x43ce80 FMADD	D5, D4, D5, D6

  (174) 0x43ce84 STR	D5, [X13, X18,LSL #3]

  (174) 0x43ce88 B	43ce20

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1609 - 1675

--------------------------------------------------------------------------------

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.16
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	.omp_outlined.#0x43b900
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1644,par_lr_interp.c:1651-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.63
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	21.63
CQA cycles if fully vectorized	5.41
Front-end cycles	21.63
DIV/SQRT cycles	19.50
P0 cycles	19.50
P1 cycles	14.75
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	6.00
P6 cycles	4.50
P7 cycles	4.25
P8 cycles	4.25
P9 cycles	19.33
P10 cycles	19.33
P11 cycles	19.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	173.00
Nb uops	173.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.51
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.20
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.16
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	.omp_outlined.#0x43b900
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1637,par_lr_interp.c:1640-1644,par_lr_interp.c:1651-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	21.63
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	21.63
CQA cycles if fully vectorized	5.41
Front-end cycles	21.63
DIV/SQRT cycles	19.50
P0 cycles	19.50
P1 cycles	14.75
P2 cycles	14.75
P3 cycles	14.75
P4 cycles	14.75
P5 cycles	6.00
P6 cycles	4.50
P7 cycles	4.25
P8 cycles	4.25
P9 cycles	19.33
P10 cycles	19.33
P11 cycles	19.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	173.00
Nb uops	173.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.51
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.20
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x43b900
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609-1660,1667-1675.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609,1612-1621,1624-1637,1640-1644,1651-1660,1667,1672-1675.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.63 to 10.00 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 21.63 to 5.41 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

6: addition or subtraction (1 inside FMA instructions)
4: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 464 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	173
loop length	692
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.50	19.50	14.75	14.75	14.75	14.75	6.00	4.50	4.25	4.25	19.33	19.33	19.33	0.00	0.00
cycles	19.50	19.50	14.75	14.75	14.75	14.75	6.00	4.50	4.25	4.25	19.33	19.33	19.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.63
Overall L1	21.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.63 cycles. At this rate:

22% of peak load performance is reached (21.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43ca5c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D3, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43ceac <.omp_outlined.+0x15ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X22, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43ca40 <.omp_outlined.+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43cac4 <.omp_outlined.+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X20, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X17, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D3, D1, D0, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
CMP X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORN W13, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W15, W20, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X13, X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W15, #0, 43caf8 <.omp_outlined.+0x11f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43cb3c <.omp_outlined.+0x123c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43caec <.omp_outlined.+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X14, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X15, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X15, X27, #4, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 43cb2c <.omp_outlined.+0x122c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cb30 <.omp_outlined.+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43cb30 <.omp_outlined.+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X17, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X15, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cb70 <.omp_outlined.+0x1270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W17, W13, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ W17, #0, 43cce8 <.omp_outlined.+0x13e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.NE 43cd24 <.omp_outlined.+0x1424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.EQ 43cdac <.omp_outlined.+0x14ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D4, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50
CMP X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43cca0 <.omp_outlined.+0x13a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X15, X18, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X16, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cc50 <.omp_outlined.+0x1350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W17, W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X13, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ W17, #0, 43cdb8 <.omp_outlined.+0x14b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43cdf8 <.omp_outlined.+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43ce00 <.omp_outlined.+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X17, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cd10 <.omp_outlined.+0x1410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X15, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cd10 <.omp_outlined.+0x1410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.EQ 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X17, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cd50 <.omp_outlined.+0x1450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 43cc10 <.omp_outlined.+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FADD D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cde8 <.omp_outlined.+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cde8 <.omp_outlined.+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D6, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D4, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D5, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43ce00 <.omp_outlined.+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X17, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X14, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43ce30 <.omp_outlined.+0x1530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x43b900
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

6: addition or subtraction (1 inside FMA instructions)
4: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 464 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	173
loop length	692
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.50	19.50	14.75	14.75	14.75	14.75	6.00	4.50	4.25	4.25	19.33	19.33	19.33	0.00	0.00
cycles	19.50	19.50	14.75	14.75	14.75	14.75	6.00	4.50	4.25	4.25	19.33	19.33	19.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.63
Overall L1	21.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.63 cycles. At this rate:

22% of peak load performance is reached (21.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43ca5c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D3, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43ceac <.omp_outlined.+0x15ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X22, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43ca40 <.omp_outlined.+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43cac4 <.omp_outlined.+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X20, [X13, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X17, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D3, D1, D0, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
CMP X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORN W13, WZR, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W15, W20, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X13, X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W15, #0, 43caf8 <.omp_outlined.+0x11f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43cb3c <.omp_outlined.+0x123c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43caec <.omp_outlined.+0x11ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X14, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X15, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X15, X27, #4, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 43cb2c <.omp_outlined.+0x122c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cb30 <.omp_outlined.+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43cb30 <.omp_outlined.+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43cbc8 <.omp_outlined.+0x12c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X17, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X15, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cb70 <.omp_outlined.+0x1270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W17, W13, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ W17, #0, 43cce8 <.omp_outlined.+0x13e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.NE 43cd24 <.omp_outlined.+0x1424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.EQ 43cdac <.omp_outlined.+0x14ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D4, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50
CMP X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 43cca0 <.omp_outlined.+0x13a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X15, X18, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORN X16, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cc50 <.omp_outlined.+0x1350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X26, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W17, W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X13, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
TBNZ W17, #0, 43cdb8 <.omp_outlined.+0x14b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 43cdf8 <.omp_outlined.+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43ce00 <.omp_outlined.+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X17, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cd10 <.omp_outlined.+0x1410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X15, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cd10 <.omp_outlined.+0x1410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.EQ 43cc04 <.omp_outlined.+0x1304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X17, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43cd50 <.omp_outlined.+0x1450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 43cc10 <.omp_outlined.+0x1310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FADD D2, D2, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X17, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X23, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 43cde8 <.omp_outlined.+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D5, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 43cde8 <.omp_outlined.+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D6, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D4, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D5, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X18, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 43ce00 <.omp_outlined.+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 43ca50 <.omp_outlined.+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X17, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X14, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 43ce30 <.omp_outlined.+0x1530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code