OV - exec - Loop 1721

0x432e44 ADD	X1, X1, #1

0x432e48 CMP	X1, X3

0x432e4c B.GE	432e80

0x432e50 LDR	X5, [X11, X1,LSL #3]    [2]

0x432e54 LDR	X5, [X12, X5,LSL #3]    [5]

0x432e58 CMP	X5, #1

0x432e5c B.NE	432e44

0x432e60 LDR	X3, [X2, X0,LSL #3]    [4]

0x432e64 ADD	X20, X20, #1

0x432e68 ADD	X3, X3, #1

0x432e6c STR	X3, [X2, X0,LSL #3]    [4]

0x432e70 STR	X16, [X4, X18,LSL #3]    [1]

0x432e74 LDR	X3, [X10, X0,LSL #3]    [3]

0x432e78 B	432e44

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 491 - 498

--------------------------------------------------------------------------------

491:      for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

492:      {

493:         j1 = S_diag_j[j];

494:         if (CF_marker[j1] == 1)

495:         {

496:            P_diag_i[i1+1]++;

497:            cnt_nz++;

498:            assigned[i1] = 1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:491-498
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.38
Front-end cycles	1.31
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.50
Nb uops	10.50
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:491-498
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.75
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:491-498
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.25
Front-end cycles	0.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	7.00
Nb uops	7.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:491-498
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:491-498.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	10.50
loop length	42
nb stack references	0

Front-end

front end

1.31 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.25	1.25	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.50	0.50
cycles	1.25	1.25	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.31
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:491-498
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:491-498.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	2.00	2.00	2.00	1.00	1.00
cycles	1.50	1.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	2.00	2.00	2.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.75
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 432e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 432e80 <hypre_BoomerAMGBuildMultipass+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 432e44 <hypre_BoomerAMGBuildMultipass+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 432e44 <hypre_BoomerAMGBuildMultipass+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:491-498
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:491-498.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

Unroll opportunity

Loop body is too small to efficiently use resources.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually.

General properties

nb instructions	7
loop length	28
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.88
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 432e50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 432e80 <hypre_BoomerAMGBuildMultipass+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X5, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 432e44 <hypre_BoomerAMGBuildMultipass+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code