OV - exec - Loop 1504

  (1503) 0x42e228 ORR	X0, XZR, X21

  (1503) 0x42e22c ORR	X1, XZR, X20

  (1503) 0x42e230 ORR	X2, XZR, X22

  (1503) 0x42e234 ORR	X3, XZR, X23

  (1503) 0x42e238 BL	4aea80

  (1503) 0x42e23c ORR	X0, XZR, X21

  (1503) 0x42e240 ORR	X1, XZR, X20

  (1503) 0x42e244 SUB	X3, X23, #1

  (1503) 0x42e248 ORR	X2, XZR, X22

  (1503) 0x42e24c BL	42e1f0

  (1503) 0x42e250 ADD	X22, X23, #1

  (1503) 0x42e254 CMP	X22, X19

  (1503) 0x42e258 B.GE	42e2e4

  (1503) 0x42e25c ADD	X8, X22, X19

  (1503) 0x42e260 ORR	X0, XZR, X21

  (1503) 0x42e264 CMP	X8, #0

  (1503) 0x42e268 ORR	X1, XZR, X20

  (1503) 0x42e26c ORR	X2, XZR, X22

  (1503) 0x42e270 CSINC	X8, X8, X8, #10

  (1503) 0x42e274 SBFM	X3, X8, #1, #63

  (1503) 0x42e278 BL	4aea80

  (1503) 0x42e27c ORR	X23, XZR, X22

  (1503) 0x42e280 CMP	X22, X19

  (1503) 0x42e284 B.GE	42e228

0x42e288 ORR	X23, XZR, X22

0x42e28c ADD	X24, X22, #1

0x42e290 B	42e2b0

0x42e2a0 ADD	X24, X24, #1

0x42e2a4 ADD	X8, X25, X24

0x42e2a8 CMP	X8, #1

0x42e2ac B.EQ	42e228

0x42e2b0 LDR	D0, [X20, X24,LSL #3]

0x42e2b4 LDR	D1, [X20, X22,LSL #3]

0x42e2b8 FABS	D0, D0

0x42e2bc FABS	D1, D1

0x42e2c0 FCMP	D0, D1

0x42e2c4 B.LE	42e2a0

0x42e2c8 ADD	X23, X23, #1

0x42e2cc ORR	X0, XZR, X21

0x42e2d0 ORR	X1, XZR, X20

0x42e2d4 ORR	X3, XZR, X24

0x42e2d8 ORR	X2, XZR, X23

0x42e2dc BL	4aea80

0x42e2e0 B	42e2a0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3180 - 3191

--------------------------------------------------------------------------------

3180:    if (left >= right)

3181:       return;

3182:    hypre_swap2( v, w, left, (left+right)/2);

3183:    last = left;

3184:    for (i = left+1; i <= right; i++)

3185:       if (fabs(w[i]) > fabs(w[left]))

3186:       {

3187:          hypre_swap2(v, w, ++last, i);

3188:       }

3189:    hypre_swap2(v, w, left, last);

3190:    hypre_qsort2abs(v, w, left, last-1);

3191:    hypre_qsort2abs(v, w, last+1, right);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	4.12
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P2, P3, P4, P5,
Function	hypre_qsort2abs
Source	par_interp.c:3184-3187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	0.67
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.69
Front-end cycles	2.50
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.50
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.82
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	4.12
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P2, P3, P4, P5,
Function	hypre_qsort2abs
Source	par_interp.c:3184-3187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	0.67
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.69
Front-end cycles	2.50
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	1.00
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.50
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.82
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_qsort2abs
Source file and lines	par_interp.c:3180-3191
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3180-3191.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3184-3187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 0.67 cycles (4.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.69 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.75 to 0.50 cycles (5.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	1.00	0.75	0.75	0.50	0.67	0.67	0.67	0.00	0.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	1.00	0.75	0.75	0.50	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

6% of peak load performance is reached (5.82 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X23, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X24, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 42e2b0 <hypre_qsort2abs+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e228 <hypre_qsort2abs+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X20, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X20, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FABS D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 42e2a0 <hypre_qsort2abs+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4aea80 <hypre_swap2>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 42e2a0 <hypre_qsort2abs+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_qsort2abs
Source file and lines	par_interp.c:3180-3191
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3180-3191.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3184-3187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 0.67 cycles (4.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.69 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.75 to 0.50 cycles (5.50x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	1.00	0.75	0.75	0.50	0.67	0.67	0.67	0.00	0.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	1.00	0.75	0.75	0.50	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

6% of peak load performance is reached (5.82 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X23, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X24, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 42e2b0 <hypre_qsort2abs+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X24, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42e228 <hypre_qsort2abs+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X20, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X20, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FABS D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 42e2a0 <hypre_qsort2abs+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4aea80 <hypre_swap2>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 42e2a0 <hypre_qsort2abs+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code