OV - exec - Loop 1313

0x4a7d40 LDR	X3, [X11, X1,LSL #3]    [2]

0x4a7d44 LDR	D0, [X12, X1,LSL #3]    [3]

0x4a7d48 LDR	D1, [X13, X9,LSL #3]    [4]

0x4a7d4c ADD	X1, X1, #1

0x4a7d50 SUBS	X2, X2, #1

0x4a7d54 LDR	D2, [X14, X3,LSL #3]    [1]

0x4a7d58 FMADD	D0, D0, D1, D2

0x4a7d5c STR	D0, [X14, X3,LSL #3]    [1]

0x4a7d60 B.NE	4a7d40

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 564 - 567

--------------------------------------------------------------------------------

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P10,
Function	.omp_outlined..26#0x4a7a70
Source	csr_matvec.c:564-567
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	1.83
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.46
Front-end cycles	1.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.09
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P10,
Function	.omp_outlined..26#0x4a7a70
Source	csr_matvec.c:564-567
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	1.83
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.46
Front-end cycles	1.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.09
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..26#0x4a7a70
Source file and lines	csr_matvec.c:564-567
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564-567.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.83 to 1.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

FMA

Detected 1 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Data deps.	1.00
Overall L1	1.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a7d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X3, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR D2, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D0, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D0, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 4a7d40 <.omp_outlined..26+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..26#0x4a7a70
Source file and lines	csr_matvec.c:564-567
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564-567.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.83 to 1.50 cycles (1.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

FMA

Detected 1 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
1: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	9
loop length	36
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	1.83	1.50	1.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	1.83	1.50	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Data deps.	1.00
Overall L1	1.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a7d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X3, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X13, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR D2, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D0, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D0, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.NE 4a7d40 <.omp_outlined..26+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code