OV - exec - Loop 1261

	Loop Id: 1261	Module: exec	Source: par_multi_interp.c:1774-1876 [...]	Coverage: 0.16%

0x438404 LDUR	X8, [X29, #400]

0x438408 ADD	X25, X25, #1

0x43840c CMP	X25, X8

0x438410 B.GE	438bd8

0x438414 LDUR	X8, [X29, #432]

0x438418 LDR	X12, [X8, X25,LSL #3]

0x43841c LDUR	X8, [X29, #424]

0x438420 ADD	X13, X12, #1

0x438424 LDR	X8, [X8, X12,LSL #3]

0x438428 LDR	X10, [X14, X12,LSL #3]

0x43842c LDR	X11, [X14, X13,LSL #3]

0x438430 ADD	X9, X11, X8

0x438434 SUB	X9, X9, X10

0x438438 CMP	X8, X9

0x43843c B.GE	4384d8

0x438440 SUB	W16, W11, W10

0x438444 ADD	X15, X10, #1

0x438448 TBZ	W16, #0, 438474

0x43844c LDR	X16, [X28]

0x438450 LDR	X18, [SP, #168]

0x438454 LDR	X16, [X1, X16,LSL #3]

0x438458 STR	XZR, [X18, X10,LSL #3]

0x43845c LDR	X18, [SP, #40]

0x438460 LDR	X16, [X16, X8,LSL #3]

0x438464 ADD	X8, X8, #1

0x438468 STR	X10, [X21, X16,LSL #3]

0x43846c STR	X16, [X18, X10,LSL #3]

0x438470 ORR	X10, XZR, X15

0x438474 CMP	X11, X15

0x438478 B.EQ	4384d8

0x43847c LDP	X16, X11, [SP, #16]

0x438480 UBFM	X15, X10, #61, #60

0x438484 ADD	X11, X11, X15

0x438488 ADD	X16, X16, X15

  (1268) 0x43848c LDR	X15, [X28]

  (1268) 0x438490 UBFM	X0, X8, #61, #60

  (1268) 0x438494 ADD	X8, X8, #2

  (1268) 0x438498 CMP	X9, X8

  (1268) 0x43849c LDR	X15, [X1, X15,LSL #3]

  (1268) 0x4384a0 LDR	X15, [X15, X0]

  (1268) 0x4384a4 STR	X10, [X21, X15,LSL #3]

  (1268) 0x4384a8 STP	XZR, XZR, [X16, #1016]

  (1268) 0x4384ac STUR	X15, [X11, #504]

  (1268) 0x4384b0 ADD	X16, X16, #16

  (1268) 0x4384b4 LDR	X15, [X28]

  (1268) 0x4384b8 LDR	X15, [X1, X15,LSL #3]

  (1268) 0x4384bc ADD	X15, X15, X0

  (1268) 0x4384c0 ADD	X0, X10, #1

  (1268) 0x4384c4 ADD	X10, X10, #2

  (1268) 0x4384c8 LDR	X15, [X15, #8]

  (1268) 0x4384cc STR	X0, [X21, X15,LSL #3]

  (1268) 0x4384d0 STR	X15, [X11], #16

  (1268) 0x4384d4 B.NE	43848c

0x4384d8 LDUR	X8, [X29, #416]

0x4384dc LDR	X11, [X17, X13,LSL #3]

0x4384e0 LDR	X10, [X17, X12,LSL #3]

0x4384e4 LDR	X8, [X8, X12,LSL #3]

0x4384e8 ADD	X9, X11, X8

0x4384ec SUB	X9, X9, X10

0x4384f0 CMP	X8, X9

0x4384f4 B.GE	438590

0x4384f8 SUB	W16, W11, W10

0x4384fc ADD	X15, X10, #1

0x438500 TBZ	W16, #0, 43852c

0x438504 LDR	X16, [X28]

0x438508 LDR	X18, [SP, #160]

0x43850c LDR	X16, [X2, X16,LSL #3]

0x438510 STR	XZR, [X18, X10,LSL #3]

0x438514 LDR	X18, [SP, #32]

0x438518 LDR	X16, [X16, X8,LSL #3]

0x43851c ADD	X8, X8, #1

0x438520 STR	X10, [X22, X16,LSL #3]

0x438524 STR	X16, [X18, X10,LSL #3]

0x438528 ORR	X10, XZR, X15

0x43852c CMP	X11, X15

0x438530 B.EQ	438590

0x438534 LDP	X16, X11, [SP]

0x438538 UBFM	X15, X10, #61, #60

0x43853c ADD	X11, X11, X15

0x438540 ADD	X16, X16, X15

  (1267) 0x438544 LDR	X15, [X28]

  (1267) 0x438548 UBFM	X0, X8, #61, #60

  (1267) 0x43854c ADD	X8, X8, #2

  (1267) 0x438550 CMP	X9, X8

  (1267) 0x438554 LDR	X15, [X2, X15,LSL #3]

  (1267) 0x438558 LDR	X15, [X15, X0]

  (1267) 0x43855c STR	X10, [X22, X15,LSL #3]

  (1267) 0x438560 STP	XZR, XZR, [X16, #1016]

  (1267) 0x438564 STUR	X15, [X11, #504]

  (1267) 0x438568 ADD	X16, X16, #16

  (1267) 0x43856c LDR	X15, [X28]

  (1267) 0x438570 LDR	X15, [X2, X15,LSL #3]

  (1267) 0x438574 ADD	X15, X15, X0

  (1267) 0x438578 ADD	X0, X10, #1

  (1267) 0x43857c ADD	X10, X10, #2

  (1267) 0x438580 LDR	X15, [X15, #8]

  (1267) 0x438584 STR	X0, [X22, X15,LSL #3]

  (1267) 0x438588 STR	X15, [X11], #16

  (1267) 0x43858c B.NE	438544

0x438590 LDR	X8, [X3, X12,LSL #3]

0x438594 LDR	X9, [X3, X13,LSL #3]

0x438598 B	4385a4

  (1266) 0x4385a0 ADD	X8, X8, #1

  (1266) 0x4385a4 CMP	X8, X9

  (1266) 0x4385a8 B.GE	4385e0

  (1266) 0x4385ac LDR	X10, [X4, X8,LSL #3]

  (1266) 0x4385b0 LDR	X15, [X28]

  (1266) 0x4385b4 LDR	X11, [X5, X10,LSL #3]

  (1266) 0x4385b8 SUB	X15, X15, #1

  (1266) 0x4385bc CMP	X11, X15

  (1266) 0x4385c0 B.NE	4385a0

  (1266) 0x4385c4 STR	X12, [X19, X10,LSL #3]

  (1266) 0x4385c8 LDR	X9, [X3, X13,LSL #3]

  (1266) 0x4385cc B	4385a0

0x4385e0 LDR	X8, [X6, X12,LSL #3]

0x4385e4 LDR	X9, [X6, X13,LSL #3]

0x4385e8 B	4385f0

  (1265) 0x4385ec ADD	X8, X8, #1

  (1265) 0x4385f0 CMP	X8, X9

  (1265) 0x4385f4 B.GE	438620

  (1265) 0x4385f8 LDR	X10, [X23, X8,LSL #3]

  (1265) 0x4385fc LDR	X15, [X28]

  (1265) 0x438600 LDR	X11, [X24, X10,LSL #3]

  (1265) 0x438604 SUB	X15, X15, #1

  (1265) 0x438608 CMP	X11, X15

  (1265) 0x43860c B.NE	4385ec

  (1265) 0x438610 STR	X12, [X20, X10,LSL #3]

  (1265) 0x438614 LDR	X9, [X6, X13,LSL #3]

  (1265) 0x438618 B	4385ec

0x438620 LDUR	X8, [X29, #408]

0x438624 MOVI	D2, #0

0x438628 LDR	X10, [X8, X12,LSL #3]

0x43862c LDR	X7, [X8, X13,LSL #3]

0x438630 ADD	X9, X10, #1

0x438634 STUR	X10, [X29, #456]

0x438638 CMP	X9, X7

0x43863c B.GE	4388a4

0x438640 LDP	X10, X11, [X29, #952]

0x438644 LDR	X8, [SP, #56]

0x438648 MOVI	D1, #0

0x43864c MOVI	D2, #0

0x438650 LDR	X6, [X11]

0x438654 LDR	X11, [SP, #152]

0x438658 LDR	X8, [X8]

0x43865c LDR	X10, [X10]

0x438660 LDR	X26, [X11]

0x438664 LDR	X11, [SP, #136]

0x438668 LDR	X2, [X11]

0x43866c LDUR	X11, [X29, #488]

0x438670 LDR	X27, [X11]

0x438674 LDR	X11, [SP, #144]

0x438678 LDR	X4, [X11]

0x43867c LDUR	X11, [X29, #496]

0x438680 ADD	X5, X27, #8

0x438684 LDR	X24, [X11]

0x438688 ADD	X11, X2, #8

0x43868c STUR	X11, [X29, #480]

0x438690 ADD	X11, X24, #8

0x438694 STUR	X11, [X29, #472]

0x438698 ADD	X11, X4, #8

0x43869c STUR	X11, [X29, #464]

0x4386a0 LDR	X18, [SP, #48]

0x4386a4 B	4386cc

  (1262) 0x4386a8 LDR	D3, [X26, X9,LSL #3]

  (1262) 0x4386ac FADD	D1, D1, D3

  (1262) 0x4386b0 HINT	#0

  (1262) 0x4386b4 HINT	#0

  (1262) 0x4386b8 HINT	#0

  (1262) 0x4386bc HINT	#0

  (1262) 0x4386c0 ADD	X9, X9, #1

  (1262) 0x4386c4 CMP	X9, X7

  (1262) 0x4386c8 B.EQ	4388c0

  (1262) 0x4386cc LDR	X23, [X18, X9,LSL #3]

  (1262) 0x4386d0 LDR	X11, [X19, X23,LSL #3]

  (1262) 0x4386d4 CMP	X11, X12

  (1262) 0x4386d8 B.NE	438708

  (1262) 0x4386dc ADD	X11, X23, #1

  (1262) 0x4386e0 LDR	X16, [X14, X23,LSL #3]

  (1262) 0x4386e4 LDR	X0, [X14, X11,LSL #3]

  (1262) 0x4386e8 CMP	X0, X16

  (1262) 0x4386ec B.LE	4387d8

  (1262) 0x4386f0 SUB	W15, W0, W16

  (1262) 0x4386f4 ADD	X1, X16, #1

  (1262) 0x4386f8 TBNZ	W15, #0, 438730

  (1262) 0x4386fc CMP	X0, X1

  (1262) 0x438700 B.NE	438764

  (1262) 0x438704 B	4387d8

  (1262) 0x438708 LDR	X11, [X8, X23,LSL #3]

  (1262) 0x43870c CMN	X11, #3

  (1262) 0x438710 B.EQ	4386c0

  (1262) 0x438714 CMP	X10, #1

  (1262) 0x438718 B.EQ	4386a8

  (1262) 0x43871c LDR	X11, [X6, X12,LSL #3]

  (1262) 0x438720 LDR	X15, [X6, X23,LSL #3]

  (1262) 0x438724 CMP	X11, X15

  (1262) 0x438728 B.EQ	4386a8

  (1262) 0x43872c B	4386c0

  (1262) 0x438730 LDR	X15, [X2, X16,LSL #3]

  (1262) 0x438734 LDR	D0, [X26, X9,LSL #3]

  (1262) 0x438738 LDR	D3, [X27, X16,LSL #3]

  (1262) 0x43873c ORR	X16, XZR, X1

  (1262) 0x438740 FMUL	D0, D0, D3

  (1262) 0x438744 LDR	X15, [X21, X15,LSL #3]

  (1262) 0x438748 LDR	D3, [X27, X15,LSL #3]

  (1262) 0x43874c FADD	D2, D2, D0

  (1262) 0x438750 FADD	D1, D1, D0

  (1262) 0x438754 FADD	D3, D0, D3

  (1262) 0x438758 STR	D3, [X27, X15,LSL #3]

  (1262) 0x43875c CMP	X0, X1

  (1262) 0x438760 B.EQ	4387d8

  (1262) 0x438764 LDUR	X3, [X29, #480]

  (1262) 0x438768 UBFM	X15, X16, #61, #60

  (1262) 0x43876c SUB	X0, X0, X16

  (1262) 0x438770 ADD	X1, X5, X15

  (1262) 0x438774 ADD	X3, X3, X15

  (1262) 0x438778 HINT	#0

  (1262) 0x43877c HINT	#0

    (1264) 0x438780 LDUR	X15, [X3, #504]

    (1264) 0x438784 LDR	D0, [X26, X9,LSL #3]

    (1264) 0x438788 LDUR	D3, [X1, #504]

    (1264) 0x43878c SUBS	X0, X0, #2

    (1264) 0x438790 FMUL	D0, D0, D3

    (1264) 0x438794 LDR	X15, [X21, X15,LSL #3]

    (1264) 0x438798 LDR	D3, [X27, X15,LSL #3]

    (1264) 0x43879c FADD	D2, D2, D0

    (1264) 0x4387a0 FADD	D1, D1, D0

    (1264) 0x4387a4 FADD	D3, D0, D3

    (1264) 0x4387a8 STR	D3, [X27, X15,LSL #3]

    (1264) 0x4387ac LDR	X15, [X3], #16

    (1264) 0x4387b0 LDR	D0, [X26, X9,LSL #3]

    (1264) 0x4387b4 LDR	D3, [X1], #16

    (1264) 0x4387b8 FMUL	D0, D0, D3

    (1264) 0x4387bc LDR	X15, [X21, X15,LSL #3]

    (1264) 0x4387c0 LDR	D3, [X27, X15,LSL #3]

    (1264) 0x4387c4 FADD	D2, D2, D0

    (1264) 0x4387c8 FADD	D1, D1, D0

    (1264) 0x4387cc FADD	D3, D0, D3

    (1264) 0x4387d0 STR	D3, [X27, X15,LSL #3]

    (1264) 0x4387d4 B.NE	438780

  (1262) 0x4387d8 LDR	X16, [X17, X23,LSL #3]

  (1262) 0x4387dc LDR	X11, [X17, X11,LSL #3]

  (1262) 0x4387e0 CMP	X11, X16

  (1262) 0x4387e4 B.LE	4386c0

  (1262) 0x4387e8 SUB	W15, W11, W16

  (1262) 0x4387ec ADD	X0, X16, #1

  (1262) 0x4387f0 TBNZ	W15, #0, 438800

  (1262) 0x4387f4 CMP	X11, X0

  (1262) 0x4387f8 B.EQ	4386c0

  (1262) 0x4387fc B	438834

  (1262) 0x438800 LDR	X15, [X4, X16,LSL #3]

  (1262) 0x438804 LDR	D0, [X26, X9,LSL #3]

  (1262) 0x438808 LDR	D3, [X24, X16,LSL #3]

  (1262) 0x43880c ORR	X16, XZR, X0

  (1262) 0x438810 FMUL	D0, D0, D3

  (1262) 0x438814 LDR	X15, [X22, X15,LSL #3]

  (1262) 0x438818 LDR	D3, [X24, X15,LSL #3]

  (1262) 0x43881c FADD	D2, D2, D0

  (1262) 0x438820 FADD	D1, D1, D0

  (1262) 0x438824 FADD	D3, D0, D3

  (1262) 0x438828 STR	D3, [X24, X15,LSL #3]

  (1262) 0x43882c CMP	X11, X0

  (1262) 0x438830 B.EQ	4386c0

  (1262) 0x438834 LDP	X1, X0, [X29, #976]

  (1262) 0x438838 UBFM	X15, X16, #61, #60

  (1262) 0x43883c SUB	X11, X11, X16

  (1262) 0x438840 ADD	X0, X0, X15

  (1262) 0x438844 ADD	X1, X1, X15

    (1263) 0x438848 LDUR	X15, [X1, #504]

    (1263) 0x43884c LDR	D0, [X26, X9,LSL #3]

    (1263) 0x438850 LDUR	D3, [X0, #504]

    (1263) 0x438854 SUBS	X11, X11, #2

    (1263) 0x438858 FMUL	D0, D0, D3

    (1263) 0x43885c LDR	X15, [X22, X15,LSL #3]

    (1263) 0x438860 LDR	D3, [X24, X15,LSL #3]

    (1263) 0x438864 FADD	D2, D2, D0

    (1263) 0x438868 FADD	D1, D1, D0

    (1263) 0x43886c FADD	D3, D0, D3

    (1263) 0x438870 STR	D3, [X24, X15,LSL #3]

    (1263) 0x438874 LDR	X15, [X1], #16

    (1263) 0x438878 LDR	D0, [X26, X9,LSL #3]

    (1263) 0x43887c LDR	D3, [X0], #16

    (1263) 0x438880 FMUL	D0, D0, D3

    (1263) 0x438884 LDR	X15, [X22, X15,LSL #3]

    (1263) 0x438888 LDR	D3, [X24, X15,LSL #3]

    (1263) 0x43888c FADD	D2, D2, D0

    (1263) 0x438890 FADD	D1, D1, D0

    (1263) 0x438894 FADD	D3, D0, D3

    (1263) 0x438898 STR	D3, [X24, X15,LSL #3]

    (1263) 0x43889c B.NE	438848

  (1262) 0x4388a0 B	4386c0

0x4388a4 MOVI	D1, #0

0x4388a8 LDUR	X9, [X29, #392]

0x4388ac LDR	X8, [X9, X12,LSL #3]

0x4388b0 LDR	X9, [X9, X13,LSL #3]

0x4388b4 CMP	X8, X9

0x4388b8 B.LT	4388ec

0x4388bc B	438a78

0x4388c0 LDP	X2, X1, [X29, #880]

0x4388c4 LDP	X4, X3, [X29, #864]

0x4388c8 LDP	X6, X5, [X29, #848]

0x4388cc CNTW	X26, ALL

0x4388d0 LDP	X24, X23, [SP, #176]

0x4388d4 LDUR	X10, [X29, #456]

0x4388d8 LDUR	X9, [X29, #392]

0x4388dc LDR	X8, [X9, X12,LSL #3]

0x4388e0 LDR	X9, [X9, X13,LSL #3]

0x4388e4 CMP	X8, X9

0x4388e8 B.GE	438a78

0x438a78 LDUR	X8, [X29, #384]

0x438a7c LDR	D3, [X8, X10,LSL #3]

0x438a80 FMUL	D2, D2, D3

0x438a84 FCMP	D2, #0

0x438a88 B.EQ	438a94

0x438a8c FNEG	D0, D1

0x438a90 FDIV	D0, D0, D2

0x438a94 LDR	X16, [X14, X12,LSL #3]

0x438a98 LDR	X8, [X14, X13,LSL #3]

0x438a9c SUBS	X11, X8, X16

0x438aa0 B.LE	438b34

0x438aa4 ORR	X9, XZR, X16

0x438aa8 CMP	X11, X26

0x438aac B.CC	438b08

0x438ab0 UDIV	X9, X11, X26

0x438ab4 LDR	X0, [SP, #168]

0x438ab8 UBFM	X18, X16, #61, #60

0x438abc ORR	X10, XZR, XZR

0x438ac0 DUP	Z1.D, Z0.D[0]

0x438ac4 MADD	X15, X9, X26, XZR

0x438ac8 ADD	X9, X16, X15

0x438acc ADD	X16, X0, X18

0x438ad0 ADDVL	X18, X18, #1

0x438ad4 SUB	X11, X11, X15

0x438ad8 ADD	X0, X0, X18

0x438adc HINT	#0

  (1272) 0x438ae0 LD1D	{Z2.D}, P0/Z, [X16, X10,LSL #3]

  (1272) 0x438ae4 LD1D	{Z3.D}, P0/Z, [X0, X10,LSL #3]

  (1272) 0x438ae8 FMUL	Z2.D, Z1.D, Z2.D

  (1272) 0x438aec FMUL	Z3.D, Z1.D, Z3.D

  (1272) 0x438af0 ST1D	{Z2.D}, P0, [X16, X10,LSL #3]

  (1272) 0x438af4 ST1D	{Z3.D}, P0, [X0, X10,LSL #3]

  (1272) 0x438af8 ADD	X10, X10, X26

  (1272) 0x438afc CMP	X15, X10

  (1272) 0x438b00 B.NE	438ae0

0x438b04 CBZ	X11, 438b34

0x438b08 LDR	X10, [SP, #168]

0x438b0c SUB	X8, X8, X9

0x438b10 ADD	X9, X10, X9,LSL #3

0x438b14 HINT	#0

0x438b18 HINT	#0

0x438b1c HINT	#0

  (1271) 0x438b20 LDR	D1, [X9]

  (1271) 0x438b24 SUBS	X8, X8, #1

  (1271) 0x438b28 FMUL	D1, D0, D1

  (1271) 0x438b2c STR	D1, [X9], #8

  (1271) 0x438b30 B.NE	438b20

0x438b34 LDR	X15, [X17, X12,LSL #3]

0x438b38 LDR	X8, [X17, X13,LSL #3]

0x438b3c SUBS	X11, X8, X15

0x438b40 B.LE	438404

0x438b44 ORR	X9, XZR, X15

0x438b48 CMP	X11, X26

0x438b4c B.CC	438ba8

0x438b50 UDIV	X9, X11, X26

0x438b54 LDR	X16, [SP, #160]

0x438b58 ORR	X10, XZR, XZR

0x438b5c DUP	Z1.D, Z0.D[0]

0x438b60 MADD	X12, X9, X26, XZR

0x438b64 ADD	X9, X15, X12

0x438b68 UBFM	X15, X15, #61, #60

0x438b6c SUB	X11, X11, X12

0x438b70 ADD	X13, X16, X15

0x438b74 ADDVL	X15, X15, #1

0x438b78 ADD	X15, X16, X15

0x438b7c HINT	#0

  (1270) 0x438b80 LD1D	{Z2.D}, P0/Z, [X13, X10,LSL #3]

  (1270) 0x438b84 LD1D	{Z3.D}, P0/Z, [X15, X10,LSL #3]

  (1270) 0x438b88 FMUL	Z2.D, Z1.D, Z2.D

  (1270) 0x438b8c FMUL	Z3.D, Z1.D, Z3.D

  (1270) 0x438b90 ST1D	{Z2.D}, P0, [X13, X10,LSL #3]

  (1270) 0x438b94 ST1D	{Z3.D}, P0, [X15, X10,LSL #3]

  (1270) 0x438b98 ADD	X10, X10, X26

  (1270) 0x438b9c CMP	X12, X10

  (1270) 0x438ba0 B.NE	438b80

0x438ba4 CBZ	X11, 438404

0x438ba8 LDR	X10, [SP, #160]

0x438bac SUB	X8, X8, X9

0x438bb0 ADD	X9, X10, X9,LSL #3

0x438bb4 HINT	#0

0x438bb8 HINT	#0

0x438bbc HINT	#0

  (1269) 0x438bc0 LDR	D1, [X9]

  (1269) 0x438bc4 SUBS	X8, X8, #1

  (1269) 0x438bc8 FMUL	D1, D0, D1

  (1269) 0x438bcc STR	D1, [X9], #8

  (1269) 0x438bd0 B.NE	438bc0

0x438bd4 B	438404

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

[...]

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.57 - 1.09
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20 - 1.69
Bottlenecks	P6, P8,
Function	.omp_outlined..22#0x4380e0
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.67 - 43.50
CQA cycles if no scalar integer	10.00 - 40.00
CQA cycles if FP arith vectorized	25.67 - 43.50
CQA cycles if fully vectorized	25.42 - 43.50
Front-end cycles	21.38
DIV/SQRT cycles	11.00
P0 cycles	11.00
P1 cycles	15.50
P2 cycles	15.50
P3 cycles	15.50
P4 cycles	15.50
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	25.67
P10 cycles	25.67
P11 cycles	25.67
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	11.75 - 43.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	179.00
Nb uops	171.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.08 - 0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.45 - 26.18
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.76
Vector-efficiency ratio all	31.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.82

Metric	Value
CQA speedup if no scalar integer	2.57 - 1.09
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20 - 1.69
Bottlenecks	P6, P8,
Function	.omp_outlined..22#0x4380e0
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.67 - 43.50
CQA cycles if no scalar integer	10.00 - 40.00
CQA cycles if FP arith vectorized	25.67 - 43.50
CQA cycles if fully vectorized	25.42 - 43.50
Front-end cycles	21.38
DIV/SQRT cycles	11.00
P0 cycles	11.00
P1 cycles	15.50
P2 cycles	15.50
P3 cycles	15.50
P4 cycles	15.50
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	25.67
P10 cycles	25.67
P11 cycles	25.67
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	11.75 - 43.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	179.00
Nb uops	171.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.08 - 0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.45 - 26.18
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.76
Vector-efficiency ratio all	31.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.82

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..22#0x4380e0
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1840,1865-1876.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1776,1779-1799,1805,1811,1824,1840,1865,1870-1875.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 43.50 to 40.00 cycles (1.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 31% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 592 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	15.50	15.50	15.50	15.50	2.50	2.50	2.50	2.50	25.67	25.67	25.67	5.00	5.00
cycles	11.00	11.00	15.50	15.50	15.50	15.50	2.50	2.50	2.50	2.50	25.67	25.67	25.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

11.75-43.50

Cycles summary

Front-end	21.38
Overall L1	25.67-43.50

Vectorization ratios

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

14% of peak load performance is reached (13.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438a78

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438bd8 <.omp_outlined..22+0xaf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4384d8 <.omp_outlined..22+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W16, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 438474 <.omp_outlined..22+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4384d8 <.omp_outlined..22+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X17, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X17, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438590 <.omp_outlined..22+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W16, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 43852c <.omp_outlined..22+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X2, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 438590 <.omp_outlined..22+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X3, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4385a4 <.omp_outlined..22+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4385f0 <.omp_outlined..22+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4388a4 <.omp_outlined..22+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4386cc <.omp_outlined..22+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4388ec <.omp_outlined..22+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 438a78 <.omp_outlined..22+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X1, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X3, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X5, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438a78 <.omp_outlined..22+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 438a94 <.omp_outlined..22+0x9b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X16, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 438b34 <.omp_outlined..22+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438b08 <.omp_outlined..22+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X18, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X15, X9, X26, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ X11, 438b34 <.omp_outlined..22+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X15, [X17, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X17, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438ba8 <.omp_outlined..22+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X12, X9, X26, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ X11, 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..22#0x4380e0
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 31% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 592 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	15.50	15.50	15.50	15.50	2.50	2.50	2.50	2.50	25.67	25.67	25.67	5.00	5.00
cycles	11.00	11.00	15.50	15.50	15.50	15.50	2.50	2.50	2.50	2.50	25.67	25.67	25.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

11.75-43.50

Cycles summary

Front-end	21.38
Overall L1	25.67-43.50

Vectorization ratios

all	8%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

14% of peak load performance is reached (13.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438a78

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438bd8 <.omp_outlined..22+0xaf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4384d8 <.omp_outlined..22+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W16, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 438474 <.omp_outlined..22+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4384d8 <.omp_outlined..22+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X17, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X17, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438590 <.omp_outlined..22+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W16, W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 43852c <.omp_outlined..22+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X2, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 438590 <.omp_outlined..22+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X3, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4385a4 <.omp_outlined..22+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X6, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4385f0 <.omp_outlined..22+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4388a4 <.omp_outlined..22+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4386cc <.omp_outlined..22+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4388ec <.omp_outlined..22+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 438a78 <.omp_outlined..22+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X1, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X3, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X5, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438a78 <.omp_outlined..22+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 438a94 <.omp_outlined..22+0x9b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X16, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X14, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 438b34 <.omp_outlined..22+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438b08 <.omp_outlined..22+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X18, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X15, X9, X26, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ X11, 438b34 <.omp_outlined..22+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X15, [X17, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X17, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438ba8 <.omp_outlined..22+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X9, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X12, X9, X26, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ X11, 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 438404 <.omp_outlined..22+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code