OV - exec - Loop 1199

	Loop Id: 1199	Module: exec	Source: par_multi_interp.c:1598-1660 [...]	Coverage: 0.07%

0x437b8c LDUR	X8, [X29, #464]

0x437b90 ADD	X0, X0, #1

0x437b94 CMP	X0, X8

0x437b98 B.GE	4380ac

0x437b9c LDUR	X8, [X29, #488]

0x437ba0 LDR	X26, [X8, X0,LSL #3]

0x437ba4 LDUR	X8, [X29, #480]

0x437ba8 ADD	X21, X26, #1

0x437bac LDR	X8, [X8, X26,LSL #3]

0x437bb0 LDR	X30, [X17, X26,LSL #3]

0x437bb4 LDR	X9, [X17, X21,LSL #3]

0x437bb8 ADD	X11, X9, X8

0x437bbc SUB	X11, X11, X30

0x437bc0 CMP	X8, X11

0x437bc4 B.GE	437c80

0x437bc8 LDR	X10, [SP, #24]

0x437bcc SUB	W16, W9, W30

0x437bd0 ANDS	X18, X16, #4160

0x437bd4 LDR	X11, [X10, #8]

0x437bd8 B.EQ	437c0c

0x437bdc ORR	X16, XZR, X8

  (1206) 0x437be0 LDR	X1, [X11, X16,LSL #3]

  (1206) 0x437be4 ADD	X16, X16, #1

  (1206) 0x437be8 SUBS	X18, X18, #1

  (1206) 0x437bec LDR	X1, [X12, X1,LSL #3]

  (1206) 0x437bf0 STR	X26, [X19, X1,LSL #3]

  (1206) 0x437bf4 B.NE	437be0

0x437bf8 ORN	X18, XZR, X30

0x437bfc ADD	X18, X9, X18

0x437c00 CMP	X18, #3

0x437c04 B.CS	437c20

0x437c08 B	437c7c

0x437c0c ORR	X16, XZR, X8

0x437c10 ORN	X18, XZR, X30

0x437c14 ADD	X18, X9, X18

0x437c18 CMP	X18, #3

0x437c1c B.CC	437c7c

0x437c20 ADD	X8, X9, X8

0x437c24 ADD	X9, X11, X16,LSL #3

0x437c28 ADD	X9, X9, #16

0x437c2c SUB	X8, X8, X16

0x437c30 SUB	X8, X8, X30

0x437c34 HINT	#0

0x437c38 HINT	#0

0x437c3c HINT	#0

  (1205) 0x437c40 LDUR	X11, [X9, #496]

  (1205) 0x437c44 SUBS	X8, X8, #4

  (1205) 0x437c48 LDR	X11, [X12, X11,LSL #3]

  (1205) 0x437c4c STR	X26, [X19, X11,LSL #3]

  (1205) 0x437c50 LDUR	X11, [X9, #504]

  (1205) 0x437c54 LDR	X11, [X12, X11,LSL #3]

  (1205) 0x437c58 STR	X26, [X19, X11,LSL #3]

  (1205) 0x437c5c LDR	X11, [X9]

  (1205) 0x437c60 LDR	X11, [X12, X11,LSL #3]

  (1205) 0x437c64 STR	X26, [X19, X11,LSL #3]

  (1205) 0x437c68 LDR	X11, [X9, #8]

  (1205) 0x437c6c ADD	X9, X9, #32

  (1205) 0x437c70 LDR	X11, [X12, X11,LSL #3]

  (1205) 0x437c74 STR	X26, [X19, X11,LSL #3]

  (1205) 0x437c78 B.NE	437c40

0x437c7c LDR	X30, [X17, X26,LSL #3]

0x437c80 LDR	X8, [X13, X26,LSL #3]

0x437c84 LDR	X16, [X13, X21,LSL #3]

0x437c88 MOVI	D2, #0

0x437c8c ADD	X8, X8, #1

0x437c90 CMP	X8, X16

0x437c94 B.GE	437d44

0x437c98 LDR	X10, [SP, #96]

0x437c9c LDUR	X9, [X29, #496]

0x437ca0 MOVI	D1, #0

0x437ca4 MOVI	D2, #0

0x437ca8 LDR	X11, [X10]

0x437cac LDR	X10, [SP, #104]

0x437cb0 LDR	X9, [X9]

0x437cb4 LDR	X18, [X10]

0x437cb8 LDR	X10, [SP, #40]

0x437cbc LDR	X1, [X10]

0x437cc0 LDR	X10, [SP, #32]

0x437cc4 LDR	X7, [X10]

0x437cc8 B	437cd8

  (1204) 0x437ccc ADD	X8, X8, #1

  (1204) 0x437cd0 CMP	X8, X16

  (1204) 0x437cd4 B.GE	437d4c

  (1204) 0x437cd8 LDR	X22, [X14, X8,LSL #3]

  (1204) 0x437cdc LDR	X6, [X15, X22,LSL #3]

  (1204) 0x437ce0 CMN	X6, #3

  (1204) 0x437ce4 B.EQ	437d0c

  (1204) 0x437ce8 LDR	X6, [X23]

  (1204) 0x437cec CMP	X6, #1

  (1204) 0x437cf0 B.EQ	437d04

  (1204) 0x437cf4 LDR	X6, [X9, X26,LSL #3]

  (1204) 0x437cf8 LDR	X24, [X9, X22,LSL #3]

  (1204) 0x437cfc CMP	X6, X24

  (1204) 0x437d00 B.NE	437d0c

  (1204) 0x437d04 LDR	D3, [X11, X8,LSL #3]

  (1204) 0x437d08 FADD	D1, D1, D3

  (1204) 0x437d0c CMN	X22, #1

  (1204) 0x437d10 B.EQ	437ccc

  (1204) 0x437d14 LDR	X6, [X19, X22,LSL #3]

  (1204) 0x437d18 CMP	X6, X26

  (1204) 0x437d1c B.NE	437ccc

  (1204) 0x437d20 LDR	D3, [X11, X8,LSL #3]

  (1204) 0x437d24 LDR	X16, [X1, X22,LSL #3]

  (1204) 0x437d28 STR	X16, [X7, X30,LSL #3]

  (1204) 0x437d2c LDR	X16, [X13, X21,LSL #3]

  (1204) 0x437d30 STR	D3, [X18, X30,LSL #3]

  (1204) 0x437d34 ADD	X30, X30, #1

  (1204) 0x437d38 LDR	D3, [X11, X8,LSL #3]

  (1204) 0x437d3c FADD	D2, D2, D3

  (1204) 0x437d40 B	437ccc

0x437d44 MOVI	D1, #0

0x437d48 B	437d50

0x437d4c LDP	X6, X17, [X29, #952]

0x437d50 LDUR	X8, [X29, #472]

0x437d54 LDR	X9, [X6, X21,LSL #3]

0x437d58 LDR	X27, [X6, X26,LSL #3]

0x437d5c LDR	X8, [X8, X26,LSL #3]

0x437d60 ADD	X11, X9, X8

0x437d64 SUB	X11, X11, X27

0x437d68 CMP	X8, X11

0x437d6c B.LT	437ee0

0x437d70 LDR	X28, [X3, X26,LSL #3]

0x437d74 LDR	X22, [X3, X21,LSL #3]

0x437d78 CMP	X28, X22

0x437d7c B.LT	437fb0

0x437d80 LDR	X8, [X13, X26,LSL #3]

0x437d84 LDUR	X9, [X29, #456]

0x437d88 LDR	D3, [X9, X8,LSL #3]

0x437d8c FMUL	D2, D2, D3

0x437d90 FCMP	D2, #0

0x437d94 B.EQ	437da0

0x437da0 LDR	X18, [X17, X26,LSL #3]

0x437da4 SUBS	X11, X30, X18

0x437da8 B.LE	437e34

0x437dac ORR	X8, XZR, X18

0x437db0 CMP	X11, X25

0x437db4 B.CC	437e0c

0x437db8 UDIV	X8, X11, X25

0x437dbc LDUR	X1, [X29, #432]

0x437dc0 UBFM	X10, X18, #61, #60

0x437dc4 ORR	X9, XZR, XZR

0x437dc8 DUP	Z1.D, Z0.D[0]

0x437dcc MADD	X16, X8, X25, XZR

0x437dd0 ADD	X8, X18, X16

0x437dd4 ADD	X18, X1, X10

0x437dd8 ADDVL	X10, X10, #1

0x437ddc SUB	X11, X11, X16

0x437de0 ADD	X1, X1, X10

  (1210) 0x437de4 LD1D	{Z2.D}, P0/Z, [X18, X9,LSL #3]

  (1210) 0x437de8 LD1D	{Z3.D}, P0/Z, [X1, X9,LSL #3]

  (1210) 0x437dec FMUL	Z2.D, Z1.D, Z2.D

  (1210) 0x437df0 FMUL	Z3.D, Z1.D, Z3.D

  (1210) 0x437df4 ST1D	{Z2.D}, P0, [X18, X9,LSL #3]

  (1210) 0x437df8 ST1D	{Z3.D}, P0, [X1, X9,LSL #3]

  (1210) 0x437dfc ADD	X9, X9, X25

  (1210) 0x437e00 CMP	X16, X9

  (1210) 0x437e04 B.NE	437de4

0x437e08 CBZ	X11, 437e34

0x437e0c LDUR	X10, [X29, #432]

0x437e10 SUB	X9, X30, X8

0x437e14 ADD	X8, X10, X8,LSL #3

0x437e18 HINT	#0

0x437e1c HINT	#0

  (1209) 0x437e20 LDR	D1, [X8]

  (1209) 0x437e24 SUBS	X9, X9, #1

  (1209) 0x437e28 FMUL	D1, D0, D1

  (1209) 0x437e2c STR	D1, [X8], #8

  (1209) 0x437e30 B.NE	437e20

0x437e34 LDR	X18, [X6, X26,LSL #3]

0x437e38 SUBS	X11, X27, X18

0x437e3c B.LE	437b8c

0x437e40 ORR	X8, XZR, X18

0x437e44 CMP	X11, X25

0x437e48 B.CC	437ea8

0x437e4c UDIV	X8, X11, X25

0x437e50 LDUR	X1, [X29, #424]

0x437e54 UBFM	X10, X18, #61, #60

0x437e58 ORR	X9, XZR, XZR

0x437e5c DUP	Z1.D, Z0.D[0]

0x437e60 MADD	X16, X8, X25, XZR

0x437e64 ADD	X8, X18, X16

0x437e68 ADD	X18, X1, X10

0x437e6c ADDVL	X10, X10, #1

0x437e70 SUB	X11, X11, X16

0x437e74 ADD	X1, X1, X10

0x437e78 HINT	#0

0x437e7c HINT	#0

  (1208) 0x437e80 LD1D	{Z2.D}, P0/Z, [X18, X9,LSL #3]

  (1208) 0x437e84 LD1D	{Z3.D}, P0/Z, [X1, X9,LSL #3]

  (1208) 0x437e88 FMUL	Z2.D, Z1.D, Z2.D

  (1208) 0x437e8c FMUL	Z3.D, Z1.D, Z3.D

  (1208) 0x437e90 ST1D	{Z2.D}, P0, [X18, X9,LSL #3]

  (1208) 0x437e94 ST1D	{Z3.D}, P0, [X1, X9,LSL #3]

  (1208) 0x437e98 ADD	X9, X9, X25

  (1208) 0x437e9c CMP	X16, X9

  (1208) 0x437ea0 B.NE	437e80

0x437ea4 CBZ	X11, 437b8c

0x437ea8 LDUR	X10, [X29, #424]

0x437eac SUB	X9, X27, X8

0x437eb0 ADD	X8, X10, X8,LSL #3

0x437eb4 HINT	#0

0x437eb8 HINT	#0

0x437ebc HINT	#0

  (1207) 0x437ec0 LDR	D1, [X8]

  (1207) 0x437ec4 SUBS	X9, X9, #1

  (1207) 0x437ec8 FMUL	D1, D0, D1

  (1207) 0x437ecc STR	D1, [X8], #8

  (1207) 0x437ed0 B.NE	437ec0

0x437ed4 B	437b8c

0x437ee0 LDR	X10, [SP, #16]

0x437ee4 SUB	W16, W9, W27

0x437ee8 ANDS	X18, X16, #4160

0x437eec LDR	X11, [X10, #8]

0x437ef0 B.EQ	437f2c

0x437ef4 ORR	X16, XZR, X8

0x437ef8 HINT	#0

0x437efc HINT	#0

  (1203) 0x437f00 LDR	X1, [X11, X16,LSL #3]

  (1203) 0x437f04 ADD	X16, X16, #1

  (1203) 0x437f08 SUBS	X18, X18, #1

  (1203) 0x437f0c LDR	X1, [X2, X1,LSL #3]

  (1203) 0x437f10 STR	X26, [X20, X1,LSL #3]

  (1203) 0x437f14 B.NE	437f00

0x437f18 ORN	X18, XZR, X27

0x437f1c ADD	X18, X9, X18

0x437f20 CMP	X18, #3

0x437f24 B.CS	437f40

0x437f28 B	437f9c

0x437f2c ORR	X16, XZR, X8

0x437f30 ORN	X18, XZR, X27

0x437f34 ADD	X18, X9, X18

0x437f38 CMP	X18, #3

0x437f3c B.CC	437f9c

0x437f40 ADD	X8, X9, X8

0x437f44 ADD	X9, X11, X16,LSL #3

0x437f48 ADD	X9, X9, #16

0x437f4c SUB	X8, X8, X16

0x437f50 SUB	X8, X8, X27

0x437f54 HINT	#0

0x437f58 HINT	#0

0x437f5c HINT	#0

  (1202) 0x437f60 LDUR	X11, [X9, #496]

  (1202) 0x437f64 SUBS	X8, X8, #4

  (1202) 0x437f68 LDR	X11, [X2, X11,LSL #3]

  (1202) 0x437f6c STR	X26, [X20, X11,LSL #3]

  (1202) 0x437f70 LDUR	X11, [X9, #504]

  (1202) 0x437f74 LDR	X11, [X2, X11,LSL #3]

  (1202) 0x437f78 STR	X26, [X20, X11,LSL #3]

  (1202) 0x437f7c LDR	X11, [X9]

  (1202) 0x437f80 LDR	X11, [X2, X11,LSL #3]

  (1202) 0x437f84 STR	X26, [X20, X11,LSL #3]

  (1202) 0x437f88 LDR	X11, [X9, #8]

  (1202) 0x437f8c ADD	X9, X9, #32

  (1202) 0x437f90 LDR	X11, [X2, X11,LSL #3]

  (1202) 0x437f94 STR	X26, [X20, X11,LSL #3]

  (1202) 0x437f98 B.NE	437f60

0x437f9c LDR	X27, [X6, X26,LSL #3]

0x437fa0 LDR	X28, [X3, X26,LSL #3]

0x437fa4 LDR	X22, [X3, X21,LSL #3]

0x437fa8 CMP	X28, X22

0x437fac B.GE	437d80

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1598 - 1660

--------------------------------------------------------------------------------

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

[...]

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	10.95 - 24.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03 - 2.19
Bottlenecks	P6, P8,
Function	.omp_outlined..20#0x437930
Source	par_multi_interp.c:1598-1598,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1612,par_multi_interp.c:1617-1618,par_multi_interp.c:1628-1628,par_multi_interp.c:1631-1633,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25 - 40.00
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	18.25 - 40.00
CQA cycles if fully vectorized	14.65 - 40.00
Front-end cycles	18.25
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	17.75
P2 cycles	17.75
P3 cycles	17.75
P4 cycles	17.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	14.33
P10 cycles	14.33
P11 cycles	14.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00 - 40.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	161.00
Nb uops	146.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.05 - 0.03
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.80 - 19.29
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.17
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.41
Vector-efficiency ratio all	27.60
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.56

Metric	Value
CQA speedup if no scalar integer	10.95 - 24.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03 - 2.19
Bottlenecks	P6, P8,
Function	.omp_outlined..20#0x437930
Source	par_multi_interp.c:1598-1598,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1612,par_multi_interp.c:1617-1618,par_multi_interp.c:1628-1628,par_multi_interp.c:1631-1633,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25 - 40.00
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	18.25 - 40.00
CQA cycles if fully vectorized	14.65 - 40.00
Front-end cycles	18.25
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	17.75
P2 cycles	17.75
P3 cycles	17.75
P4 cycles	17.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	14.33
P10 cycles	14.33
P11 cycles	14.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	10.00 - 40.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	161.00
Nb uops	146.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.05 - 0.03
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.80 - 19.29
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.17
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.41
Vector-efficiency ratio all	27.60
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.56

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20#0x437930
Source file and lines	par_multi_interp.c:1598-1660
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598,1605-1639,1655-1660.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598,1605-1607,1610-1612,1617-1618,1628,1631-1633,1638-1639,1655-1659.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 1.67 cycles (24.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 352 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	161
loop length	644
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	17.75	17.75	17.75	17.75	2.00	2.00	2.00	2.00	14.33	14.33	14.33	0.00	0.00
cycles	12.00	12.00	17.75	17.75	17.75	17.75	2.00	2.00	2.00	2.00	14.33	14.33	14.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	18.25
Overall L1	18.25-40.00

Vectorization ratios

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4380ac <.omp_outlined..20+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X17, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437c80 <.omp_outlined..20+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W9, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X18, X16, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.EQ 437c0c <.omp_outlined..20+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 437c20 <.omp_outlined..20+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437c7c <.omp_outlined..20+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437c7c <.omp_outlined..20+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X30, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437d44 <.omp_outlined..20+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 437cd8 <.omp_outlined..20+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 437d50 <.omp_outlined..20+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X17, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437ee0 <.omp_outlined..20+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X3, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437fb0 <.omp_outlined..20+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 437da0 <.omp_outlined..20+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437e34 <.omp_outlined..20+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437e0c <.omp_outlined..20+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDUR X1, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X16, X8, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X10, X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X11, 437e34 <.omp_outlined..20+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X18, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X27, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437ea8 <.omp_outlined..20+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X16, X8, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X10, X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CBZ X11, 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X18, X16, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.EQ 437f2c <.omp_outlined..20+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 437f40 <.omp_outlined..20+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437f9c <.omp_outlined..20+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437f9c <.omp_outlined..20+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X27, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X3, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437d80 <.omp_outlined..20+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20#0x437930
Source file and lines	par_multi_interp.c:1598-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 352 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	161
loop length	644
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	17.75	17.75	17.75	17.75	2.00	2.00	2.00	2.00	14.33	14.33	14.33	0.00	0.00
cycles	12.00	12.00	17.75	17.75	17.75	17.75	2.00	2.00	2.00	2.00	14.33	14.33	14.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	18.25
Overall L1	18.25-40.00

Vectorization ratios

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4380ac <.omp_outlined..20+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X17, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437c80 <.omp_outlined..20+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W9, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X18, X16, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.EQ 437c0c <.omp_outlined..20+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 437c20 <.omp_outlined..20+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437c7c <.omp_outlined..20+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437c7c <.omp_outlined..20+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X30, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437d44 <.omp_outlined..20+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 437cd8 <.omp_outlined..20+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 437d50 <.omp_outlined..20+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X17, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437ee0 <.omp_outlined..20+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X3, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437fb0 <.omp_outlined..20+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 437da0 <.omp_outlined..20+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437e34 <.omp_outlined..20+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437e0c <.omp_outlined..20+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDUR X1, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X16, X8, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X10, X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X11, 437e34 <.omp_outlined..20+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X18, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X11, X27, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437ea8 <.omp_outlined..20+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X8, X11, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MADD X16, X8, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X10, X10, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CBZ X11, 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 437b8c <.omp_outlined..20+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X18, X16, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.EQ 437f2c <.omp_outlined..20+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 437f40 <.omp_outlined..20+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437f9c <.omp_outlined..20+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X16, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 437f9c <.omp_outlined..20+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X27, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X3, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X28, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437d80 <.omp_outlined..20+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code