OV - exec - Loop 1181

0x46a940 LDR	X8, [X11, X3,LSL #3]

0x46a944 ADD	X5, X5, #1

0x46a948 CMP	X5, X8

0x46a94c B.GE	46aa68

0x46a950 LDR	X27, [X12, X5,LSL #3]

0x46a954 LDR	X8, [X13, X27,LSL #3]

0x46a958 CMP	X8, #1

0x46a95c B.LT	46a984

0x46a960 LDR	X8, [X6, X27,LSL #3]

0x46a964 LDR	X9, [X24, X8,LSL #3]

0x46a968 CMP	X9, X1

0x46a96c B.GE	46a984

0x46a970 LDUR	X9, [X29, #480]

0x46a974 STR	X9, [X24, X8,LSL #3]

0x46a978 LDUR	X8, [X29, #480]

0x46a97c ADD	X8, X8, #1

0x46a980 STUR	X8, [X29, #480]

0x46a984 ADD	X28, X27, #1

0x46a988 LDR	X10, [X11, X27,LSL #3]

0x46a98c LDR	X8, [X11, X28,LSL #3]

0x46a990 CMP	X10, X8

0x46a994 B.GE	46aa00

0x46a998 LDUR	X9, [X29, #456]

0x46a99c LDR	X9, [X9]

0x46a9a0 B	46a9b0

  (1183) 0x46a9a4 ADD	X10, X10, #1

  (1183) 0x46a9a8 CMP	X10, X8

  (1183) 0x46a9ac B.GE	46aa00

  (1183) 0x46a9b0 LDR	X4, [X12, X10,LSL #3]

  (1183) 0x46a9b4 LDR	X19, [X13, X4,LSL #3]

  (1183) 0x46a9b8 CMP	X19, #1

  (1183) 0x46a9bc B.LT	46a9a4

  (1183) 0x46a9c0 LDR	X4, [X9, X4,LSL #3]

  (1183) 0x46a9c4 CMP	X4, X18

  (1183) 0x46a9c8 B.EQ	46a9a4

  (1183) 0x46a9cc LDR	X19, [X24, X4,LSL #3]

  (1183) 0x46a9d0 CMP	X19, X1

  (1183) 0x46a9d4 B.GE	46a9a4

  (1183) 0x46a9d8 LDUR	X8, [X29, #480]

  (1183) 0x46a9dc STR	X8, [X24, X4,LSL #3]

  (1183) 0x46a9e0 LDUR	X8, [X29, #480]

  (1183) 0x46a9e4 ADD	X8, X8, #1

  (1183) 0x46a9e8 STUR	X8, [X29, #480]

  (1183) 0x46a9ec LDR	X8, [X11, X28,LSL #3]

  (1183) 0x46a9f0 B	46a9a4

0x46aa00 LDR	X10, [X14, X27,LSL #3]

0x46aa04 LDR	X9, [X14, X28,LSL #3]

0x46aa08 CMP	X10, X9

0x46aa0c B.GE	46a940

0x46aa10 LDUR	X8, [X29, #464]

0x46aa14 LDR	X8, [X8]

0x46aa18 B	46aa2c

  (1182) 0x46aa20 ADD	X10, X10, #1

  (1182) 0x46aa24 CMP	X10, X9

  (1182) 0x46aa28 B.GE	46a940

  (1182) 0x46aa2c LDR	X4, [X7, X10,LSL #3]

  (1182) 0x46aa30 LDR	X19, [X30, X4,LSL #3]

  (1182) 0x46aa34 CMP	X19, #1

  (1182) 0x46aa38 B.LT	46aa20

  (1182) 0x46aa3c LDR	X4, [X8, X4,LSL #3]

  (1182) 0x46aa40 LDR	X19, [X25, X4,LSL #3]

  (1182) 0x46aa44 CMP	X19, X2

  (1182) 0x46aa48 B.GE	46aa20

  (1182) 0x46aa4c LDUR	X9, [X29, #472]

  (1182) 0x46aa50 STR	X9, [X25, X4,LSL #3]

  (1182) 0x46aa54 LDUR	X9, [X29, #472]

  (1182) 0x46aa58 ADD	X9, X9, #1

  (1182) 0x46aa5c STUR	X9, [X29, #472]

  (1182) 0x46aa60 LDR	X9, [X14, X28,LSL #3]

  (1182) 0x46aa64 B	46aa20

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1731 - 1765

--------------------------------------------------------------------------------

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..20#0x46a650
Source	par_strength.c:1731-1740,par_strength.c:1743-1743,par_strength.c:1756-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.67
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	1.42
Front-end cycles	4.00
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.67
P10 cycles	5.67
P11 cycles	5.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..20#0x46a650
Source	par_strength.c:1731-1740,par_strength.c:1743-1743,par_strength.c:1756-1756
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.67
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	1.42
Front-end cycles	4.00
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.67
P10 cycles	5.67
P11 cycles	5.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20#0x46a650
Source file and lines	par_strength.c:1731-1765
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1765.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1740,1743,1756.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 1.42 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	5.67	5.67	5.67	1.00	1.00
cycles	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	5.67	5.67	5.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

22% of peak load performance is reached (21.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X8, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa68 <.omp_outlined..20+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 46a984 <.omp_outlined..20+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a984 <.omp_outlined..20+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa00 <.omp_outlined..20+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a9b0 <.omp_outlined..20+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X14, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a940 <.omp_outlined..20+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46aa2c <.omp_outlined..20+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20#0x46a650
Source file and lines	par_strength.c:1731-1765
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1765.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1731-1740,1743,1756.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 1.42 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	5.67	5.67	5.67	1.00	1.00
cycles	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	5.67	5.67	5.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.00
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

22% of peak load performance is reached (21.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X8, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa68 <.omp_outlined..20+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 46a984 <.omp_outlined..20+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X6, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a984 <.omp_outlined..20+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X24, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X11, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa00 <.omp_outlined..20+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a9b0 <.omp_outlined..20+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X14, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a940 <.omp_outlined..20+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46aa2c <.omp_outlined..20+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code