OV - exec - Loop 1179

0x46a8c4 ADD	X18, X18, #1

0x46a8c8 CMP	X18, X30

0x46a8cc B.EQ	46b130

0x46a8d0 LDUR	X8, [X29, #448]

0x46a8d4 LDP	X2, X1, [X29, #984]

0x46a8d8 LDR	X10, [X8, X18,LSL #3]

0x46a8dc LDUR	X8, [X29, #440]

0x46a8e0 STR	X1, [X8, X18,LSL #3]

0x46a8e4 LDUR	X8, [X29, #432]

0x46a8e8 LDR	X8, [X8]

0x46a8ec CBZ	X8, 46a8fc

0x46a8f0 LDUR	X8, [X29, #472]

0x46a8f4 LDR	X9, [SP, #144]

0x46a8f8 STR	X8, [X9, X18,LSL #3]

0x46a8fc ADD	X3, X10, #1

0x46a900 LDR	X5, [X11, X10,LSL #3]

0x46a904 LDR	X8, [X11, X3,LSL #3]

0x46a908 CMP	X5, X8

0x46a90c B.GE	46aa70

0x46a910 LDUR	X8, [X29, #456]

0x46a914 STUR	X10, [X29, #376]

0x46a918 LDR	X6, [X8]

0x46a91c LDUR	X8, [X29, #400]

0x46a920 LDR	X7, [X8]

0x46a924 LDUR	X8, [X29, #408]

0x46a928 LDR	X30, [X8]

0x46a92c B	46a950

  (1181) 0x46a940 LDR	X8, [X11, X3,LSL #3]

  (1181) 0x46a944 ADD	X5, X5, #1

  (1181) 0x46a948 CMP	X5, X8

  (1181) 0x46a94c B.GE	46aa68

  (1181) 0x46a950 LDR	X27, [X12, X5,LSL #3]

  (1181) 0x46a954 LDR	X8, [X13, X27,LSL #3]

  (1181) 0x46a958 CMP	X8, #1

  (1181) 0x46a95c B.LT	46a984

  (1181) 0x46a960 LDR	X8, [X6, X27,LSL #3]

  (1181) 0x46a964 LDR	X9, [X24, X8,LSL #3]

  (1181) 0x46a968 CMP	X9, X1

  (1181) 0x46a96c B.GE	46a984

  (1181) 0x46a970 LDUR	X9, [X29, #480]

  (1181) 0x46a974 STR	X9, [X24, X8,LSL #3]

  (1181) 0x46a978 LDUR	X8, [X29, #480]

  (1181) 0x46a97c ADD	X8, X8, #1

  (1181) 0x46a980 STUR	X8, [X29, #480]

  (1181) 0x46a984 ADD	X28, X27, #1

  (1181) 0x46a988 LDR	X10, [X11, X27,LSL #3]

  (1181) 0x46a98c LDR	X8, [X11, X28,LSL #3]

  (1181) 0x46a990 CMP	X10, X8

  (1181) 0x46a994 B.GE	46aa00

  (1181) 0x46a998 LDUR	X9, [X29, #456]

  (1181) 0x46a99c LDR	X9, [X9]

  (1181) 0x46a9a0 B	46a9b0

    (1183) 0x46a9a4 ADD	X10, X10, #1

    (1183) 0x46a9a8 CMP	X10, X8

    (1183) 0x46a9ac B.GE	46aa00

    (1183) 0x46a9b0 LDR	X4, [X12, X10,LSL #3]

    (1183) 0x46a9b4 LDR	X19, [X13, X4,LSL #3]

    (1183) 0x46a9b8 CMP	X19, #1

    (1183) 0x46a9bc B.LT	46a9a4

    (1183) 0x46a9c0 LDR	X4, [X9, X4,LSL #3]

    (1183) 0x46a9c4 CMP	X4, X18

    (1183) 0x46a9c8 B.EQ	46a9a4

    (1183) 0x46a9cc LDR	X19, [X24, X4,LSL #3]

    (1183) 0x46a9d0 CMP	X19, X1

    (1183) 0x46a9d4 B.GE	46a9a4

    (1183) 0x46a9d8 LDUR	X8, [X29, #480]

    (1183) 0x46a9dc STR	X8, [X24, X4,LSL #3]

    (1183) 0x46a9e0 LDUR	X8, [X29, #480]

    (1183) 0x46a9e4 ADD	X8, X8, #1

    (1183) 0x46a9e8 STUR	X8, [X29, #480]

    (1183) 0x46a9ec LDR	X8, [X11, X28,LSL #3]

    (1183) 0x46a9f0 B	46a9a4

  (1181) 0x46aa00 LDR	X10, [X14, X27,LSL #3]

  (1181) 0x46aa04 LDR	X9, [X14, X28,LSL #3]

  (1181) 0x46aa08 CMP	X10, X9

  (1181) 0x46aa0c B.GE	46a940

  (1181) 0x46aa10 LDUR	X8, [X29, #464]

  (1181) 0x46aa14 LDR	X8, [X8]

  (1181) 0x46aa18 B	46aa2c

    (1182) 0x46aa20 ADD	X10, X10, #1

    (1182) 0x46aa24 CMP	X10, X9

    (1182) 0x46aa28 B.GE	46a940

    (1182) 0x46aa2c LDR	X4, [X7, X10,LSL #3]

    (1182) 0x46aa30 LDR	X19, [X30, X4,LSL #3]

    (1182) 0x46aa34 CMP	X19, #1

    (1182) 0x46aa38 B.LT	46aa20

    (1182) 0x46aa3c LDR	X4, [X8, X4,LSL #3]

    (1182) 0x46aa40 LDR	X19, [X25, X4,LSL #3]

    (1182) 0x46aa44 CMP	X19, X2

    (1182) 0x46aa48 B.GE	46aa20

    (1182) 0x46aa4c LDUR	X9, [X29, #472]

    (1182) 0x46aa50 STR	X9, [X25, X4,LSL #3]

    (1182) 0x46aa54 LDUR	X9, [X29, #472]

    (1182) 0x46aa58 ADD	X9, X9, #1

    (1182) 0x46aa5c STUR	X9, [X29, #472]

    (1182) 0x46aa60 LDR	X9, [X14, X28,LSL #3]

    (1182) 0x46aa64 B	46aa20

0x46aa68 LDUR	X30, [X29, #416]

0x46aa6c LDUR	X10, [X29, #376]

0x46aa70 LDR	X4, [X14, X10,LSL #3]

0x46aa74 LDR	X8, [X14, X3,LSL #3]

0x46aa78 CMP	X4, X8

0x46aa7c B.GE	46a8c4

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1714 - 1770

--------------------------------------------------------------------------------

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..20#0x46a650
Source	par_strength.c:1714-1714,par_strength.c:1720-1722,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.83
CQA cycles if no scalar integer	7.83
CQA cycles if FP arith vectorized	7.83
CQA cycles if fully vectorized	1.96
Front-end cycles	4.13
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.83
P10 cycles	7.50
P11 cycles	7.67
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.51
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..20#0x46a650
Source	par_strength.c:1714-1714,par_strength.c:1720-1722,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.83
CQA cycles if no scalar integer	7.83
CQA cycles if FP arith vectorized	7.83
CQA cycles if fully vectorized	1.96
Front-end cycles	4.13
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.83
P10 cycles	7.50
P11 cycles	7.67
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.51
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20#0x46a650
Source file and lines	par_strength.c:1714-1770
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1770.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1722,1725-1728,1731,1756,1770.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.83 to 1.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	7.83	7.50	7.67	1.50	1.50
cycles	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	7.83	7.50	7.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.13
Overall L1	7.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.83 cycles. At this rate:

22% of peak load performance is reached (21.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a8c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X1, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46a8fc <.omp_outlined..20+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa70 <.omp_outlined..20+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a950 <.omp_outlined..20+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #376]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a8c4 <.omp_outlined..20+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20#0x46a650
Source file and lines	par_strength.c:1714-1770
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1770.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1722,1725-1728,1731,1756,1770.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.83 to 1.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 168 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	7.83	7.50	7.67	1.50	1.50
cycles	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	7.83	7.50	7.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.13
Overall L1	7.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.83 cycles. At this rate:

22% of peak load performance is reached (21.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46a8c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X1, [X29, #984]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [X8, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46a8fc <.omp_outlined..20+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46aa70 <.omp_outlined..20+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #376]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a950 <.omp_outlined..20+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #376]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 46a8c4 <.omp_outlined..20+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code