OV - exec - Loop 1066

0x4a6340 LDP	X1, X2, [X0, #1008]    [1]

0x4a6344 LDP	D2, D3, [X18, #1008]    [4]

0x4a6348 SUBS	X17, X17, #4

0x4a634c LDR	D1, [X10, X1,LSL #3]    [2]

0x4a6350 FMADD	D0, D2, D1, D0

0x4a6354 LDR	D1, [X10, X2,LSL #3]    [2]

0x4a6358 FMADD	D0, D3, D1, D0

0x4a635c LDP	X1, X2, [X0], #32    [1]

0x4a6360 LDR	D2, [X10, X1,LSL #3]    [3]

0x4a6364 LDP	D1, D3, [X18], #32    [4]

0x4a6368 FMADD	D0, D1, D2, D0

0x4a636c LDR	D1, [X10, X2,LSL #3]    [3]

0x4a6370 FMADD	D0, D3, D1, D0

0x4a6374 B.NE	4a6340

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 259 - 261

--------------------------------------------------------------------------------

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	.omp_outlined..18#0x4a6160
Source	csr_matvec.c:259-261
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.29
Front-end cycles	1.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	33.33
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.00
Bottlenecks
Function	.omp_outlined..18#0x4a6160
Source	csr_matvec.c:259-261
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.29
Front-end cycles	1.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	33.33
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..18#0x4a6160
Source file and lines	csr_matvec.c:259-261
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:259-261.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.29 cycles (3.50x speedup).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	1.00	1.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	1.00	1.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.75
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a6340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDP X1, X2, [X0, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D2, D3, [X18, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUBS X17, X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP X1, X2, [X0], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR D2, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D1, D3, [X18], #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B.NE 4a6340 <.omp_outlined..18+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..18#0x4a6160
Source file and lines	csr_matvec.c:259-261
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:259-261.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.29 cycles (3.50x speedup).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	1.00	1.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	1.00	1.00	1.00	1.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	1.75
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a6340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDP X1, X2, [X0, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDP D2, D3, [X18, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUBS X17, X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR D1, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP X1, X2, [X0], #32	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR D2, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D1, D3, [X18], #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D1, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B.NE 4a6340 <.omp_outlined..18+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code