OV - exec - Loop 1040

0x4a62c4 STR	D0, [X13, X20,LSL #3]

0x4a62c8 ORR	X20, XZR, X17

0x4a62cc CMP	X17, X19

0x4a62d0 B.EQ	4a6c5c

0x4a62d4 LDR	D0, [X8, X20,LSL #3]

0x4a62d8 ADD	X17, X20, #1

0x4a62dc ORR	X18, XZR, X16

0x4a62e0 LDR	X16, [X9, X17,LSL #3]

0x4a62e4 CMP	X16, X18

0x4a62e8 B.LE	4a62c4

0x4a62ec SUB	W0, W16, W18

0x4a62f0 ANDS	X1, X0, #4160

0x4a62f4 B.EQ	4a6330

0x4a62f8 ORR	X0, XZR, X18

0x4a62fc HINT	#0

  (1042) 0x4a6300 LDR	X2, [X12, X0,LSL #3]

  (1042) 0x4a6304 LDR	D1, [X10, X0,LSL #3]

  (1042) 0x4a6308 ADD	X0, X0, #1

  (1042) 0x4a630c SUBS	X1, X1, #1

  (1042) 0x4a6310 LDR	D2, [X11, X2,LSL #3]

  (1042) 0x4a6314 FMADD	D0, D1, D2, D0

  (1042) 0x4a6318 B.NE	4a6300

0x4a631c ORN	X18, XZR, X18

0x4a6320 ADD	X18, X16, X18

0x4a6324 CMP	X18, #3

0x4a6328 B.CC	4a62c4

0x4a632c B	4a6344

0x4a6330 ORR	X0, XZR, X18

0x4a6334 ORN	X18, XZR, X18

0x4a6338 ADD	X18, X16, X18

0x4a633c CMP	X18, #3

0x4a6340 B.CC	4a62c4

0x4a6344 UBFM	X1, X0, #61, #60

0x4a6348 SUB	X18, X16, X0

0x4a634c ADD	X0, X14, X1

0x4a6350 ADD	X1, X15, X1

0x4a6354 HINT	#0

0x4a6358 HINT	#0

0x4a635c HINT	#0

  (1041) 0x4a6360 LDP	X2, X3, [X1, #1008]

  (1041) 0x4a6364 LDP	D2, D3, [X0, #1008]

  (1041) 0x4a6368 SUBS	X18, X18, #4

  (1041) 0x4a636c LDR	D1, [X11, X2,LSL #3]

  (1041) 0x4a6370 FMADD	D0, D2, D1, D0

  (1041) 0x4a6374 LDR	D1, [X11, X3,LSL #3]

  (1041) 0x4a6378 FMADD	D0, D3, D1, D0

  (1041) 0x4a637c LDP	X2, X3, [X1], #32

  (1041) 0x4a6380 LDR	D2, [X11, X2,LSL #3]

  (1041) 0x4a6384 LDP	D1, D3, [X0], #32

  (1041) 0x4a6388 FMADD	D0, D1, D2, D0

  (1041) 0x4a638c LDR	D1, [X11, X3,LSL #3]

  (1041) 0x4a6390 FMADD	D0, D3, D1, D0

  (1041) 0x4a6394 B.NE	4a6360

0x4a6398 B	4a62c4

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 334 - 341

--------------------------------------------------------------------------------

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	5.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..18#0x4a5dc0
Source	csr_matvec.c:334-337,csr_matvec.c:341-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.00
Front-end cycles	3.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.05
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	5.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P2, P3, P4, P5,
Function	.omp_outlined..18#0x4a5dc0
Source	csr_matvec.c:334-337,csr_matvec.c:341-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	1.00
Front-end cycles	3.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.05
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..18#0x4a5dc0
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-337,341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.75 to 0.83 cycles (5.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	0.50	0.50	0.00	0.00	1.17	0.83	1.00	0.00	0.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	0.50	0.50	0.00	0.00	1.17	0.83	1.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a62d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR D0, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X20, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a6c5c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X17, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W0, W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a6330 <.omp_outlined..18+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a6344 <.omp_outlined..18+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..18#0x4a5dc0
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-337,341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.75 to 0.83 cycles (5.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 1.00 cycles (4.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	4.75	4.75	0.50	0.50	0.00	0.00	1.17	0.83	1.00	0.00	0.00
cycles	3.50	3.50	4.75	4.75	4.75	4.75	0.50	0.50	0.00	0.00	1.17	0.83	1.00	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	4.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4a62d4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR D0, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X20, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a6c5c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X17, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W0, W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4a6330 <.omp_outlined..18+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a6344 <.omp_outlined..18+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X18, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X15, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 4a62c4 <.omp_outlined..18+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code