OV - exec - Function hypre_IJMatrixSetDiagOffdSizesParCSR

	Function: hypre_IJMatrixSetDiagOffdSizesParCSR	Module: exec	Source: IJMatrix_parcsr.c:178-219 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 178 - 219

--------------------------------------------------------------------------------

178: {

179:    HYPRE_Int local_num_rows;

180:    HYPRE_Int i;

181:    hypre_ParCSRMatrix *par_matrix = (hypre_ParCSRMatrix *)hypre_IJMatrixObject(matrix);

182:    hypre_AuxParCSRMatrix *aux_matrix = (hypre_AuxParCSRMatrix *)hypre_IJMatrixTranslator(matrix);

[...]

188:    if (!par_matrix)

189:    {

190:       hypre_IJMatrixCreateParCSR(matrix);

191:       par_matrix = (hypre_ParCSRMatrix *)hypre_IJMatrixObject(matrix);

192:    }

193:

194:    diag =  hypre_ParCSRMatrixDiag(par_matrix);

195:    diag_i =  hypre_CSRMatrixI(diag);

196:    local_num_rows = hypre_CSRMatrixNumRows(diag);

197:    if (!diag_i)

198:       diag_i = hypre_CTAlloc(HYPRE_Int, local_num_rows+1);

199:    for (i = 0; i < local_num_rows; i++)

200:       diag_i[i+1] = diag_i[i] + diag_sizes[i];

201:    hypre_CSRMatrixI(diag) = diag_i;

202:    hypre_CSRMatrixNumNonzeros(diag) = diag_i[local_num_rows];

203:    offd =  hypre_ParCSRMatrixOffd(par_matrix);

204:    offd_i =  hypre_CSRMatrixI(offd);

205:    if (!offd_i)

206:       offd_i = hypre_CTAlloc(HYPRE_Int, local_num_rows+1);

207:    for (i = 0; i < local_num_rows; i++)

208:       offd_i[i+1] = offd_i[i] + offdiag_sizes[i];

209:    hypre_CSRMatrixI(offd) = offd_i;

210:    hypre_CSRMatrixNumNonzeros(offd) = offd_i[local_num_rows];

211:    if (!aux_matrix)

212:    {

213:       hypre_AuxParCSRMatrixCreate(&aux_matrix, local_num_rows,

214:                                   hypre_CSRMatrixNumCols(diag), NULL);

215:       hypre_IJMatrixTranslator(matrix) = aux_matrix;

216:    }

217:    hypre_AuxParCSRMatrixNeedAux(aux_matrix) = 0;

218:

219:    return hypre_error_flag;

0x497fb0 SUB	SP, SP, #80

0x497fb4 STP	X29, X30, [SP, #16]

0x497fb8 STP	X24, X23, [SP, #32]

0x497fbc STP	X22, X21, [SP, #48]

0x497fc0 STP	X20, X19, [SP, #64]

0x497fc4 ADD	X29, SP, #16

0x497fc8 LDP	X24, X8, [X0, #32]

0x497fcc ORR	X20, XZR, X2

0x497fd0 ORR	X22, XZR, X1

0x497fd4 STR	X8, [SP, #8]

0x497fd8 ORR	X19, XZR, X0

0x497fdc CBZ	X24, 497ffc

0x497fe0 LDR	X23, [X24, #56]

0x497fe4 LDR	X0, [X23]

0x497fe8 LDR	X21, [X23, #16]

0x497fec CBZ	X0, 498018

0x497ff0 CMP	X21, #1

0x497ff4 B.GE	49802c

0x497ff8 B	4980a0

0x497ffc ORR	X0, XZR, X19

0x498000 BL	497ce0

0x498004 LDR	X24, [X19, #32]

0x498008 LDR	X23, [X24, #56]

0x49800c LDR	X0, [X23]

0x498010 LDR	X21, [X23, #16]

0x498014 CBNZ	X0, 497ff0

0x498018 ADD	X0, X21, #1

0x49801c MOVZ	W1, #8

0x498020 BL	4ae430

0x498024 CMP	X21, #1

0x498028 B.LT	4980a0

0x49802c LDR	X8, [X0]

0x498030 CMP	X21, #1

0x498034 B.NE	498044

0x498038 ORR	X9, XZR, XZR

0x49803c TBNZ	W21, #0, 49808c

0x498040 B	4980a0

0x498044 AND	X10, X21, #8127

0x498048 ORR	X9, XZR, XZR

0x49804c ADD	X11, X22, #8

0x498050 ADD	X12, X0, #16

0x498054 SUB	X10, XZR, X10

0x498058 HINT	#0

0x49805c HINT	#0

(3506) 0x498060 LDUR	X13, [X11, #504]

(3506) 0x498064 SUB	X9, X9, #2

(3506) 0x498068 CMP	X10, X9

(3506) 0x49806c ADD	X8, X13, X8

(3506) 0x498070 STUR	X8, [X12, #504]

(3506) 0x498074 LDR	X13, [X11], #16

(3506) 0x498078 ADD	X8, X13, X8

(3506) 0x49807c STR	X8, [X12], #16

(3506) 0x498080 B.NE	498060

0x498084 SUB	X9, XZR, X9

0x498088 TBZ	W21, #0, 4980a0

0x49808c UBFM	X9, X9, #61, #60

0x498090 LDR	X10, [X22, X9]

0x498094 ADD	X9, X9, X0

0x498098 ADD	X8, X10, X8

0x49809c STR	X8, [X9, #8]

0x4980a0 LDR	X22, [X24, #64]

0x4980a4 STR	X0, [X23]

0x4980a8 LDR	X8, [X0, X21,LSL #3]

0x4980ac LDR	X0, [X22]

0x4980b0 STR	X8, [X23, #32]

0x4980b4 CBNZ	X0, 4980c4

0x4980b8 ADD	X0, X21, #1

0x4980bc MOVZ	W1, #8

0x4980c0 BL	4ae430

0x4980c4 CMP	X21, #1

0x4980c8 B.LT	498140

0x4980cc LDR	X8, [X0]

0x4980d0 CMP	X21, #1

0x4980d4 B.NE	4980e4

0x4980d8 ORR	X9, XZR, XZR

0x4980dc TBNZ	W21, #0, 49812c

0x4980e0 B	498140

0x4980e4 AND	X10, X21, #8127

0x4980e8 ORR	X9, XZR, XZR

0x4980ec ADD	X11, X20, #8

0x4980f0 ADD	X12, X0, #16

0x4980f4 SUB	X10, XZR, X10

0x4980f8 HINT	#0

0x4980fc HINT	#0

(3507) 0x498100 LDUR	X13, [X11, #504]

(3507) 0x498104 SUB	X9, X9, #2

(3507) 0x498108 CMP	X10, X9

(3507) 0x49810c ADD	X8, X13, X8

(3507) 0x498110 STUR	X8, [X12, #504]

(3507) 0x498114 LDR	X13, [X11], #16

(3507) 0x498118 ADD	X8, X13, X8

(3507) 0x49811c STR	X8, [X12], #16

(3507) 0x498120 B.NE	498100

0x498124 SUB	X9, XZR, X9

0x498128 TBZ	W21, #0, 498140

0x49812c UBFM	X9, X9, #61, #60

0x498130 LDR	X10, [X20, X9]

0x498134 ADD	X9, X9, X0

0x498138 ADD	X8, X10, X8

0x49813c STR	X8, [X9, #8]

0x498140 LDR	X8, [X0, X21,LSL #3]

0x498144 STR	X0, [X22]

0x498148 STR	X8, [X22, #32]

0x49814c LDR	X8, [SP, #8]

0x498150 CBNZ	X8, 498170

0x498154 LDR	X2, [X23, #24]

0x498158 ORR	X1, XZR, X21

0x49815c ORR	X3, XZR, XZR

0x498160 ADD	X0, SP, #8

0x498164 BL	4a1300

0x498168 LDR	X8, [SP, #8]

0x49816c STR	X8, [X19, #40]

0x498170 STR	XZR, [X8, #16]

0x498174 ADRP	X8,

0x498178 LDR	X8, [X8, #4040]

0x49817c LDR	X0, [X8]

0x498180 LDP	X20, X19, [SP, #64]

0x498184 LDP	X22, X21, [SP, #48]

0x498188 LDP	X24, X23, [SP, #32]

0x49818c LDP	X29, X30, [SP, #16]

0x498190 ADD	SP, SP, #80

0x498194 RET

0x498198 HINT	#0

0x49819c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:178-219
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:178-182,188-219.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.83 to 1.87 cycles (6.84x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.83 to 2.00 cycles (6.42x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	106
loop length	424
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	12.83	12.50	12.67	6.50	6.50
cycles	11.00	11.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	12.83	12.50	12.67	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Overall L1	12.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

19% of peak load performance is reached (18.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 497fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X8, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X24, 497ffc <hypre_IJMatrixSetDiagOffdSizesParCSR+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X24, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 498018 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49802c <hypre_IJMatrixSetDiagOffdSizesParCSR+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 497ce0 <hypre_IJMatrixCreateParCSR>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X24, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 497ff0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 498044 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W21, #0, 49808c <hypre_IJMatrixSetDiagOffdSizesParCSR+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X10, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
SUB X9, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W21, #0, 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X22, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X24, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 4980c4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4980e4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W21, #0, 49812c <hypre_IJMatrixSetDiagOffdSizesParCSR+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X10, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
SUB X9, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W21, #0, 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 498170 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a1300 <hypre_AuxParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X8, <4ef174>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	IJMatrix_parcsr.c:178-219
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:178-182,188-219.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.83 to 2.00 cycles (6.42x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 240 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	106
loop length	424
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.00	11.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	12.83	12.50	12.67	6.50	6.50
cycles	11.00	11.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	12.83	12.50	12.67	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Overall L1	12.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

19% of peak load performance is reached (18.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 497fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X8, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X20, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X24, 497ffc <hypre_IJMatrixSetDiagOffdSizesParCSR+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X24, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 498018 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49802c <hypre_IJMatrixSetDiagOffdSizesParCSR+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 497ce0 <hypre_IJMatrixCreateParCSR>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X24, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X24, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 497ff0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 498044 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W21, #0, 49808c <hypre_IJMatrixSetDiagOffdSizesParCSR+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X10, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
SUB X9, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W21, #0, 4980a0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X22, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X24, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 4980c4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4980e4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W21, #0, 49812c <hypre_IJMatrixSetDiagOffdSizesParCSR+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND X10, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
SUB X9, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W21, #0, 498140 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 498170 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a1300 <hypre_AuxParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X8, <4ef174>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4040]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetDiagOffdSizesParCSR–	0.02	0.01
○Loop 3506 - IJMatrix_parcsr.c:199-200 - exec	0.01	0.17
○Loop 3507 - IJMatrix_parcsr.c:207-208 - exec	0.01	0.15

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code