| Function: hypre_BoomerAMGBuildMultipass | Module: exec | Source: par_multi_interp.c:41-2060 [...] | Coverage: 0.27% |
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| Function: hypre_BoomerAMGBuildMultipass | Module: exec | Source: par_multi_interp.c:41-2060 [...] | Coverage: 0.27% |
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/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 41 - 2060 |
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41: { |
42: #ifdef HYPRE_PROFILE |
43: hypre_profile_times[HYPRE_TIMER_ID_MULTIPASS_INTERP] -= hypre_MPI_Wtime(); |
44: #endif |
45: |
46: MPI_Comm comm = hypre_ParCSRMatrixComm(A); |
47: hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(S); |
48: hypre_ParCSRCommHandle *comm_handle; |
49: hypre_ParCSRCommPkg *tmp_comm_pkg; |
50: |
51: hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A); |
52: HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag); |
53: HYPRE_Int *A_diag_i = hypre_CSRMatrixI(A_diag); |
54: HYPRE_Int *A_diag_j = hypre_CSRMatrixJ(A_diag); |
55: |
56: hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A); |
57: HYPRE_Real *A_offd_data = NULL; |
58: HYPRE_Int *A_offd_i = hypre_CSRMatrixI(A_offd); |
59: HYPRE_Int *A_offd_j = NULL; |
60: HYPRE_Int *col_map_offd_A = hypre_ParCSRMatrixColMapOffd(A); |
61: HYPRE_Int num_cols_offd_A = hypre_CSRMatrixNumCols(A_offd); |
62: |
63: hypre_CSRMatrix *S_diag = hypre_ParCSRMatrixDiag(S); |
64: HYPRE_Int *S_diag_i = hypre_CSRMatrixI(S_diag); |
65: HYPRE_Int *S_diag_j = hypre_CSRMatrixJ(S_diag); |
66: |
67: hypre_CSRMatrix *S_offd = hypre_ParCSRMatrixOffd(S); |
68: HYPRE_Int *S_offd_i = hypre_CSRMatrixI(S_offd); |
69: HYPRE_Int *S_offd_j = NULL; |
70: HYPRE_Int *col_map_offd_S = hypre_ParCSRMatrixColMapOffd(S); |
71: HYPRE_Int num_cols_offd_S = hypre_CSRMatrixNumCols(S_offd); |
[...] |
83: HYPRE_Real *P_offd_data = NULL; |
84: HYPRE_Int *P_offd_i; /*at first counter of nonzero cols for each row, |
85: finally will be pointer to start of row */ |
86: HYPRE_Int *P_offd_j = NULL; |
[...] |
99: HYPRE_Int *Pext_start = NULL; |
100: HYPRE_Int *P_ncols = NULL; |
101: |
102: HYPRE_Int *CF_marker_offd = NULL; |
103: HYPRE_Int *dof_func_offd = NULL; |
104: HYPRE_Int *P_marker; |
105: HYPRE_Int *P_marker_offd = NULL; |
106: HYPRE_Int *C_array; |
107: HYPRE_Int *C_array_offd = NULL; |
108: HYPRE_Int *pass_array = NULL; /* contains points ordered according to pass */ |
109: HYPRE_Int *pass_pointer = NULL; /* pass_pointer[j] contains pointer to first |
110: point of pass j contained in pass_array */ |
111: HYPRE_Int *P_diag_start; |
112: HYPRE_Int *P_offd_start = NULL; |
113: HYPRE_Int **P_diag_pass; |
114: HYPRE_Int **P_offd_pass = NULL; |
115: HYPRE_Int **Pext_pass = NULL; |
116: HYPRE_Int **new_elmts = NULL; /* new neighbors generated in each pass */ |
117: HYPRE_Int *new_counter = NULL; /* contains no. of new neighbors for |
118: each pass */ |
119: HYPRE_Int *loc = NULL; /* contains locations for new neighbor |
120: connections in int_o_buffer to avoid searching */ |
121: HYPRE_Int *Pext_i = NULL; /*contains P_diag_i and P_offd_i info for nonzero |
122: cols of off proc neighbors */ |
123: HYPRE_Int *Pext_send_buffer = NULL; /* used to collect global nonzero |
124: col ids in P_diag for send_map_elmts */ |
125: |
126: HYPRE_Int *map_S_to_new = NULL; |
127: /*HYPRE_Int *map_A_to_new = NULL;*/ |
128: HYPRE_Int *map_A_to_S = NULL; |
129: HYPRE_Int *new_col_map_offd = NULL; |
130: HYPRE_Int *col_map_offd_P = NULL; |
131: HYPRE_Int *permute = NULL; |
[...] |
141: HYPRE_Int n_coarse = 0; |
142: HYPRE_Int n_coarse_offd = 0; |
143: HYPRE_Int n_SF = 0; |
144: HYPRE_Int n_SF_offd = 0; |
145: |
146: HYPRE_Int *fine_to_coarse = NULL; |
147: HYPRE_Int *fine_to_coarse_offd = NULL; |
148: |
149: HYPRE_Int *assigned = NULL; |
150: HYPRE_Int *assigned_offd = NULL; |
151: |
152: HYPRE_Real *Pext_send_data = NULL; |
153: HYPRE_Real *Pext_data = NULL; |
[...] |
184: HYPRE_Int P_offd_size = 0; |
185: HYPRE_Int local_index = -1; |
186: HYPRE_Int new_num_cols_offd = 0; |
[...] |
194: HYPRE_Int * max_num_threads = hypre_CTAlloc(HYPRE_Int, 1); |
[...] |
202: max_num_threads[0] = hypre_NumThreads(); |
203: cnt_nz_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]); |
204: cnt_nz_offd_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]); |
205: for(i=0; i < max_num_threads[0]; i++) |
206: { |
207: cnt_nz_offd_per_thread[i] = 0; |
208: cnt_nz_per_thread[i] = 0; |
[...] |
216: hypre_MPI_Comm_size(comm,&num_procs); |
217: hypre_MPI_Comm_rank(comm,&my_id); |
218: |
219: #ifdef HYPRE_NO_GLOBAL_PARTITION |
220: my_first_cpt = num_cpts_global[0]; |
221: /* total_global_cpts = 0; */ |
222: if (my_id == (num_procs -1)) total_global_cpts = num_cpts_global[1]; |
223: hypre_MPI_Bcast(&total_global_cpts, 1, HYPRE_MPI_INT, num_procs-1, comm); |
[...] |
229: if (!comm_pkg) |
230: { |
231: comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
232: if (!comm_pkg) |
233: { |
234: hypre_MatvecCommPkgCreate(A); |
235: |
236: comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
237: } |
238: col_offd_S_to_A = NULL; |
239: } |
240: |
241: if (col_offd_S_to_A) |
[...] |
252: if (num_cols_offd_A) |
253: { |
254: A_offd_data = hypre_CSRMatrixData(A_offd); |
255: A_offd_j = hypre_CSRMatrixJ(A_offd); |
256: } |
257: |
258: if (num_cols_offd) |
259: S_offd_j = hypre_CSRMatrixJ(S_offd); |
260: |
261: n_fine = hypre_CSRMatrixNumRows(A_diag); |
[...] |
267: if (n_fine) fine_to_coarse = hypre_CTAlloc(HYPRE_Int, n_fine); |
268: |
269: n_coarse = 0; |
270: n_SF = 0; |
271: #ifdef HYPRE_USING_OPENMP |
272: #pragma omp parallel for private(i) reduction(+:n_coarse,n_SF ) HYPRE_SMP_SCHEDULE |
[...] |
278: pass_array_size = n_fine-n_coarse-n_SF; |
279: if (pass_array_size) pass_array = hypre_CTAlloc(HYPRE_Int, pass_array_size); |
280: pass_pointer = hypre_CTAlloc(HYPRE_Int, max_num_passes+1); |
281: if (n_fine) assigned = hypre_CTAlloc(HYPRE_Int, n_fine); |
282: P_diag_i = hypre_CTAlloc(HYPRE_Int, n_fine+1); |
283: P_offd_i = hypre_CTAlloc(HYPRE_Int, n_fine+1); |
284: if (n_coarse) C_array = hypre_CTAlloc(HYPRE_Int, n_coarse); |
285: |
286: if (num_cols_offd) |
287: { |
288: CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
289: if (num_functions > 1) dof_func_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
290: } |
291: |
292: if (num_procs > 1) |
293: { |
294: num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg); |
295: send_procs = hypre_ParCSRCommPkgSendProcs(comm_pkg); |
296: send_map_start = hypre_ParCSRCommPkgSendMapStarts(comm_pkg); |
297: send_map_elmt = hypre_ParCSRCommPkgSendMapElmts(comm_pkg); |
298: num_recvs = hypre_ParCSRCommPkgNumRecvs(comm_pkg); |
299: recv_procs = hypre_ParCSRCommPkgRecvProcs(comm_pkg); |
300: recv_vec_start = hypre_ParCSRCommPkgRecvVecStarts(comm_pkg); |
301: if (send_map_start[num_sends]) |
302: int_buf_data = hypre_CTAlloc(HYPRE_Int, send_map_start[num_sends]); |
303: } |
304: |
305: |
306: index = 0; |
307: for (i=0; i < num_sends; i++) |
308: { |
309: start = send_map_start[i]; |
310: for (j = start; j < send_map_start[i+1]; j++) |
311: int_buf_data[index++] = CF_marker[send_map_elmt[j]]; |
312: } |
313: if (num_procs > 1) |
314: { |
315: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
316: CF_marker_offd); |
317: hypre_ParCSRCommHandleDestroy(comm_handle); |
318: } |
319: |
320: if (num_functions > 1) |
321: { |
322: index = 0; |
323: for (i=0; i < num_sends; i++) |
324: { |
325: start = send_map_start[i]; |
326: for (j = start; j < send_map_start[i+1]; j++) |
327: int_buf_data[index++] = dof_func[send_map_elmt[j]]; |
328: } |
329: if (num_procs > 1) |
330: { |
331: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
332: dof_func_offd); |
333: hypre_ParCSRCommHandleDestroy(comm_handle); |
334: } |
335: } |
336: |
337: n_coarse_offd = 0; |
338: n_SF_offd = 0; |
339: #ifdef HYPRE_USING_OPENMP |
340: #pragma omp parallel for private(i) reduction(+:n_coarse_offd,n_SF_offd) HYPRE_SMP_SCHEDULE |
[...] |
346: if (num_cols_offd) |
347: { |
348: assigned_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
349: map_S_to_new = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
350: fine_to_coarse_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
351: new_col_map_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd); |
[...] |
382: p_cnt = pass_array_size-1; |
383: P_diag_i[0] = 0; |
384: P_offd_i[0] = 0; |
385: for (i = 0; i < n_fine; i++) |
386: { |
387: if (CF_marker[i] == 1) |
388: { |
389: fine_to_coarse[i] = cnt; /* this C point is assigned index |
390: coarse_counter on coarse grid, |
391: and in column of P */ |
392: C_array[cnt++] = i; |
393: assigned[i] = 0; |
394: P_diag_i[i+1] = 1; /* one element in row i1 of P */ |
395: P_offd_i[i+1] = 0; |
396: } |
397: else if (CF_marker[i] == -1) |
398: { |
399: pass_array[p_cnt--] = i; |
400: P_diag_i[i+1] = 0; |
[...] |
415: for (i=0; i < num_sends; i++) |
416: { |
417: start = send_map_start[i]; |
418: for (j = start; j < send_map_start[i+1]; j++) |
419: { |
420: int_buf_data[index] = fine_to_coarse[send_map_elmt[j]]; |
421: if (int_buf_data[index] > -1) |
422: int_buf_data[index] += my_first_cpt; |
423: index++; |
424: } |
425: } |
426: if (num_procs > 1) |
427: { |
428: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
429: fine_to_coarse_offd); |
430: hypre_ParCSRCommHandleDestroy(comm_handle); |
431: } |
432: |
433: new_recv_vec_start = hypre_CTAlloc(HYPRE_Int,num_recvs+1); |
434: |
435: if (n_coarse_offd) |
436: C_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd); |
437: |
438: cnt = 0; |
439: new_recv_vec_start[0] = 0; |
440: for (j = 0; j < num_recvs; j++) |
441: { |
442: for (i = recv_vec_start[j]; i < recv_vec_start[j+1]; i++) |
443: { |
444: if (CF_marker_offd[i] == 1) |
445: { |
446: map_S_to_new[i] = cnt; |
447: C_array_offd[cnt] = i; |
448: new_col_map_offd[cnt++] = fine_to_coarse_offd[i]; |
449: assigned_offd[i] = 0; |
450: } |
451: else |
452: { |
453: assigned_offd[i] = -1; |
454: map_S_to_new[i] = -1; |
455: } |
456: } |
457: new_recv_vec_start[j+1] = cnt; |
458: } |
459: |
460: cnt = 0; |
461: hypre_TFree(fine_to_coarse_offd); |
462: |
463: if (col_offd_S_to_A) |
464: { |
465: map_A_to_S = hypre_CTAlloc(HYPRE_Int,num_cols_offd_A); |
466: for (i=0; i < num_cols_offd_A; i++) |
467: { |
468: if (cnt < num_cols_offd && col_map_offd_A[i] == col_map_offd[cnt]) |
[...] |
479: pass_pointer[0] = 0; |
480: pass_pointer[1] = 0; |
481: total_nz = n_coarse; /* accumulates total number of nonzeros in P_diag */ |
482: total_nz_offd = 0; /* accumulates total number of nonzeros in P_offd */ |
[...] |
488: for (i = pass_array_size-1; i > cnt-1; i--) |
489: { |
490: i1 = pass_array[i]; |
491: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
492: { |
493: j1 = S_diag_j[j]; |
494: if (CF_marker[j1] == 1) |
495: { |
496: P_diag_i[i1+1]++; |
497: cnt_nz++; |
498: assigned[i1] = 1; |
499: } |
500: } |
501: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
502: { |
503: j1 = S_offd_j[j]; |
504: if (CF_marker_offd[j1] == 1) |
505: { |
506: P_offd_i[i1+1]++; |
507: cnt_nz_offd++; |
508: assigned[i1] = 1; |
509: } |
510: } |
511: if (assigned[i1] == 1) |
512: { |
513: pass_array[i++] = pass_array[cnt]; |
514: pass_array[cnt++] = i1; |
515: } |
516: } |
517: |
518: pass_pointer[2] = cnt; |
[...] |
526: for (i=0; i < num_sends; i++) |
527: { |
528: start = send_map_start[i]; |
529: for (j = start; j < send_map_start[i+1]; j++) |
530: { int_buf_data[index++] = assigned[send_map_elmt[j]]; } |
531: } |
532: if (num_procs > 1) |
533: { |
534: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
535: assigned_offd); |
536: hypre_ParCSRCommHandleDestroy(comm_handle); |
[...] |
544: pass = 2; |
545: local_pass_array_size = pass_array_size - cnt; |
546: hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT, |
547: hypre_MPI_SUM, comm); |
548: while (global_pass_array_size && pass < max_num_passes) |
549: { |
550: for (i = pass_array_size-1; i > cnt-1; i--) |
551: { |
552: i1 = pass_array[i]; |
553: no_break = 1; |
554: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
555: { |
556: j1 = S_diag_j[j]; |
557: if (assigned[j1] == pass-1) |
[...] |
568: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
569: { |
570: j1 = S_offd_j[j]; |
571: if (assigned_offd[j1] == pass-1) |
[...] |
583: pass++; |
584: pass_pointer[pass] = cnt; |
585: |
586: local_pass_array_size = pass_array_size - cnt; |
587: hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT, |
588: hypre_MPI_SUM, comm); |
589: index = 0; |
590: for (i=0; i < num_sends; i++) |
591: { |
592: start = send_map_start[i]; |
593: for (j = start; j < send_map_start[i+1]; j++) |
594: { int_buf_data[index++] = assigned[send_map_elmt[j]]; } |
595: } |
596: if (num_procs > 1) |
597: { |
598: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
599: assigned_offd); |
600: hypre_ParCSRCommHandleDestroy(comm_handle); |
601: } |
602: } |
603: |
604: hypre_TFree(int_buf_data); |
605: |
606: num_passes = pass; |
607: |
608: P_diag_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); /* P_diag_pass[i] will contain |
609: all column numbers for points of pass i */ |
610: |
611: P_diag_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz); |
612: |
613: P_diag_start = hypre_CTAlloc(HYPRE_Int, n_fine); /* P_diag_start[i] contains |
614: pointer to begin of column numbers in P_pass for point i, |
615: P_diag_i[i+1] contains number of columns for point i */ |
616: |
617: P_offd_start = hypre_CTAlloc(HYPRE_Int, n_fine); |
618: |
619: if (num_procs > 1) |
620: { |
621: P_offd_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); |
622: |
623: if (cnt_nz_offd) |
624: P_offd_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz_offd); |
625: else |
626: P_offd_pass[1] = NULL; |
627: |
628: new_elmts = hypre_CTAlloc(HYPRE_Int*,num_passes); |
629: |
630: new_counter = hypre_CTAlloc(HYPRE_Int, num_passes+1); |
631: |
632: new_counter[0] = 0; |
633: new_counter[1] = n_coarse_offd; |
634: new_num_cols_offd = n_coarse_offd; |
635: |
636: new_elmts[0] = new_col_map_offd; |
[...] |
646: for (i=pass_pointer[1]; i < pass_pointer[2]; i++) |
647: { |
648: i1 = pass_array[i]; |
649: P_diag_start[i1] = cnt_nz; |
650: P_offd_start[i1] = cnt_nz_offd; |
651: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
652: { |
653: j1 = S_diag_j[j]; |
654: if (CF_marker[j1] == 1) |
655: { P_diag_pass[1][cnt_nz++] = fine_to_coarse[j1]; } |
656: } |
657: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
658: { |
659: j1 = S_offd_j[j]; |
660: if (CF_marker_offd[j1] == 1) |
661: { P_offd_pass[1][cnt_nz_offd++] = map_S_to_new[j1]; } |
662: } |
663: } |
664: |
665: |
666: total_nz += cnt_nz; |
667: total_nz_offd += cnt_nz_offd; |
668: |
669: if (num_procs > 1) |
670: { |
671: tmp_comm_pkg = hypre_CTAlloc(hypre_ParCSRCommPkg,1); |
672: Pext_send_map_start = hypre_CTAlloc(HYPRE_Int*,num_passes); |
673: Pext_recv_vec_start = hypre_CTAlloc(HYPRE_Int*,num_passes); |
674: Pext_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); |
675: Pext_i = hypre_CTAlloc(HYPRE_Int, num_cols_offd+1); |
676: if (num_cols_offd) Pext_start = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
677: if (send_map_start[num_sends]) |
678: P_ncols = hypre_CTAlloc(HYPRE_Int,send_map_start[num_sends]); |
679: #ifdef HYPRE_USING_OPENMP |
680: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
681: #endif |
682: for (i=0; i < num_cols_offd+1; i++) |
683: { Pext_i[i] = 0; } |
684: #ifdef HYPRE_USING_OPENMP |
685: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
693: for (pass=2; pass < num_passes; pass++) |
694: { |
695: |
696: if (num_procs > 1) |
697: { |
698: Pext_send_map_start[pass] = hypre_CTAlloc(HYPRE_Int, num_sends+1); |
699: Pext_recv_vec_start[pass] = hypre_CTAlloc(HYPRE_Int, num_recvs+1); |
700: Pext_send_size = 0; |
701: Pext_send_map_start[pass][0] = 0; |
702: |
703: for (i=0; i < num_sends; i++) |
704: { |
705: #ifdef HYPRE_USING_OPENMP |
706: #pragma omp parallel for private(j,j1) reduction(+:Pext_send_size) HYPRE_SMP_SCHEDULE |
[...] |
717: Pext_send_map_start[pass][i+1] = Pext_send_size; |
718: } |
719: |
720: comm_handle = hypre_ParCSRCommHandleCreate (11, comm_pkg, |
721: P_ncols, &Pext_i[1]); |
722: hypre_ParCSRCommHandleDestroy(comm_handle); |
723: |
724: if (Pext_send_size > old_Pext_send_size) |
725: { |
726: hypre_TFree(Pext_send_buffer); |
727: Pext_send_buffer = hypre_CTAlloc(HYPRE_Int, Pext_send_size); |
728: } |
729: old_Pext_send_size = Pext_send_size; |
730: } |
731: |
732: cnt_offd = 0; |
733: for (i=0; i < num_sends; i++) |
734: { |
735: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
736: { |
737: j1 = send_map_elmt[j]; |
738: if (assigned[j1] == pass-1) |
739: { |
740: j_start = P_diag_start[j1]; |
741: j_end = j_start+P_diag_i[j1+1]; |
742: for (k=j_start; k < j_end; k++) |
743: { |
744: Pext_send_buffer[cnt_offd++] = my_first_cpt |
745: +P_diag_pass[pass-1][k]; |
746: } |
747: j_start = P_offd_start[j1]; |
748: j_end = j_start+P_offd_i[j1+1]; |
749: for (k=j_start; k < j_end; k++) |
750: { |
751: k1 = P_offd_pass[pass-1][k]; |
752: k3 = 0; |
753: while (k3 < pass-1) |
754: { |
755: if (k1 < new_counter[k3+1]) |
756: { |
757: k2 = k1-new_counter[k3]; |
758: Pext_send_buffer[cnt_offd++] = new_elmts[k3][k2]; |
[...] |
768: if (num_procs > 1) |
769: { |
770: Pext_recv_size = 0; |
771: Pext_recv_vec_start[pass][0] = 0; |
772: cnt_offd = 0; |
773: for (i=0; i < num_recvs; i++) |
774: { |
775: for (j=recv_vec_start[i]; j<recv_vec_start[i+1]; j++) |
776: { |
777: if (assigned_offd[j] == pass-1) |
778: { |
779: Pext_start[j] = cnt_offd; |
780: cnt_offd += Pext_i[j+1]; |
781: } |
782: } |
783: Pext_recv_size = cnt_offd; |
784: Pext_recv_vec_start[pass][i+1] = Pext_recv_size; |
785: } |
786: |
787: hypre_ParCSRCommPkgComm(tmp_comm_pkg) = comm; |
788: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
789: hypre_ParCSRCommPkgSendProcs(tmp_comm_pkg) = send_procs; |
790: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
791: Pext_send_map_start[pass]; |
792: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
793: hypre_ParCSRCommPkgRecvProcs(tmp_comm_pkg) = recv_procs; |
794: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
795: Pext_recv_vec_start[pass]; |
796: |
797: if (Pext_recv_size) |
798: { |
799: Pext_pass[pass] = hypre_CTAlloc(HYPRE_Int, Pext_recv_size); |
800: new_elmts[pass-1] = hypre_CTAlloc(HYPRE_Int,Pext_recv_size); |
801: } |
802: else |
803: { |
804: Pext_pass[pass] = NULL; |
805: new_elmts[pass-1] = NULL; |
806: } |
807: |
808: comm_handle = hypre_ParCSRCommHandleCreate (11, tmp_comm_pkg, |
809: Pext_send_buffer, Pext_pass[pass]); |
810: hypre_ParCSRCommHandleDestroy(comm_handle); |
811: |
812: if (Pext_recv_size > old_Pext_recv_size) |
813: { |
814: hypre_TFree(loc); |
815: loc = hypre_CTAlloc(HYPRE_Int,Pext_recv_size); |
[...] |
823: for (i=0; i < num_recvs; i++) |
824: { |
825: for (j=recv_vec_start[i]; j < recv_vec_start[i+1]; j++) |
826: { |
827: if (assigned_offd[j] == pass-1) |
828: { |
829: for (j1 = cnt_offd; j1 < cnt_offd+Pext_i[j+1]; j1++) |
830: { |
831: k1 = Pext_pass[pass][j1]; |
832: k2 = k1 - my_first_cpt; |
833: if (k2 > -1 && k2 < n_coarse) |
834: { Pext_pass[pass][j1] = -k2-1; } |
835: else |
836: { |
837: not_found = 1; |
838: k3 = 0; |
839: while (k3 < pass-1 && not_found) |
840: { |
841: k2 = hypre_BinarySearch(new_elmts[k3], k1, |
842: (new_counter[k3+1]-new_counter[k3])); |
843: if (k2 > -1) |
844: { |
845: Pext_pass[pass][j1] = k2 + new_counter[k3]; |
[...] |
855: new_elmts[pass-1][cnt_new] = Pext_pass[pass][j1]; |
856: loc[cnt_new++] = j1; |
[...] |
865: if (cnt_new) |
866: { |
867: hypre_qsort2i(new_elmts[pass-1],loc,0,cnt_new-1); |
868: cnt = 0; |
869: local_index = new_counter[pass-1]; |
870: Pext_pass[pass][loc[0]] = local_index; |
871: |
872: for (i=1; i < cnt_new; i++) |
873: { |
874: if (new_elmts[pass-1][i] > new_elmts[pass-1][cnt]) |
875: { |
876: new_elmts[pass-1][++cnt] = new_elmts[pass-1][i]; |
877: local_index++; |
878: } |
879: Pext_pass[pass][loc[i]] = local_index; |
880: } |
881: new_counter[pass] = local_index+1; |
882: } |
883: else if (num_procs > 1) |
884: new_counter[pass] = new_counter[pass-1]; |
885: |
886: if (new_num_cols_offd < local_index+1) |
887: { new_num_cols_offd = local_index+1; } |
888: |
889: pass_length = pass_pointer[pass+1] - pass_pointer[pass]; |
890: #ifdef HYPRE_USING_OPENMP |
891: #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd) |
[...] |
1140: hypre_TFree(loc); |
1141: hypre_TFree(P_ncols); |
1142: hypre_TFree(Pext_send_buffer); |
1143: hypre_TFree(new_recv_vec_start); |
1144: hypre_TFree(cnt_nz_per_thread); |
1145: hypre_TFree(cnt_nz_offd_per_thread); |
1146: hypre_TFree(max_num_threads); |
1147: |
1148: P_diag_j = hypre_CTAlloc(HYPRE_Int,total_nz); |
1149: P_diag_data = hypre_CTAlloc(HYPRE_Real,total_nz); |
1150: |
1151: |
1152: if (total_nz_offd) |
1153: { |
1154: P_offd_j = hypre_CTAlloc(HYPRE_Int,total_nz_offd); |
1155: P_offd_data = hypre_CTAlloc(HYPRE_Real,total_nz_offd); |
1156: } |
1157: |
1158: for (i=0; i < n_fine; i++) |
1159: { |
1160: P_diag_i[i+1] += P_diag_i[i]; |
1161: P_offd_i[i+1] += P_offd_i[i]; |
[...] |
1167: #pragma omp parallel for private(i,i1) HYPRE_SMP_SCHEDULE |
[...] |
1177: if (weight_option) /*if this is set, weights are separated into |
[...] |
1184: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_pos,sum_C_neg,sum_N_pos,sum_N_neg,j_start,j_end,j,k1,cnt,j1,cnt_offd,diagonal,alfa,beta) |
[...] |
1304: if (n_coarse) hypre_TFree(C_array); |
1305: hypre_TFree(C_array_offd); |
1306: hypre_TFree(P_diag_pass[1]); |
1307: if (num_procs > 1) hypre_TFree(P_offd_pass[1]); |
1308: |
1309: |
1310: for (pass = 2; pass < num_passes; pass++) |
1311: { |
1312: |
1313: if (num_procs > 1) |
1314: { |
1315: Pext_send_size = Pext_send_map_start[pass][num_sends]; |
1316: if (Pext_send_size > old_Pext_send_size) |
1317: { |
1318: hypre_TFree(Pext_send_data); |
1319: Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size); |
1320: } |
1321: old_Pext_send_size = Pext_send_size; |
1322: |
1323: cnt_offd = 0; |
1324: for (i=0; i < num_sends; i++) |
1325: { |
1326: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
1327: { |
1328: j1 = send_map_elmt[j]; |
1329: if (assigned[j1] == pass-1) |
1330: { |
1331: j_start = P_diag_i[j1]; |
1332: j_end = P_diag_i[j1+1]; |
1333: for (k=j_start; k < j_end; k++) |
1334: { Pext_send_data[cnt_offd++] = P_diag_data[k]; } |
1335: j_start = P_offd_i[j1]; |
1336: j_end = P_offd_i[j1+1]; |
1337: for (k=j_start; k < j_end; k++) |
1338: { Pext_send_data[cnt_offd++] = P_offd_data[k]; } |
1339: } |
1340: } |
1341: } |
1342: |
1343: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
1344: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
1345: Pext_send_map_start[pass]; |
1346: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
1347: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
1348: Pext_recv_vec_start[pass]; |
1349: |
1350: Pext_recv_size = Pext_recv_vec_start[pass][num_recvs]; |
1351: |
1352: if (Pext_recv_size > old_Pext_recv_size) |
1353: { |
1354: hypre_TFree(Pext_data); |
1355: Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size); |
1356: } |
1357: old_Pext_recv_size = Pext_recv_size; |
1358: |
1359: comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg, |
1360: Pext_send_data, Pext_data); |
1361: hypre_ParCSRCommHandleDestroy(comm_handle); |
1362: |
1363: hypre_TFree(Pext_send_map_start[pass]); |
1364: hypre_TFree(Pext_recv_vec_start[pass]); |
1365: } |
1366: |
1367: pass_length = pass_pointer[pass+1]-pass_pointer[pass]; |
1368: #ifdef HYPRE_USING_OPENMP |
1369: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_neg,sum_C_pos,sum_N_neg,sum_N_pos,j_start,j_end,cnt,j,k1,cnt_offd,j1,k,alfa,beta,diagonal,C_array,C_array_offd) |
[...] |
1562: hypre_TFree(P_diag_pass[pass]); |
1563: if (num_procs > 1) |
1564: { |
1565: hypre_TFree(P_offd_pass[pass]); |
1566: hypre_TFree(Pext_pass[pass]); |
[...] |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1669: if (n_coarse) hypre_TFree(C_array); |
1670: hypre_TFree(C_array_offd); |
1671: hypre_TFree(P_diag_pass[1]); |
1672: if (num_procs > 1) hypre_TFree(P_offd_pass[1]); |
1673: |
1674: for (pass = 2; pass < num_passes; pass++) |
1675: { |
1676: |
1677: if (num_procs > 1) |
1678: { |
1679: Pext_send_size = Pext_send_map_start[pass][num_sends]; |
1680: if (Pext_send_size > old_Pext_send_size) |
1681: { |
1682: hypre_TFree(Pext_send_data); |
1683: Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size); |
1684: } |
1685: old_Pext_send_size = Pext_send_size; |
1686: |
1687: cnt_offd = 0; |
1688: for (i=0; i < num_sends; i++) |
1689: { |
1690: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
1691: { |
1692: j1 = send_map_elmt[j]; |
1693: if (assigned[j1] == pass-1) |
1694: { |
1695: j_start = P_diag_i[j1]; |
1696: j_end = P_diag_i[j1+1]; |
1697: for (k=j_start; k < j_end; k++) |
1698: { |
1699: Pext_send_data[cnt_offd++] = P_diag_data[k]; |
1700: } |
1701: j_start = P_offd_i[j1]; |
1702: j_end = P_offd_i[j1+1]; |
1703: for (k=j_start; k < j_end; k++) |
1704: { |
1705: Pext_send_data[cnt_offd++] = P_offd_data[k]; |
[...] |
1711: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
1712: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
1713: Pext_send_map_start[pass]; |
1714: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
1715: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
1716: Pext_recv_vec_start[pass]; |
1717: |
1718: Pext_recv_size = Pext_recv_vec_start[pass][num_recvs]; |
1719: |
1720: if (Pext_recv_size > old_Pext_recv_size) |
1721: { |
1722: hypre_TFree(Pext_data); |
1723: Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size); |
1724: } |
1725: old_Pext_recv_size = Pext_recv_size; |
1726: |
1727: comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg, |
1728: Pext_send_data, Pext_data); |
1729: hypre_ParCSRCommHandleDestroy(comm_handle); |
1730: |
1731: hypre_TFree(Pext_send_map_start[pass]); |
1732: hypre_TFree(Pext_recv_vec_start[pass]); |
1733: } |
1734: |
1735: pass_length = pass_pointer[pass+1]-pass_pointer[pass]; |
1736: #ifdef HYPRE_USING_OPENMP |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1884: hypre_TFree(P_diag_pass[pass]); |
1885: if (num_procs > 1) |
1886: { |
1887: hypre_TFree(P_offd_pass[pass]); |
1888: hypre_TFree(Pext_pass[pass]); |
1889: } |
1890: } |
1891: } |
1892: |
1893: hypre_TFree(CF_marker_offd); |
1894: hypre_TFree(Pext_send_map_start); |
1895: hypre_TFree(Pext_recv_vec_start); |
1896: hypre_TFree(dof_func_offd); |
1897: hypre_TFree(Pext_send_data); |
1898: hypre_TFree(Pext_data); |
1899: hypre_TFree(P_diag_pass); |
1900: hypre_TFree(P_offd_pass); |
1901: hypre_TFree(Pext_pass); |
1902: hypre_TFree(P_diag_start); |
1903: hypre_TFree(P_offd_start); |
1904: hypre_TFree(Pext_start); |
1905: hypre_TFree(Pext_i); |
1906: hypre_TFree(fine_to_coarse); |
1907: hypre_TFree(assigned); |
1908: hypre_TFree(assigned_offd); |
1909: hypre_TFree(pass_pointer); |
1910: hypre_TFree(pass_array); |
1911: hypre_TFree(map_S_to_new); |
1912: hypre_TFree(map_A_to_S); |
1913: if (num_procs > 1) hypre_TFree(tmp_comm_pkg); |
1914: |
1915: P = hypre_ParCSRMatrixCreate(comm, |
1916: hypre_ParCSRMatrixGlobalNumRows(A), |
1917: total_global_cpts, |
1918: hypre_ParCSRMatrixColStarts(A), |
1919: num_cpts_global, |
1920: 0, |
1921: P_diag_i[n_fine], |
1922: P_offd_i[n_fine]); |
1923: P_diag = hypre_ParCSRMatrixDiag(P); |
1924: hypre_CSRMatrixData(P_diag) = P_diag_data; |
1925: hypre_CSRMatrixI(P_diag) = P_diag_i; |
1926: hypre_CSRMatrixJ(P_diag) = P_diag_j; |
1927: P_offd = hypre_ParCSRMatrixOffd(P); |
1928: hypre_CSRMatrixData(P_offd) = P_offd_data; |
1929: hypre_CSRMatrixI(P_offd) = P_offd_i; |
1930: hypre_CSRMatrixJ(P_offd) = P_offd_j; |
1931: hypre_ParCSRMatrixOwnsRowStarts(P) = 0; |
1932: |
1933: /* Compress P, removing coefficients smaller than trunc_factor * Max |
1934: and/or keep yat most <P_max_elmts> per row absolutely maximal coefficients */ |
1935: |
1936: if (trunc_factor != 0.0 || P_max_elmts != 0) |
1937: { |
1938: hypre_BoomerAMGInterpTruncation(P, trunc_factor, P_max_elmts); |
1939: P_diag_data = hypre_CSRMatrixData(P_diag); |
1940: P_diag_i = hypre_CSRMatrixI(P_diag); |
1941: P_diag_j = hypre_CSRMatrixJ(P_diag); |
1942: P_offd_data = hypre_CSRMatrixData(P_offd); |
1943: P_offd_i = hypre_CSRMatrixI(P_offd); |
1944: P_offd_j = hypre_CSRMatrixJ(P_offd); |
1945: } |
1946: P_offd_size = P_offd_i[n_fine]; |
1947: |
1948: num_cols_offd_P = 0; |
1949: if (P_offd_size) |
1950: { |
1951: if (new_num_cols_offd > num_cols_offd) |
1952: { P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1953: else |
1954: { P_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1955: #ifdef HYPRE_USING_OPENMP |
1956: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
1957: #endif |
1958: for (i=0; i < new_num_cols_offd; i++) |
1959: { P_marker_offd[i] = 0; } |
1960: |
1961: num_cols_offd_P = 0; |
1962: for (i=0; i < P_offd_size; i++) |
1963: { |
1964: index = P_offd_j[i]; |
1965: if (!P_marker_offd[index]) |
1966: { |
1967: num_cols_offd_P++; |
1968: P_marker_offd[index] = 1; |
1969: } |
1970: } |
1971: |
1972: col_map_offd_P = hypre_CTAlloc(HYPRE_Int,num_cols_offd_P); |
1973: permute = hypre_CTAlloc(HYPRE_Int, new_counter[num_passes-1]); |
1974: |
1975: #ifdef HYPRE_USING_OPENMP |
1976: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
1982: for (i=0; i < num_passes-1; i++) |
1983: { |
1984: for (j=new_counter[i]; j < new_counter[i+1]; j++) |
1985: { |
1986: if (P_marker_offd[j]) |
1987: { |
1988: col_map_offd_P[cnt] = new_elmts[i][j-new_counter[i]]; |
1989: permute[j] = col_map_offd_P[cnt++]; |
1990: } |
1991: } |
1992: } |
1993: |
1994: hypre_qsort0(col_map_offd_P,0,num_cols_offd_P-1); |
1995: |
1996: #ifdef HYPRE_USING_OPENMP |
1997: #pragma omp parallel for private(i,k1) HYPRE_SMP_SCHEDULE |
[...] |
2007: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
2008: #endif |
2009: for (i=0; i < P_offd_size; i++) |
2010: { P_offd_j[i] = permute[P_offd_j[i]]; } |
2011: |
2012: hypre_TFree(P_marker_offd); |
2013: } |
2014: if (num_procs > 1) |
2015: { |
2016: for (i=0; i < num_passes-1; i++) |
2017: hypre_TFree(new_elmts[i]); |
2018: } |
2019: hypre_TFree(permute); |
2020: hypre_TFree(new_elmts); |
2021: hypre_TFree(new_counter); |
2022: |
2023: if (num_cols_offd_P) |
2024: { |
2025: hypre_ParCSRMatrixColMapOffd(P) = col_map_offd_P; |
2026: hypre_CSRMatrixNumCols(P_offd) = num_cols_offd_P; |
2027: } |
2028: |
2029: if (n_SF) |
2030: { |
2031: #ifdef HYPRE_USING_OPENMP |
2032: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
2038: if (num_procs > 1) |
2039: { |
2040: hypre_MatvecCommPkgCreate(P); |
2041: } |
2042: |
2043: *P_ptr = P; |
[...] |
2060: return(0); |
0x4324e0 STR D8, [SP, #400]! |
0x4324e4 STP X29, X30, [SP, #16] |
0x4324e8 STP X28, X27, [SP, #32] |
0x4324ec STP X26, X25, [SP, #48] |
0x4324f0 STP X24, X23, [SP, #64] |
0x4324f4 STP X22, X21, [SP, #80] |
0x4324f8 STP X20, X19, [SP, #96] |
0x4324fc ADD X29, SP, #16 |
0x432500 SUB SP, SP, #1008 |
0x432504 LDP X22, X23, [X0, #56] |
0x432508 STUR X1, [X29, #504] |
0x43250c STP X5, X4, [X29, #984] |
0x432510 LDR X10, [X0] |
0x432514 MOVZ W1, #8 |
0x432518 FMOV D8, D0 |
0x43251c LDR X24, [X0, #88] |
0x432520 LDR X26, [X2, #88] |
0x432524 STP X7, X0, [SP, #304] |
0x432528 MOVZ W0, #1 |
0x43252c STR X3, [SP, #320] |
0x432530 LDR X8, [X22, #48] |
0x432534 LDR X21, [X23, #24] |
0x432538 STUR X8, [X29, #464] |
0x43253c LDP X8, X9, [X22] |
0x432540 STP XZR, X9, [X29, #952] |
0x432544 STUR X8, [X29, #456] |
0x432548 LDR X8, [X23] |
0x43254c STP XZR, X8, [X29, #936] |
0x432550 LDP X8, X25, [X2, #56] |
0x432554 LDP X9, X8, [X8] |
0x432558 LDR X28, [X25, #24] |
0x43255c STP X8, X9, [X29, #920] |
0x432560 LDR X9, [X2, #112] |
0x432564 LDR X8, [X25] |
0x432568 STUR XZR, [X29, #392] |
0x43256c STUR XZR, [X29, #352] |
0x432570 STP XZR, XZR, [X29, #840] |
0x432574 STP XZR, XZR, [X29, #808] |
0x432578 STP XZR, XZR, [X29, #792] |
0x43257c STUR XZR, [X29, #272] |
0x432580 STUR XZR, [X29, #256] |
0x432584 STR XZR, [SP, #760] |
0x432588 STR XZR, [SP, #752] |
0x43258c STR XZR, [SP, #736] |
0x432590 STR XZR, [SP, #720] |
0x432594 STR XZR, [SP, #712] |
0x432598 STR XZR, [SP, #704] |
0x43259c STR XZR, [SP, #696] |
0x4325a0 STR XZR, [SP, #688] |
0x4325a4 STR XZR, [SP, #680] |
0x4325a8 STR XZR, [SP, #672] |
0x4325ac STR XZR, [SP, #664] |
0x4325b0 STR XZR, [SP, #624] |
0x4325b4 STR XZR, [SP, #616] |
0x4325b8 STR XZR, [SP, #608] |
0x4325bc STR XZR, [SP, #600] |
0x4325c0 STR XZR, [SP, #592] |
0x4325c4 STR XZR, [SP, #584] |
0x4325c8 STR XZR, [SP, #576] |
0x4325cc STR XZR, [SP, #568] |
0x4325d0 STR XZR, [SP, #480] |
0x4325d4 STP X9, X10, [SP, #376] |
0x4325d8 STUR X8, [X29, #400] |
0x4325dc MOVN X8, #0 |
0x4325e0 STP X8, XZR, [SP, #488] |
0x4325e4 BL 4ae430 |
0x4325e8 ORR X19, XZR, X0 |
0x4325ec STR X0, [SP, #456] |
0x4325f0 BL 4b05a0 |
0x4325f4 MOVZ W1, #8 |
0x4325f8 STR X0, [X19] |
0x4325fc BL 4ae430 |
0x432600 STR X0, [SP, #448] |
0x432604 ORR X20, XZR, X0 |
0x432608 MOVZ W1, #8 |
0x43260c LDR X0, [X19] |
0x432610 BL 4ae430 |
0x432614 STR X0, [SP, #440] |
0x432618 STR XZR, [SP, #560] |
0x43261c LDR X8, [X19] |
0x432620 CMP X8, #1 |
0x432624 B.LT 432650 |
0x432628 ORR X8, XZR, XZR |
(1736) 0x43262c STR XZR, [X0, X8,LSL #3] |
(1736) 0x432630 LDR X8, [SP, #560] |
(1736) 0x432634 STR XZR, [X20, X8,LSL #3] |
(1736) 0x432638 LDR X8, [SP, #560] |
(1736) 0x43263c ADD X8, X8, #1 |
(1736) 0x432640 STR X8, [SP, #560] |
(1736) 0x432644 LDR X9, [X19] |
(1736) 0x432648 CMP X8, X9 |
(1736) 0x43264c B.LT 43262c |
0x432650 LDR X19, [SP, #384] |
0x432654 ADD X1, SP, #528 |
0x432658 ORR X0, XZR, X19 |
0x43265c BL 4afa30 |
0x432660 ORR X0, XZR, X19 |
0x432664 ADD X1, SP, #536 |
0x432668 BL 4afa60 |
0x43266c LDR X9, [SP, #528] |
0x432670 LDR X8, [SP, #536] |
0x432674 SUB X3, X9, #1 |
0x432678 CMP X8, X3 |
0x43267c B.NE 43268c |
0x432680 LDR X8, [SP, #320] |
0x432684 LDR X8, [X8, #8] |
0x432688 STR X8, [SP, #520] |
0x43268c LDR X8, [SP, #320] |
0x432690 ADRP X2, |
0x432694 ADD X0, SP, #520 |
0x432698 MOVZ W1, #1 |
0x43269c LDR X27, [X8] |
0x4326a0 LDR X2, [X2, #3928] |
0x4326a4 LDR X4, [SP, #384] |
0x4326a8 BL 4b0030 |
0x4326ac LDR X8, [SP, #376] |
0x4326b0 CBZ X8, 432784 |
0x4326b4 LDR X8, [X29, #104] |
0x4326b8 CMP X8, #0 |
0x4326bc CSEL X8, X21, X28, #0 |
0x4326c0 CSEL X20, X24, X26, #0 |
0x4326c4 STUR X8, [X29, #384] |
0x4326c8 CBZ X21, 4326dc |
0x4326cc LDR X9, [X23, #48] |
0x4326d0 STUR X9, [X29, #440] |
0x4326d4 LDR X9, [X23, #8] |
0x4326d8 STUR X9, [X29, #424] |
0x4326dc CBZ X8, 4326e8 |
0x4326e0 LDR X8, [X25, #8] |
0x4326e4 STUR X8, [X29, #392] |
0x4326e8 LDR X0, [X22, #16] |
0x4326ec STR X0, [SP, #632] |
0x4326f0 CBZ X0, 432700 |
0x4326f4 MOVZ W1, #8 |
0x4326f8 BL 4ae430 |
0x4326fc STR X0, [SP, #592] |
0x432700 ADRP X0, |
0x432704 ADD X0, X0, #240 |
0x432708 ADRP X2, 435708 |
0x43270c ADD X2, X2, #592 |
0x432710 STR XZR, [SP, #624] |
0x432714 STR XZR, [SP, #608] |
0x432718 ADD X3, SP, #632 |
0x43271c SUB X4, X29, #8 |
0x432720 ADD X5, SP, #624 |
0x432724 ADD X6, SP, #608 |
0x432728 MOVZ W1, #4 |
0x43272c BL 40fa00 |
0x432730 LDR X9, [SP, #624] |
0x432734 LDR X10, [SP, #608] |
0x432738 LDR X8, [SP, #632] |
0x43273c ADD X9, X10, X9 |
0x432740 SUBS X28, X8, X9 |
0x432744 B.EQ 432758 |
0x432748 ORR X0, XZR, X28 |
0x43274c MOVZ W1, #8 |
0x432750 BL 4ae430 |
0x432754 STR X0, [SP, #760] |
0x432758 MOVZ W0, #11 |
0x43275c MOVZ W1, #8 |
0x432760 BL 4ae430 |
0x432764 STR X0, [SP, #752] |
0x432768 LDR X0, [SP, #632] |
0x43276c CBZ X0, 4327c8 |
0x432770 MOVZ W1, #8 |
0x432774 BL 4ae430 |
0x432778 LDR X8, [SP, #632] |
0x43277c STR X0, [SP, #584] |
0x432780 B 4327cc |
0x432784 LDR X8, [SP, #312] |
0x432788 LDR X8, [X8, #112] |
0x43278c STR X8, [SP, #376] |
0x432790 CBNZ X8, 4327a8 |
0x432794 LDR X19, [SP, #312] |
0x432798 ORR X0, XZR, X19 |
0x43279c BL 486250 |
0x4327a0 LDR X8, [X19, #112] |
0x4327a4 STR X8, [SP, #376] |
0x4327a8 ORR X8, XZR, XZR |
0x4327ac STR XZR, [X29, #104] |
0x4327b0 CMP X8, #0 |
0x4327b4 CSEL X8, X21, X28, #0 |
0x4327b8 CSEL X20, X24, X26, #0 |
0x4327bc STUR X8, [X29, #384] |
0x4327c0 CBNZ X21, 4326cc |
0x4327c4 B 4326dc |
0x4327c8 ORR X8, XZR, XZR |
0x4327cc ADD X0, X8, #1 |
0x4327d0 MOVZ W1, #8 |
0x4327d4 BL 4ae430 |
0x4327d8 LDR X8, [SP, #632] |
0x4327dc STUR X0, [X29, #368] |
0x4327e0 MOVZ W1, #8 |
0x4327e4 ADD X0, X8, #1 |
0x4327e8 BL 4ae430 |
0x4327ec STUR X0, [X29, #344] |
0x4327f0 LDR X0, [SP, #624] |
0x4327f4 CBZ X0, 432804 |
0x4327f8 MOVZ W1, #8 |
0x4327fc BL 4ae430 |
0x432800 STUR X0, [X29, #264] |
0x432804 LDUR X0, [X29, #384] |
0x432808 CBZ X0, 432834 |
0x43280c MOVZ W1, #8 |
0x432810 BL 4ae430 |
0x432814 LDUR X8, [X29, #480] |
0x432818 STUR X0, [X29, #288] |
0x43281c CMP X8, #2 |
0x432820 B.LT 432834 |
0x432824 LDUR X0, [X29, #384] |
0x432828 MOVZ W1, #8 |
0x43282c BL 4ae430 |
0x432830 STUR X0, [X29, #280] |
0x432834 LDR X8, [SP, #528] |
0x432838 CMP X8, #1 |
0x43283c B.LE 432890 |
0x432840 LDR X11, [SP, #376] |
0x432844 LDP X8, X9, [X11, #8] |
0x432848 STR X9, [SP, #336] |
0x43284c LDP X9, X10, [X11, #24] |
0x432850 STUR X10, [X29, #312] |
0x432854 LDR X10, [X11, #40] |
0x432858 STP X9, X8, [X29, #832] |
0x43285c LDR X0, [X9, X8,LSL #3] |
0x432860 STR X10, [SP, #416] |
0x432864 LDP X10, X19, [X11, #48] |
0x432868 STR X10, [SP, #328] |
0x43286c CBZ X0, 4328ac |
0x432870 MOVZ W1, #8 |
0x432874 BL 4ae430 |
0x432878 ORR X25, XZR, X0 |
0x43287c LDUR X13, [X29, #328] |
0x432880 STR XZR, [SP, #560] |
0x432884 CMP X13, #1 |
0x432888 B.GE 4328c0 |
0x43288c B 432930 |
0x432890 STR XZR, [SP, #416] |
0x432894 ORR X25, XZR, XZR |
0x432898 LDUR X13, [X29, #328] |
0x43289c STR XZR, [SP, #560] |
0x4328a0 CMP X13, #1 |
0x4328a4 B.GE 4328c0 |
0x4328a8 B 432930 |
0x4328ac ORR X25, XZR, XZR |
0x4328b0 LDUR X13, [X29, #328] |
0x4328b4 STR XZR, [SP, #560] |
0x4328b8 CMP X13, #1 |
0x4328bc B.LT 432930 |
0x4328c0 LDP X11, X8, [X29, #824] |
0x4328c4 LDUR X9, [X29, #504] |
0x4328c8 ORR X10, XZR, XZR |
0x4328cc ORR X12, XZR, XZR |
0x4328d0 B 4328ec |
0x4328d4 HINT #0 |
0x4328d8 HINT #0 |
0x4328dc HINT #0 |
(1734) 0x4328e0 CMP X12, X13 |
(1734) 0x4328e4 STR X12, [SP, #560] |
(1734) 0x4328e8 B.GE 432930 |
(1734) 0x4328ec LDR X14, [X8, X12,LSL #3] |
(1734) 0x4328f0 ADD X12, X12, #1 |
(1734) 0x4328f4 LDR X15, [X8, X12,LSL #3] |
(1734) 0x4328f8 CMP X14, X15 |
(1734) 0x4328fc B.GE 4328e0 |
(1735) 0x432900 LDR X12, [X11, X14,LSL #3] |
(1735) 0x432904 ADD X14, X14, #1 |
(1735) 0x432908 LDR X12, [X9, X12,LSL #3] |
(1735) 0x43290c STR X12, [X25, X10,LSL #3] |
(1735) 0x432910 ADD X10, X10, #1 |
(1735) 0x432914 LDR X12, [SP, #560] |
(1735) 0x432918 ADD X12, X12, #1 |
(1735) 0x43291c LDR X13, [X8, X12,LSL #3] |
(1735) 0x432920 CMP X14, X13 |
(1735) 0x432924 B.LT 432900 |
(1734) 0x432928 LDUR X13, [X29, #328] |
(1734) 0x43292c B 4328e0 |
0x432930 LDR X8, [SP, #528] |
0x432934 CMP X8, #1 |
0x432938 B.LE 432954 |
0x43293c LDUR X3, [X29, #288] |
0x432940 LDR X1, [SP, #376] |
0x432944 ORR X2, XZR, X25 |
0x432948 MOVZ W0, #11 |
0x43294c BL 485620 |
0x432950 BL 485a00 |
0x432954 LDUR X8, [X29, #480] |
0x432958 CMP X8, #2 |
0x43295c B.LT 4329f8 |
0x432960 LDUR X13, [X29, #328] |
0x432964 STR XZR, [SP, #560] |
0x432968 CMP X13, #1 |
0x43296c B.LT 4329d4 |
0x432970 LDP X11, X8, [X29, #824] |
0x432974 LDUR X9, [X29, #472] |
0x432978 ORR X10, XZR, XZR |
0x43297c ORR X12, XZR, XZR |
0x432980 B 432990 |
(1732) 0x432984 CMP X12, X13 |
(1732) 0x432988 STR X12, [SP, #560] |
(1732) 0x43298c B.GE 4329d4 |
(1732) 0x432990 LDR X14, [X8, X12,LSL #3] |
(1732) 0x432994 ADD X12, X12, #1 |
(1732) 0x432998 LDR X15, [X8, X12,LSL #3] |
(1732) 0x43299c CMP X14, X15 |
(1732) 0x4329a0 B.GE 432984 |
(1733) 0x4329a4 LDR X12, [X11, X14,LSL #3] |
(1733) 0x4329a8 ADD X14, X14, #1 |
(1733) 0x4329ac LDR X12, [X9, X12,LSL #3] |
(1733) 0x4329b0 STR X12, [X25, X10,LSL #3] |
(1733) 0x4329b4 ADD X10, X10, #1 |
(1733) 0x4329b8 LDR X12, [SP, #560] |
(1733) 0x4329bc ADD X12, X12, #1 |
(1733) 0x4329c0 LDR X13, [X8, X12,LSL #3] |
(1733) 0x4329c4 CMP X14, X13 |
(1733) 0x4329c8 B.LT 4329a4 |
(1732) 0x4329cc LDUR X13, [X29, #328] |
(1732) 0x4329d0 B 432984 |
0x4329d4 LDR X8, [SP, #528] |
0x4329d8 CMP X8, #1 |
0x4329dc B.LE 4329f8 |
0x4329e0 LDUR X3, [X29, #280] |
0x4329e4 LDR X1, [SP, #376] |
0x4329e8 ORR X2, XZR, X25 |
0x4329ec MOVZ W0, #11 |
0x4329f0 BL 485620 |
0x4329f4 BL 485a00 |
0x4329f8 ADRP X0, |
0x4329fc ADD X0, X0, #336 |
0x432a00 ADRP X2, 435a00 |
0x432a04 ADD X2, X2, #1104 |
0x432a08 STR X19, [SP, #424] |
0x432a0c STR XZR, [SP, #616] |
0x432a10 STR XZR, [SP, #600] |
0x432a14 SUB X3, X29, #128 |
0x432a18 SUB X4, X29, #224 |
0x432a1c ADD X5, SP, #616 |
0x432a20 ADD X6, SP, #600 |
0x432a24 MOVZ W1, #4 |
0x432a28 BL 40fa00 |
0x432a2c LDUR X0, [X29, #384] |
0x432a30 CBZ X0, 432a74 |
0x432a34 MOVZ W1, #8 |
0x432a38 BL 4ae430 |
0x432a3c STR X0, [SP, #576] |
0x432a40 LDUR X0, [X29, #384] |
0x432a44 MOVZ W1, #8 |
0x432a48 BL 4ae430 |
0x432a4c STR X0, [SP, #688] |
0x432a50 LDUR X0, [X29, #384] |
0x432a54 MOVZ W1, #8 |
0x432a58 BL 4ae430 |
0x432a5c ORR X19, XZR, X0 |
0x432a60 LDR X0, [SP, #616] |
0x432a64 MOVZ W1, #8 |
0x432a68 BL 4ae430 |
0x432a6c ORR X26, XZR, X0 |
0x432a70 B 432a7c |
0x432a74 ORR X19, XZR, XZR |
0x432a78 ORR X26, XZR, XZR |
0x432a7c LDUR X12, [X29, #368] |
0x432a80 SUB X23, X28, #1 |
0x432a84 STR XZR, [X12] |
0x432a88 LDUR X13, [X29, #344] |
0x432a8c STR XZR, [X13] |
0x432a90 STR XZR, [SP, #560] |
0x432a94 LDR X8, [SP, #632] |
0x432a98 CMP X8, #1 |
0x432a9c B.LT 432b74 |
0x432aa0 LDUR X8, [X29, #504] |
0x432aa4 LDR X9, [SP, #760] |
0x432aa8 LDR X10, [SP, #584] |
0x432aac ORR X11, XZR, XZR |
0x432ab0 ORR X0, XZR, XZR |
0x432ab4 ORR X18, XZR, X23 |
0x432ab8 LDR X15, [SP, #592] |
0x432abc LDUR X17, [X29, #264] |
0x432ac0 ADD X12, X12, #8 |
0x432ac4 ADD X13, X13, #8 |
0x432ac8 MOVN X14, #0 |
0x432acc MOVZ W16, #1 |
0x432ad0 B 432b20 |
0x432ad4 HINT #0 |
0x432ad8 HINT #0 |
0x432adc HINT #0 |
(1729) 0x432ae0 STR X0, [X9, X18,LSL #3] |
(1729) 0x432ae4 SUB X18, X18, #1 |
(1729) 0x432ae8 LDR X0, [SP, #560] |
(1730) 0x432aec STR XZR, [X12, X0,LSL #3] |
(1730) 0x432af0 LDR X0, [SP, #560] |
(1730) 0x432af4 STR XZR, [X13, X0,LSL #3] |
(1730) 0x432af8 LDR X0, [SP, #560] |
(1730) 0x432afc STR X14, [X10, X0,LSL #3] |
(1730) 0x432b00 LDR X0, [SP, #560] |
(1730) 0x432b04 STR X14, [X15, X0,LSL #3] |
(1730) 0x432b08 LDR X0, [SP, #560] |
(1730) 0x432b0c LDR X1, [SP, #632] |
(1730) 0x432b10 ADD X0, X0, #1 |
(1730) 0x432b14 CMP X0, X1 |
(1730) 0x432b18 STR X0, [SP, #560] |
(1730) 0x432b1c B.GE 432b74 |
(1731) 0x432b20 LDR X1, [X8, X0,LSL #3] |
(1731) 0x432b24 CMN X1, #1 |
(1731) 0x432b28 B.EQ 432ae0 |
(1731) 0x432b2c CMP X1, #1 |
(1731) 0x432b30 B.NE 432aec |
(1731) 0x432b34 STR X11, [X15, X0,LSL #3] |
(1731) 0x432b38 LDR X0, [SP, #560] |
(1731) 0x432b3c STR X0, [X17, X11,LSL #3] |
(1731) 0x432b40 ADD X11, X11, #1 |
(1731) 0x432b44 LDR X0, [SP, #560] |
(1731) 0x432b48 STR XZR, [X10, X0,LSL #3] |
(1731) 0x432b4c LDR X0, [SP, #560] |
(1731) 0x432b50 STR X16, [X12, X0,LSL #3] |
(1731) 0x432b54 LDR X0, [SP, #560] |
(1731) 0x432b58 STR XZR, [X13, X0,LSL #3] |
(1731) 0x432b5c LDR X0, [SP, #560] |
(1731) 0x432b60 LDR X1, [SP, #632] |
(1731) 0x432b64 ADD X0, X0, #1 |
(1731) 0x432b68 CMP X0, X1 |
(1731) 0x432b6c STR X0, [SP, #560] |
(1731) 0x432b70 B.LT 432b20 |
0x432b74 LDUR X13, [X29, #328] |
0x432b78 STR XZR, [SP, #560] |
0x432b7c CMP X13, #1 |
0x432b80 B.LT 432bfc |
0x432b84 LDP X11, X9, [X29, #824] |
0x432b88 LDR X10, [SP, #592] |
0x432b8c ORR X8, XZR, XZR |
0x432b90 ORR X12, XZR, XZR |
0x432b94 B 432bac |
0x432b98 HINT #0 |
0x432b9c HINT #0 |
(1727) 0x432ba0 CMP X12, X13 |
(1727) 0x432ba4 STR X12, [SP, #560] |
(1727) 0x432ba8 B.GE 432bfc |
(1727) 0x432bac LDR X14, [X9, X12,LSL #3] |
(1727) 0x432bb0 ADD X12, X12, #1 |
(1727) 0x432bb4 LDR X15, [X9, X12,LSL #3] |
(1727) 0x432bb8 CMP X14, X15 |
(1727) 0x432bbc B.GE 432ba0 |
(1728) 0x432bc0 LDR X12, [X11, X14,LSL #3] |
(1728) 0x432bc4 ADD X14, X14, #1 |
(1728) 0x432bc8 LDR X12, [X10, X12,LSL #3] |
(1728) 0x432bcc CMP X12, #0 |
(1728) 0x432bd0 CSEL X13, XZR, X27, #11 |
(1728) 0x432bd4 ADD X12, X13, X12 |
(1728) 0x432bd8 STR X12, [X25, X8,LSL #3] |
(1728) 0x432bdc ADD X8, X8, #1 |
(1728) 0x432be0 LDR X12, [SP, #560] |
(1728) 0x432be4 ADD X12, X12, #1 |
(1728) 0x432be8 LDR X13, [X9, X12,LSL #3] |
(1728) 0x432bec CMP X14, X13 |
(1728) 0x432bf0 B.LT 432bc0 |
(1727) 0x432bf4 LDUR X13, [X29, #328] |
(1727) 0x432bf8 B 432ba0 |
0x432bfc LDR X8, [SP, #528] |
0x432c00 CMP X8, #1 |
0x432c04 B.LE 432c20 |
0x432c08 LDR X1, [SP, #376] |
0x432c0c ORR X2, XZR, X25 |
0x432c10 ORR X3, XZR, X19 |
0x432c14 MOVZ W0, #11 |
0x432c18 BL 485620 |
0x432c1c BL 485a00 |
0x432c20 LDR X8, [SP, #416] |
0x432c24 MOVZ W1, #8 |
0x432c28 ADD X0, X8, #1 |
0x432c2c STR X0, [SP, #344] |
0x432c30 BL 4ae430 |
0x432c34 ORR X22, XZR, X0 |
0x432c38 LDR X0, [SP, #616] |
0x432c3c CBZ X0, 432c4c |
0x432c40 MOVZ W1, #8 |
0x432c44 BL 4ae430 |
0x432c48 STUR X0, [X29, #256] |
0x432c4c LDR X8, [SP, #416] |
0x432c50 STR XZR, [X22] |
0x432c54 CMP X8, #1 |
0x432c58 B.LT 432d1c |
0x432c5c LDUR X9, [X29, #288] |
0x432c60 ORR X8, XZR, XZR |
0x432c64 ORR X10, XZR, XZR |
0x432c68 MOVN X11, #0 |
0x432c6c B 432c90 |
0x432c70 HINT #0 |
0x432c74 HINT #0 |
0x432c78 HINT #0 |
0x432c7c HINT #0 |
(1724) 0x432c80 LDR X12, [SP, #416] |
(1724) 0x432c84 STR X10, [X22, X8,LSL #3] |
(1724) 0x432c88 CMP X8, X12 |
(1724) 0x432c8c B.EQ 432d1c |
(1724) 0x432c90 LDR X12, [SP, #424] |
(1724) 0x432c94 LDR X15, [X12, X8,LSL #3] |
(1724) 0x432c98 ADD X8, X8, #1 |
(1724) 0x432c9c STR X15, [SP, #560] |
(1724) 0x432ca0 LDR X12, [X12, X8,LSL #3] |
(1724) 0x432ca4 CMP X15, X12 |
(1724) 0x432ca8 B.GE 432c80 |
(1726) 0x432cac LDR X12, [SP, #576] |
(1726) 0x432cb0 LDR X13, [SP, #688] |
(1726) 0x432cb4 LDUR X14, [X29, #256] |
(1726) 0x432cb8 B 432ce8 |
0x432cbc HINT #0 |
(1725) 0x432cc0 STR X11, [X12, X15,LSL #3] |
(1725) 0x432cc4 LDR X15, [SP, #560] |
(1725) 0x432cc8 STR X11, [X13, X15,LSL #3] |
(1726) 0x432ccc LDR X15, [SP, #560] |
(1726) 0x432cd0 LDR X16, [SP, #424] |
(1726) 0x432cd4 ADD X15, X15, #1 |
(1726) 0x432cd8 STR X15, [SP, #560] |
(1726) 0x432cdc LDR X16, [X16, X8,LSL #3] |
(1726) 0x432ce0 CMP X15, X16 |
(1726) 0x432ce4 B.GE 432c80 |
(1726) 0x432ce8 LDR X16, [X9, X15,LSL #3] |
(1726) 0x432cec CMP X16, #1 |
(1726) 0x432cf0 B.NE 432cc0 |
(1726) 0x432cf4 STR X10, [X13, X15,LSL #3] |
(1726) 0x432cf8 LDR X15, [SP, #560] |
(1726) 0x432cfc STR X15, [X14, X10,LSL #3] |
(1726) 0x432d00 LDR X15, [SP, #560] |
(1726) 0x432d04 LDR X15, [X19, X15,LSL #3] |
(1726) 0x432d08 STR X15, [X26, X10,LSL #3] |
(1726) 0x432d0c ADD X10, X10, #1 |
(1726) 0x432d10 LDR X15, [SP, #560] |
(1726) 0x432d14 STR XZR, [X12, X15,LSL #3] |
(1726) 0x432d18 B 432ccc |
0x432d1c ORR X0, XZR, X19 |
0x432d20 BL 4ae530 |
0x432d24 LDR X8, [X29, #104] |
0x432d28 CBZ X8, 432db4 |
0x432d2c ORR X0, XZR, X21 |
0x432d30 MOVZ W1, #8 |
0x432d34 BL 4ae430 |
0x432d38 CMP X21, #1 |
0x432d3c STR X0, [SP, #680] |
0x432d40 STR XZR, [SP, #560] |
0x432d44 B.LT 432db4 |
0x432d48 ORR X8, XZR, XZR |
0x432d4c ORR X9, XZR, XZR |
0x432d50 B 432d8c |
0x432d54 HINT #0 |
0x432d58 HINT #0 |
0x432d5c HINT #0 |
(1722) 0x432d60 LDR X10, [X24, X9,LSL #3] |
(1722) 0x432d64 LDR X11, [X20, X8,LSL #3] |
(1722) 0x432d68 CMP X10, X11 |
(1722) 0x432d6c CSINV X10, X8, XZR, #0 |
(1722) 0x432d70 CSINC X8, X8, X8, #1 |
(1722) 0x432d74 STR X10, [X0, X9,LSL #3] |
(1722) 0x432d78 LDR X9, [SP, #560] |
(1722) 0x432d7c ADD X9, X9, #1 |
(1722) 0x432d80 CMP X9, X21 |
(1722) 0x432d84 STR X9, [SP, #560] |
(1722) 0x432d88 B.GE 432db4 |
(1723) 0x432d8c LDUR X10, [X29, #384] |
(1723) 0x432d90 CMP X8, X10 |
(1723) 0x432d94 B.LT 432d60 |
(1723) 0x432d98 MOVN X10, #0 |
(1723) 0x432d9c STR X10, [X0, X9,LSL #3] |
(1723) 0x432da0 LDR X9, [SP, #560] |
(1723) 0x432da4 ADD X9, X9, #1 |
(1723) 0x432da8 CMP X9, X21 |
(1723) 0x432dac STR X9, [SP, #560] |
(1723) 0x432db0 B.LT 432d8c |
0x432db4 LDR X8, [SP, #752] |
0x432db8 STR X22, [SP, #296] |
0x432dbc ORR X22, XZR, X23 |
0x432dc0 CMP X28, #1 |
0x432dc4 STP XZR, XZR, [X8] |
0x432dc8 STR XZR, [SP, #512] |
0x432dcc LDR X9, [SP, #624] |
0x432dd0 STR X23, [SP, #560] |
0x432dd4 STR X9, [SP, #656] |
0x432dd8 B.LT 432f0c |
0x432ddc LDR X9, [SP, #760] |
0x432de0 LDP X11, X10, [X29, #920] |
0x432de4 LDUR X12, [X29, #504] |
0x432de8 ORR X19, XZR, XZR |
0x432dec ORR X23, XZR, XZR |
0x432df0 ORR X20, XZR, XZR |
0x432df4 LDP X14, X13, [X29, #904] |
0x432df8 LDUR X15, [X29, #288] |
0x432dfc LDR X17, [SP, #584] |
0x432e00 ORR X18, XZR, X22 |
0x432e04 MOVZ W16, #1 |
0x432e08 B 432e20 |
(1719) 0x432e0c LDR X0, [SP, #560] |
(1719) 0x432e10 SUB X18, X0, #1 |
(1719) 0x432e14 CMP X0, X23 |
(1719) 0x432e18 STR X18, [SP, #560] |
(1719) 0x432e1c B.LE 432f18 |
(1719) 0x432e20 LDR X18, [X9, X18,LSL #3] |
(1719) 0x432e24 ADD X0, X18, #1 |
(1719) 0x432e28 LDR X1, [X10, X18,LSL #3] |
(1719) 0x432e2c LDR X3, [X10, X0,LSL #3] |
(1719) 0x432e30 CMP X1, X3 |
(1719) 0x432e34 B.GE 432e80 |
(1719) 0x432e38 LDUR X2, [X29, #368] |
(1719) 0x432e3c LDR X4, [SP, #584] |
(1719) 0x432e40 B 432e50 |
(1721) 0x432e44 ADD X1, X1, #1 |
(1721) 0x432e48 CMP X1, X3 |
(1721) 0x432e4c B.GE 432e80 |
(1721) 0x432e50 LDR X5, [X11, X1,LSL #3] |
(1721) 0x432e54 LDR X5, [X12, X5,LSL #3] |
(1721) 0x432e58 CMP X5, #1 |
(1721) 0x432e5c B.NE 432e44 |
(1721) 0x432e60 LDR X3, [X2, X0,LSL #3] |
(1721) 0x432e64 ADD X20, X20, #1 |
(1721) 0x432e68 ADD X3, X3, #1 |
(1721) 0x432e6c STR X3, [X2, X0,LSL #3] |
(1721) 0x432e70 STR X16, [X4, X18,LSL #3] |
(1721) 0x432e74 LDR X3, [X10, X0,LSL #3] |
(1721) 0x432e78 B 432e44 |
0x432e7c HINT #0 |
(1719) 0x432e80 LDR X1, [X13, X18,LSL #3] |
(1719) 0x432e84 LDR X4, [X13, X0,LSL #3] |
(1719) 0x432e88 CMP X1, X4 |
(1719) 0x432e8c B.GE 432ee0 |
(1719) 0x432e90 LDUR X2, [X29, #344] |
(1719) 0x432e94 LDR X3, [SP, #584] |
(1719) 0x432e98 B 432eac |
0x432e9c HINT #0 |
(1720) 0x432ea0 ADD X1, X1, #1 |
(1720) 0x432ea4 CMP X1, X4 |
(1720) 0x432ea8 B.GE 432ee0 |
(1720) 0x432eac LDR X5, [X14, X1,LSL #3] |
(1720) 0x432eb0 LDR X5, [X15, X5,LSL #3] |
(1720) 0x432eb4 CMP X5, #1 |
(1720) 0x432eb8 B.NE 432ea0 |
(1720) 0x432ebc LDR X4, [X2, X0,LSL #3] |
(1720) 0x432ec0 ADD X19, X19, #1 |
(1720) 0x432ec4 ADD X4, X4, #1 |
(1720) 0x432ec8 STR X4, [X2, X0,LSL #3] |
(1720) 0x432ecc STR X16, [X3, X18,LSL #3] |
(1720) 0x432ed0 LDR X4, [X13, X0,LSL #3] |
(1720) 0x432ed4 B 432ea0 |
0x432ed8 HINT #0 |
0x432edc HINT #0 |
(1719) 0x432ee0 LDR X0, [X17, X18,LSL #3] |
(1719) 0x432ee4 CMP X0, #1 |
(1719) 0x432ee8 B.NE 432e0c |
(1719) 0x432eec LDR X1, [SP, #560] |
(1719) 0x432ef0 LDR X0, [X9, X23,LSL #3] |
(1719) 0x432ef4 ADD X2, X1, #1 |
(1719) 0x432ef8 STR X2, [SP, #560] |
(1719) 0x432efc STR X0, [X9, X1,LSL #3] |
(1719) 0x432f00 STR X18, [X9, X23,LSL #3] |
(1719) 0x432f04 ADD X23, X23, #1 |
(1719) 0x432f08 B 432e0c |
0x432f0c ORR X20, XZR, XZR |
0x432f10 ORR X23, XZR, XZR |
0x432f14 ORR X19, XZR, XZR |
0x432f18 LDUR X13, [X29, #328] |
0x432f1c STR X23, [X8, #16] |
0x432f20 STR XZR, [SP, #560] |
0x432f24 CMP X13, #1 |
0x432f28 B.LT 432f90 |
0x432f2c LDP X11, X8, [X29, #824] |
0x432f30 LDR X9, [SP, #584] |
0x432f34 ORR X10, XZR, XZR |
0x432f38 ORR X12, XZR, XZR |
0x432f3c B 432f4c |
(1717) 0x432f40 CMP X12, X13 |
(1717) 0x432f44 STR X12, [SP, #560] |
(1717) 0x432f48 B.GE 432f90 |
(1717) 0x432f4c LDR X14, [X8, X12,LSL #3] |
(1717) 0x432f50 ADD X12, X12, #1 |
(1717) 0x432f54 LDR X15, [X8, X12,LSL #3] |
(1717) 0x432f58 CMP X14, X15 |
(1717) 0x432f5c B.GE 432f40 |
(1718) 0x432f60 LDR X12, [X11, X14,LSL #3] |
(1718) 0x432f64 ADD X14, X14, #1 |
(1718) 0x432f68 LDR X12, [X9, X12,LSL #3] |
(1718) 0x432f6c STR X12, [X25, X10,LSL #3] |
(1718) 0x432f70 ADD X10, X10, #1 |
(1718) 0x432f74 LDR X12, [SP, #560] |
(1718) 0x432f78 ADD X12, X12, #1 |
(1718) 0x432f7c LDR X13, [X8, X12,LSL #3] |
(1718) 0x432f80 CMP X14, X13 |
(1718) 0x432f84 B.LT 432f60 |
(1717) 0x432f88 LDUR X13, [X29, #328] |
(1717) 0x432f8c B 432f40 |
0x432f90 LDR X8, [SP, #528] |
0x432f94 CMP X8, #1 |
0x432f98 B.LE 432fb4 |
0x432f9c LDR X3, [SP, #576] |
0x432fa0 LDR X1, [SP, #376] |
0x432fa4 ORR X2, XZR, X25 |
0x432fa8 MOVZ W0, #11 |
0x432fac BL 485620 |
0x432fb0 BL 485a00 |
0x432fb4 MOVZ W8, #2 |
0x432fb8 ADRP X3, |
0x432fbc ADRP X4, |
0x432fc0 ADD X0, SP, #544 |
0x432fc4 STR X8, [SP, #648] |
0x432fc8 SUB X8, X28, X23 |
0x432fcc ADD X1, SP, #552 |
0x432fd0 MOVZ W2, #1 |
0x432fd4 STR X8, [SP, #544] |
0x432fd8 LDR X3, [X3, #3928] |
0x432fdc LDR X4, [X4, #3784] |
0x432fe0 LDR X5, [SP, #384] |
0x432fe4 BL 4b0270 |
0x432fe8 LDR X8, [SP, #552] |
0x432fec CBZ X8, 4331f8 |
0x432ff0 LDR X8, [SP, #648] |
0x432ff4 CMP X8, #9 |
0x432ff8 B.GT 4331f8 |
0x432ffc ADRP X21, |
0x433000 ADRP X24, |
0x433004 LDR X21, [X21, #3928] |
0x433008 LDR X24, [X24, #3784] |
(1711) 0x43300c CMP X28, X23 |
(1711) 0x433010 STR X22, [SP, #560] |
(1711) 0x433014 B.LE 433104 |
(1711) 0x433018 LDR X8, [SP, #760] |
(1711) 0x43301c LDP X10, X9, [X29, #920] |
(1711) 0x433020 LDR X11, [SP, #584] |
(1711) 0x433024 ORR X15, XZR, X22 |
(1711) 0x433028 LDP X13, X12, [X29, #904] |
(1711) 0x43302c LDR X14, [SP, #576] |
(1711) 0x433030 B 433074 |
0x433034 HINT #0 |
0x433038 HINT #0 |
0x43303c HINT #0 |
(1714) 0x433040 LDR X17, [X8, X23,LSL #3] |
(1714) 0x433044 ADD X18, X15, #1 |
(1714) 0x433048 STR X18, [SP, #560] |
(1714) 0x43304c STR X17, [X8, X15,LSL #3] |
(1714) 0x433050 STR X16, [X8, X23,LSL #3] |
(1714) 0x433054 ADD X23, X23, #1 |
(1714) 0x433058 LDR X15, [SP, #648] |
(1714) 0x43305c STR X15, [X11, X16,LSL #3] |
(1714) 0x433060 LDR X15, [SP, #560] |
(1714) 0x433064 CMP X15, X23 |
(1714) 0x433068 SUB X15, X15, #1 |
(1714) 0x43306c STR X15, [SP, #560] |
(1714) 0x433070 B.LE 433100 |
(1714) 0x433074 LDR X16, [X8, X15,LSL #3] |
(1714) 0x433078 ADD X17, X16, #1 |
(1714) 0x43307c LDR X1, [X9, X16,LSL #3] |
(1714) 0x433080 LDR X0, [X9, X17,LSL #3] |
(1714) 0x433084 CMP X1, X0 |
(1714) 0x433088 B.GE 4330bc |
(1714) 0x43308c LDR X18, [SP, #648] |
(1714) 0x433090 SUB X0, X0, X1 |
(1714) 0x433094 ADD X1, X10, X1,LSL #3 |
(1714) 0x433098 SUB X18, X18, #1 |
(1714) 0x43309c HINT #0 |
(1716) 0x4330a0 LDR X2, [X1] |
(1716) 0x4330a4 LDR X2, [X11, X2,LSL #3] |
(1716) 0x4330a8 CMP X2, X18 |
(1716) 0x4330ac B.EQ 433040 |
(1716) 0x4330b0 SUBS X0, X0, #1 |
(1716) 0x4330b4 ADD X1, X1, #8 |
(1716) 0x4330b8 B.NE 4330a0 |
(1714) 0x4330bc LDR X0, [X12, X16,LSL #3] |
(1714) 0x4330c0 LDR X18, [X12, X17,LSL #3] |
(1714) 0x4330c4 CMP X0, X18 |
(1714) 0x4330c8 B.GE 433064 |
(1714) 0x4330cc LDR X17, [SP, #648] |
(1714) 0x4330d0 SUB X18, X18, X0 |
(1714) 0x4330d4 ADD X0, X13, X0,LSL #3 |
(1714) 0x4330d8 SUB X17, X17, #1 |
(1714) 0x4330dc HINT #0 |
(1715) 0x4330e0 LDR X1, [X0] |
(1715) 0x4330e4 LDR X1, [X14, X1,LSL #3] |
(1715) 0x4330e8 CMP X1, X17 |
(1715) 0x4330ec B.EQ 433040 |
(1715) 0x4330f0 SUBS X18, X18, #1 |
(1715) 0x4330f4 ADD X0, X0, #8 |
(1715) 0x4330f8 B.NE 4330e0 |
(1714) 0x4330fc B 433064 |
(1711) 0x433100 LDR X8, [SP, #648] |
(1711) 0x433104 LDR X9, [SP, #752] |
(1711) 0x433108 LDR X5, [SP, #384] |
(1711) 0x43310c ADD X8, X8, #1 |
(1711) 0x433110 ORR X3, XZR, X21 |
(1711) 0x433114 ORR X4, XZR, X24 |
(1711) 0x433118 ADD X0, SP, #544 |
(1711) 0x43311c ADD X1, SP, #552 |
(1711) 0x433120 STR X8, [SP, #648] |
(1711) 0x433124 MOVZ W2, #1 |
(1711) 0x433128 STR X23, [X9, X8,LSL #3] |
(1711) 0x43312c SUB X8, X28, X23 |
(1711) 0x433130 STR X8, [SP, #544] |
(1711) 0x433134 BL 4b0270 |
(1711) 0x433138 LDUR X13, [X29, #328] |
(1711) 0x43313c STR XZR, [SP, #560] |
(1711) 0x433140 CMP X13, #1 |
(1711) 0x433144 B.LT 4331c0 |
(1711) 0x433148 LDP X11, X8, [X29, #824] |
(1711) 0x43314c LDR X9, [SP, #584] |
(1711) 0x433150 ORR X10, XZR, XZR |
(1711) 0x433154 ORR X12, XZR, XZR |
(1711) 0x433158 B 43316c |
0x43315c HINT #0 |
(1712) 0x433160 CMP X12, X13 |
(1712) 0x433164 STR X12, [SP, #560] |
(1712) 0x433168 B.GE 4331c0 |
(1712) 0x43316c LDR X14, [X8, X12,LSL #3] |
(1712) 0x433170 ADD X12, X12, #1 |
(1712) 0x433174 LDR X15, [X8, X12,LSL #3] |
(1712) 0x433178 CMP X14, X15 |
(1712) 0x43317c B.GE 433160 |
(1713) 0x433180 LDR X12, [X11, X14,LSL #3] |
(1713) 0x433184 ADD X14, X14, #1 |
(1713) 0x433188 LDR X12, [X9, X12,LSL #3] |
(1713) 0x43318c STR X12, [X25, X10,LSL #3] |
(1713) 0x433190 ADD X10, X10, #1 |
(1713) 0x433194 LDR X12, [SP, #560] |
(1713) 0x433198 ADD X12, X12, #1 |
(1713) 0x43319c LDR X13, [X8, X12,LSL #3] |
(1713) 0x4331a0 CMP X14, X13 |
(1713) 0x4331a4 B.LT 433180 |
(1712) 0x4331a8 LDUR X13, [X29, #328] |
(1712) 0x4331ac B 433160 |
0x4331b0 HINT #0 |
0x4331b4 HINT #0 |
0x4331b8 HINT #0 |
0x4331bc HINT #0 |
(1711) 0x4331c0 LDR X8, [SP, #528] |
(1711) 0x4331c4 CMP X8, #1 |
(1711) 0x4331c8 B.LE 4331e4 |
(1711) 0x4331cc LDR X3, [SP, #576] |
(1711) 0x4331d0 LDR X1, [SP, #376] |
(1711) 0x4331d4 ORR X2, XZR, X25 |
(1711) 0x4331d8 MOVZ W0, #11 |
(1711) 0x4331dc BL 485620 |
(1711) 0x4331e0 BL 485a00 |
(1711) 0x4331e4 LDR X8, [SP, #552] |
(1711) 0x4331e8 CBZ X8, 4331f8 |
(1711) 0x4331ec LDR X8, [SP, #648] |
(1711) 0x4331f0 CMP X8, #10 |
(1711) 0x4331f4 B.LT 43300c |
0x4331f8 ORR X0, XZR, X25 |
0x4331fc BL 4ae530 |
0x433200 LDR X21, [SP, #648] |
0x433204 MOVZ W1, #8 |
0x433208 ORR X0, XZR, X21 |
0x43320c STR X21, [SP, #640] |
0x433210 BL 4ae430 |
0x433214 STR X0, [SP, #728] |
0x433218 ORR X0, XZR, X20 |
0x43321c MOVZ W1, #8 |
0x433220 BL 4ae430 |
0x433224 LDR X8, [SP, #728] |
0x433228 MOVZ W1, #8 |
0x43322c STR X0, [X8, #8] |
0x433230 LDR X0, [SP, #632] |
0x433234 BL 4ae430 |
0x433238 STR X0, [SP, #744] |
0x43323c LDR X0, [SP, #632] |
0x433240 MOVZ W1, #8 |
0x433244 BL 4ae430 |
0x433248 LDR X8, [SP, #528] |
0x43324c STR X0, [SP, #736] |
0x433250 CMP X8, #2 |
0x433254 B.LT 433284 |
0x433258 ORR X0, XZR, X21 |
0x43325c MOVZ W1, #8 |
0x433260 BL 4ae430 |
0x433264 STR X0, [SP, #720] |
0x433268 CBZ X19, 4350ac |
0x43326c ORR X0, XZR, X19 |
0x433270 MOVZ W1, #8 |
0x433274 BL 4ae430 |
0x433278 ORR X8, XZR, X0 |
0x43327c LDR X0, [SP, #720] |
0x433280 B 4350b0 |
0x433284 ORR X30, XZR, XZR |
0x433288 LDR X9, [SP, #752] |
0x43328c LDR X21, [SP, #424] |
0x433290 LDP X1, X8, [X9, #8] |
0x433294 CMP X1, X8 |
0x433298 STR X1, [SP, #560] |
0x43329c B.LT 435104 |
(1671) 0x4332a0 ORR X10, XZR, XZR |
(1671) 0x4332a4 ORR X8, XZR, XZR |
(1671) 0x4332a8 LDR X9, [SP, #656] |
(1671) 0x4332ac STR X30, [SP, #432] |
(1671) 0x4332b0 ADD X9, X9, X10 |
(1671) 0x4332b4 STR X9, [SP, #656] |
(1671) 0x4332b8 LDR X9, [SP, #512] |
(1671) 0x4332bc ADD X8, X9, X8 |
(1671) 0x4332c0 STR X8, [SP, #512] |
(1671) 0x4332c4 LDR X8, [SP, #528] |
(1671) 0x4332c8 CMP X8, #1 |
(1671) 0x4332cc B.LE 433c20 |
(1671) 0x4332d0 MOVZ W0, #1 |
(1671) 0x4332d4 MOVZ W1, #112 |
(1671) 0x4332d8 BL 4ae430 |
(1671) 0x4332dc LDR X19, [SP, #640] |
(1671) 0x4332e0 STR X0, [SP, #392] |
(1671) 0x4332e4 MOVZ W1, #8 |
(1671) 0x4332e8 ORR X0, XZR, X19 |
(1671) 0x4332ec BL 4ae430 |
(1671) 0x4332f0 STR X0, [SP, #400] |
(1671) 0x4332f4 ORR X0, XZR, X19 |
(1671) 0x4332f8 MOVZ W1, #8 |
(1671) 0x4332fc BL 4ae430 |
(1671) 0x433300 STR X0, [SP, #408] |
(1671) 0x433304 ORR X0, XZR, X19 |
(1671) 0x433308 MOVZ W1, #8 |
(1671) 0x43330c BL 4ae430 |
(1671) 0x433310 LDUR X8, [X29, #384] |
(1671) 0x433314 STR X0, [SP, #712] |
(1671) 0x433318 MOVZ W1, #8 |
(1671) 0x43331c ADD X0, X8, #1 |
(1671) 0x433320 BL 4ae430 |
(1671) 0x433324 STR X0, [SP, #696] |
(1671) 0x433328 LDUR X0, [X29, #384] |
(1671) 0x43332c CBZ X0, 43333c |
(1671) 0x433330 MOVZ W1, #8 |
(1671) 0x433334 BL 4ae430 |
(1671) 0x433338 STUR X0, [X29, #304] |
(1671) 0x43333c LDP X8, X9, [X29, #832] |
(1671) 0x433340 LDR X0, [X8, X9,LSL #3] |
(1671) 0x433344 CBZ X0, 433354 |
(1671) 0x433348 MOVZ W1, #8 |
(1671) 0x43334c BL 4ae430 |
(1671) 0x433350 STUR X0, [X29, #296] |
(1671) 0x433354 ADRP X0, |
(1671) 0x433358 ADD X0, X0, #408 |
(1671) 0x43335c ADRP X2, 43535c |
(1671) 0x433360 ADD X2, X2, #1568 |
(1671) 0x433364 SUB X3, X29, #128 |
(1671) 0x433368 ADD X4, SP, #696 |
(1671) 0x43336c MOVZ W1, #2 |
(1671) 0x433370 BL 40fa00 |
(1671) 0x433374 ADRP X0, |
(1671) 0x433378 ADD X0, X0, #480 |
(1671) 0x43337c ADRP X2, 43537c |
(1671) 0x433380 ADD X2, X2, #1824 |
(1671) 0x433384 SUB X3, X29, #192 |
(1671) 0x433388 SUB X4, X29, #184 |
(1671) 0x43338c SUB X5, X29, #216 |
(1671) 0x433390 MOVZ W1, #3 |
(1671) 0x433394 BL 40fa00 |
(1671) 0x433398 LDR X30, [SP, #432] |
(1671) 0x43339c MOVZ W8, #2 |
(1671) 0x4333a0 CMP X19, #3 |
(1671) 0x4333a4 STR X8, [SP, #648] |
(1671) 0x4333a8 B.GE 433c38 |
(1671) 0x4333ac ORR X20, XZR, XZR |
(1671) 0x4333b0 ORR X25, XZR, XZR |
(1671) 0x4333b4 ORR X0, XZR, X25 |
(1671) 0x4333b8 BL 4ae530 |
(1671) 0x4333bc LDUR X0, [X29, #296] |
(1671) 0x4333c0 BL 4ae530 |
(1671) 0x4333c4 ORR X0, XZR, X20 |
(1671) 0x4333c8 STUR XZR, [X29, #296] |
(1671) 0x4333cc BL 4ae530 |
(1671) 0x4333d0 LDR X0, [SP, #296] |
(1671) 0x4333d4 BL 4ae530 |
(1671) 0x4333d8 LDR X0, [SP, #448] |
(1671) 0x4333dc BL 4ae530 |
(1671) 0x4333e0 LDR X0, [SP, #440] |
(1671) 0x4333e4 STR XZR, [SP, #448] |
(1671) 0x4333e8 BL 4ae530 |
(1671) 0x4333ec LDR X0, [SP, #456] |
(1671) 0x4333f0 STR XZR, [SP, #440] |
(1671) 0x4333f4 BL 4ae530 |
(1671) 0x4333f8 LDR X0, [SP, #656] |
(1671) 0x4333fc MOVZ W1, #8 |
(1671) 0x433400 STR XZR, [SP, #456] |
(1671) 0x433404 BL 4ae430 |
(1671) 0x433408 STUR X0, [X29, #360] |
(1671) 0x43340c LDR X0, [SP, #656] |
(1671) 0x433410 MOVZ W1, #8 |
(1671) 0x433414 BL 4ae430 |
(1671) 0x433418 STUR X0, [X29, #376] |
(1671) 0x43341c LDR X0, [SP, #512] |
(1671) 0x433420 CBZ X0, 433440 |
(1671) 0x433424 MOVZ W1, #8 |
(1671) 0x433428 BL 4ae430 |
(1671) 0x43342c STUR X0, [X29, #336] |
(1671) 0x433430 LDR X0, [SP, #512] |
(1671) 0x433434 MOVZ W1, #8 |
(1671) 0x433438 BL 4ae430 |
(1671) 0x43343c STUR X0, [X29, #352] |
(1671) 0x433440 LDR X8, [SP, #632] |
(1671) 0x433444 LDR X25, [X29, #96] |
(1671) 0x433448 STR XZR, [SP, #560] |
(1671) 0x43344c CMP X8, #1 |
(1671) 0x433450 B.LT 4334a4 |
(1671) 0x433454 LDUR X8, [X29, #368] |
(1671) 0x433458 LDUR X9, [X29, #344] |
(1671) 0x43345c ORR X12, XZR, XZR |
(1671) 0x433460 ADD X10, X8, #8 |
(1671) 0x433464 ADD X11, X9, #8 |
(1697) 0x433468 LDR X13, [X8, X12,LSL #3] |
(1697) 0x43346c LDR X14, [X10, X12,LSL #3] |
(1697) 0x433470 ADD X13, X14, X13 |
(1697) 0x433474 STR X13, [X10, X12,LSL #3] |
(1697) 0x433478 LDR X12, [SP, #560] |
(1697) 0x43347c LDR X13, [X9, X12,LSL #3] |
(1697) 0x433480 LDR X14, [X11, X12,LSL #3] |
(1697) 0x433484 ADD X13, X14, X13 |
(1697) 0x433488 STR X13, [X11, X12,LSL #3] |
(1697) 0x43348c LDR X12, [SP, #560] |
(1697) 0x433490 LDR X13, [SP, #632] |
(1697) 0x433494 ADD X12, X12, #1 |
(1697) 0x433498 CMP X12, X13 |
(1697) 0x43349c STR X12, [SP, #560] |
(1697) 0x4334a0 B.LT 433468 |
(1671) 0x4334a4 SUB X21, X29, #136 |
(1671) 0x4334a8 ADRP X0, |
(1671) 0x4334ac ADD X0, X0, #744 |
(1671) 0x4334b0 ADRP X2, 4364b0 |
(1671) 0x4334b4 ADD X2, X2, #1056 |
(1671) 0x4334b8 STR X21, [SP] |
(1671) 0x4334bc ADD X3, SP, #624 |
(1671) 0x4334c0 SUB X4, X29, #248 |
(1671) 0x4334c4 SUB X5, X29, #152 |
(1671) 0x4334c8 SUB X6, X29, #144 |
(1671) 0x4334cc ADD X7, SP, #592 |
(1671) 0x4334d0 MOVZ W1, #6 |
(1671) 0x4334d4 SUB X20, X29, #248 |
(1671) 0x4334d8 SUB X22, X29, #152 |
(1671) 0x4334dc SUB X19, X29, #144 |
(1671) 0x4334e0 ADD X24, SP, #592 |
(1671) 0x4334e4 BL 40fa00 |
(1671) 0x4334e8 LDR X8, [SP, #752] |
(1671) 0x4334ec LDP X8, X9, [X8, #8] |
(1671) 0x4334f0 SUB X8, X9, X8 |
(1671) 0x4334f4 SUB X9, X29, #176 |
(1671) 0x4334f8 STR X8, [SP, #464] |
(1671) 0x4334fc ADD X8, SP, #688 |
(1671) 0x433500 CBZ X25, 43448c |
(1671) 0x433504 STP X9, X8, [SP, #200] |
(1671) 0x433508 SUB X8, X29, #160 |
(1671) 0x43350c SUB X10, X29, #72 |
(1671) 0x433510 SUB X11, X29, #232 |
(1671) 0x433514 SUB X9, X29, #88 |
(1671) 0x433518 STP X21, X22, [SP, #80] |
(1671) 0x43351c STP X10, X8, [SP, #184] |
(1671) 0x433520 SUB X8, X29, #224 |
(1671) 0x433524 STR X9, [SP, #160] |
(1671) 0x433528 ADD X9, X29, #104 |
(1671) 0x43352c SUB X10, X29, #32 |
(1671) 0x433530 ADD X12, SP, #728 |
(1671) 0x433534 ADRP X0, |
(1671) 0x433538 ADD X0, X0, #768 |
(1671) 0x43353c STP X12, X20, [SP, #16] |
(1671) 0x433540 STP X8, X11, [SP, #168] |
(1671) 0x433544 ADD X8, SP, #680 |
(1671) 0x433548 SUB X11, X29, #56 |
(1671) 0x43354c ADRP X2, 43654c |
(1671) 0x433550 ADD X2, X2, #1424 |
(1671) 0x433554 STP X9, X8, [SP, #144] |
(1671) 0x433558 SUB X8, X29, #80 |
(1671) 0x43355c SUB X9, X29, #256 |
(1671) 0x433560 STP X9, X8, [SP, #128] |
(1671) 0x433564 ADD X8, SP, #720 |
(1671) 0x433568 SUB X9, X29, #168 |
(1671) 0x43356c ADD X3, SP, #632 |
(1671) 0x433570 SUB X4, X29, #128 |
(1671) 0x433574 STP X9, X8, [SP, #112] |
(1671) 0x433578 ADD X8, SP, #736 |
(1671) 0x43357c SUB X9, X29, #40 |
(1671) 0x433580 ADD X5, SP, #752 |
(1671) 0x433584 ADD X6, SP, #464 |
(1671) 0x433588 STP X24, X8, [SP, #96] |
(1671) 0x43358c SUB X8, X29, #48 |
(1671) 0x433590 ADD X7, SP, #760 |
(1671) 0x433594 MOVZ W1, #32 |
(1671) 0x433598 STP X9, X8, [SP, #64] |
(1671) 0x43359c SUB X8, X29, #8 |
(1671) 0x4335a0 SUB X9, X29, #64 |
(1671) 0x4335a4 STP X8, X10, [SP, #48] |
(1671) 0x4335a8 ADD X8, SP, #744 |
(1671) 0x4335ac STP X11, X9, [SP, #32] |
(1671) 0x4335b0 STP X8, X19, [SP] |
(1671) 0x4335b4 BL 40fa00 |
(1671) 0x4335b8 LDR X8, [SP, #624] |
(1671) 0x4335bc CBZ X8, 4335cc |
(1671) 0x4335c0 LDUR X0, [X29, #264] |
(1671) 0x4335c4 BL 4ae530 |
(1671) 0x4335c8 STUR XZR, [X29, #264] |
(1671) 0x4335cc LDUR X0, [X29, #256] |
(1671) 0x4335d0 BL 4ae530 |
(1671) 0x4335d4 LDR X8, [SP, #728] |
(1671) 0x4335d8 STUR XZR, [X29, #256] |
(1671) 0x4335dc LDR X0, [X8, #8] |
(1671) 0x4335e0 BL 4ae530 |
(1671) 0x4335e4 LDR X8, [SP, #728] |
(1671) 0x4335e8 STR XZR, [X8, #8] |
(1671) 0x4335ec LDR X8, [SP, #528] |
(1671) 0x4335f0 CMP X8, #2 |
(1671) 0x4335f4 B.LT 43360c |
(1671) 0x4335f8 LDR X8, [SP, #720] |
(1671) 0x4335fc LDR X0, [X8, #8] |
(1671) 0x433600 BL 4ae530 |
(1671) 0x433604 LDR X8, [SP, #720] |
(1671) 0x433608 STR XZR, [X8, #8] |
(1671) 0x43360c LDR X24, [SP, #640] |
(1671) 0x433610 MOVZ W8, #2 |
(1671) 0x433614 STR X8, [SP, #648] |
(1671) 0x433618 CMP X24, #2 |
(1671) 0x43361c B.LE 434bc8 |
(1671) 0x433620 RDVL X9, #1 |
(1671) 0x433624 ORR X22, XZR, XZR |
(1671) 0x433628 MOVZ W8, #2 |
(1671) 0x43362c MOVZ W26, #16 |
(1671) 0x433630 SUB X21, X29, #232 |
(1671) 0x433634 STP XZR, X24, [SP, #368] |
(1671) 0x433638 ORR X19, XZR, XZR |
(1671) 0x43363c CNTW X25, ALL |
(1671) 0x433640 UBFM X27, X9, #4, #63 |
(1671) 0x433644 PTRUE P0.D, ALL |
(1671) 0x433648 B 433664 |
(1688) 0x43364c LDR X9, [SP, #376] |
(1688) 0x433650 PTRUE P0.D, ALL |
(1688) 0x433654 ADD X8, X8, #1 |
(1688) 0x433658 STR X8, [SP, #648] |
(1688) 0x43365c CMP X8, X9 |
(1688) 0x433660 B.GE 434bc0 |
(1688) 0x433664 LDR X9, [SP, #528] |
(1688) 0x433668 CMP X9, #2 |
(1688) 0x43366c B.LT 433a64 |
(1688) 0x433670 LDR X9, [SP, #400] |
(1688) 0x433674 LDUR X23, [X29, #328] |
(1688) 0x433678 LDR X8, [X9, X8,LSL #3] |
(1688) 0x43367c LDR X9, [SP, #368] |
(1688) 0x433680 LDR X8, [X8, X23,LSL #3] |
(1688) 0x433684 CMP X8, X9 |
(1688) 0x433688 STR X8, [SP, #504] |
(1688) 0x43368c B.LE 4336b4 |
(1688) 0x433690 ORR X0, XZR, X19 |
(1688) 0x433694 BL 4ae530 |
(1688) 0x433698 LDR X0, [SP, #504] |
(1688) 0x43369c MOVZ W1, #8 |
(1688) 0x4336a0 BL 4ae430 |
(1688) 0x4336a4 LDR X8, [SP, #504] |
(1688) 0x4336a8 LDUR X23, [X29, #328] |
(1688) 0x4336ac PTRUE P0.D, ALL |
(1688) 0x4336b0 ORR X19, XZR, X0 |
(1688) 0x4336b4 STP X22, X8, [SP, #360] |
(1688) 0x4336b8 CMP X23, #1 |
(1688) 0x4336bc STR XZR, [SP, #560] |
(1688) 0x4336c0 B.LT 4339c4 |
(1688) 0x4336c4 LDP X11, X10, [X29, #824] |
(1688) 0x4336c8 LDR X8, [SP, #648] |
(1688) 0x4336cc LDR X12, [SP, #584] |
(1688) 0x4336d0 ORR X4, XZR, XZR |
(1688) 0x4336d4 ORR X9, XZR, XZR |
(1688) 0x4336d8 ADD X14, X19, #16 |
(1688) 0x4336dc SUB X13, X8, #1 |
(1688) 0x4336e0 STR X10, [SP, #424] |
(1688) 0x4336e4 B 4336f8 |
(1689) 0x4336e8 LDR X10, [SP, #424] |
(1689) 0x4336ec CMP X9, X23 |
(1689) 0x4336f0 STR X9, [SP, #560] |
(1689) 0x4336f4 B.EQ 4339c4 |
(1689) 0x4336f8 LDR X15, [X10, X9,LSL #3] |
(1689) 0x4336fc ADD X9, X9, #1 |
(1689) 0x433700 LDR X16, [X10, X9,LSL #3] |
(1689) 0x433704 CMP X15, X16 |
(1689) 0x433708 B.GE 4336ec |
(1689) 0x43370c LDP X17, X18, [X29, #880] |
(1689) 0x433710 LDP X0, X1, [X29, #856] |
(1689) 0x433714 ADD X2, X18, #16 |
(1689) 0x433718 ADD X3, X1, #16 |
(1689) 0x43371c B 433730 |
(1690) 0x433720 ORR X4, XZR, X6 |
(1690) 0x433724 ADD X15, X15, #1 |
(1690) 0x433728 CMP X15, X16 |
(1690) 0x43372c B.EQ 4336e8 |
(1690) 0x433730 LDR X5, [X11, X15,LSL #3] |
(1690) 0x433734 LDR X8, [X12, X5,LSL #3] |
(1690) 0x433738 CMP X8, X13 |
(1690) 0x43373c B.NE 433724 |
(1690) 0x433740 ADD X7, X5, #1 |
(1690) 0x433744 LDR X28, [X17, X5,LSL #3] |
(1690) 0x433748 LDR X22, [X17, X7,LSL #3] |
(1690) 0x43374c SUBS X8, X22, X28 |
(1690) 0x433750 B.LE 433820 |
(1690) 0x433754 CMP X25, #16 |
(1690) 0x433758 CSEL X10, X25, X26, #8 |
(1690) 0x43375c CMP X8, X10 |
(1690) 0x433760 B.CC 433778 |
(1690) 0x433764 ADD X10, X19, X4,LSL #3 |
(1690) 0x433768 ADD X6, X18, X28,LSL #3 |
(1690) 0x43376c SUB X10, X10, X6 |
(1690) 0x433770 CMP X10, X27,LSL #5 |
(1690) 0x433774 B.CS 4338f8 |
(1690) 0x433778 ORR X6, XZR, X4 |
(1690) 0x43377c ORR X21, XZR, X28 |
(1690) 0x433780 SUB W8, W22, W21 |
(1690) 0x433784 ORR X4, XZR, X21 |
(1690) 0x433788 ANDS X20, X8, #4160 |
(1690) 0x43378c B.EQ 4337b8 |
(1690) 0x433790 HINT #0 |
(1690) 0x433794 HINT #0 |
(1690) 0x433798 HINT #0 |
(1690) 0x43379c HINT #0 |
(1695) 0x4337a0 LDR D0, [X18, X4,LSL #3] |
(1695) 0x4337a4 ADD X4, X4, #1 |
(1695) 0x4337a8 SUBS X20, X20, #1 |
(1695) 0x4337ac STR D0, [X19, X6,LSL #3] |
(1695) 0x4337b0 ADD X6, X6, #1 |
(1695) 0x4337b4 B.NE 4337a0 |
(1690) 0x4337b8 ORN X8, XZR, X21 |
(1690) 0x4337bc ADD X8, X22, X8 |
(1690) 0x4337c0 CMP X8, #3 |
(1690) 0x4337c4 B.CC 433824 |
(1690) 0x4337c8 SUB X22, X22, X4 |
(1690) 0x4337cc ADD X4, X2, X4,LSL #3 |
(1690) 0x4337d0 ADD X20, X14, X6,LSL #3 |
(1690) 0x4337d4 HINT #0 |
(1690) 0x4337d8 HINT #0 |
(1690) 0x4337dc HINT #0 |
(1694) 0x4337e0 LDUR D0, [X4, #496] |
(1694) 0x4337e4 ADD X6, X6, #4 |
(1694) 0x4337e8 SUBS X22, X22, #4 |
(1694) 0x4337ec STUR D0, [X20, #496] |
(1694) 0x4337f0 LDUR D0, [X4, #504] |
(1694) 0x4337f4 STUR D0, [X20, #504] |
(1694) 0x4337f8 LDR D0, [X4] |
(1694) 0x4337fc STR D0, [X20] |
(1694) 0x433800 LDR D0, [X4, #8] |
(1694) 0x433804 ADD X4, X4, #32 |
(1694) 0x433808 STR D0, [X20, #8] |
(1694) 0x43380c ADD X20, X20, #32 |
(1694) 0x433810 B.NE 4337e0 |
(1690) 0x433814 B 433824 |
0x433818 HINT #0 |
0x43381c HINT #0 |
(1690) 0x433820 ORR X6, XZR, X4 |
(1690) 0x433824 LDR X21, [X0, X5,LSL #3] |
(1690) 0x433828 LDR X5, [X0, X7,LSL #3] |
(1690) 0x43382c SUBS X8, X5, X21 |
(1690) 0x433830 B.LE 433720 |
(1690) 0x433834 CMP X25, #16 |
(1690) 0x433838 CSEL X10, X25, X26, #8 |
(1690) 0x43383c CMP X8, X10 |
(1690) 0x433840 B.CC 433858 |
(1690) 0x433844 ADD X10, X19, X6,LSL #3 |
(1690) 0x433848 ADD X4, X1, X21,LSL #3 |
(1690) 0x43384c SUB X10, X10, X4 |
(1690) 0x433850 CMP X10, X27,LSL #5 |
(1690) 0x433854 B.CS 433964 |
(1690) 0x433858 ORR X4, XZR, X6 |
(1690) 0x43385c ORR X7, XZR, X21 |
(1690) 0x433860 SUB W8, W5, W7 |
(1690) 0x433864 ORR X6, XZR, X7 |
(1690) 0x433868 ANDS X20, X8, #4160 |
(1690) 0x43386c B.EQ 433898 |
(1690) 0x433870 HINT #0 |
(1690) 0x433874 HINT #0 |
(1690) 0x433878 HINT #0 |
(1690) 0x43387c HINT #0 |
(1692) 0x433880 LDR D0, [X1, X6,LSL #3] |
(1692) 0x433884 ADD X6, X6, #1 |
(1692) 0x433888 SUBS X20, X20, #1 |
(1692) 0x43388c STR D0, [X19, X4,LSL #3] |
(1692) 0x433890 ADD X4, X4, #1 |
(1692) 0x433894 B.NE 433880 |
(1690) 0x433898 ORN X8, XZR, X7 |
(1690) 0x43389c ADD X8, X5, X8 |
(1690) 0x4338a0 CMP X8, #3 |
(1690) 0x4338a4 B.CC 433724 |
(1690) 0x4338a8 SUB X5, X5, X6 |
(1690) 0x4338ac ADD X6, X3, X6,LSL #3 |
(1690) 0x4338b0 ADD X7, X14, X4,LSL #3 |
(1690) 0x4338b4 HINT #0 |
(1690) 0x4338b8 HINT #0 |
(1690) 0x4338bc HINT #0 |
(1691) 0x4338c0 LDUR D0, [X6, #496] |
(1691) 0x4338c4 ADD X4, X4, #4 |
(1691) 0x4338c8 SUBS X5, X5, #4 |
(1691) 0x4338cc STUR D0, [X7, #496] |
(1691) 0x4338d0 LDUR D0, [X6, #504] |
(1691) 0x4338d4 STUR D0, [X7, #504] |
(1691) 0x4338d8 LDR D0, [X6] |
(1691) 0x4338dc STR D0, [X7] |
(1691) 0x4338e0 LDR D0, [X6, #8] |
(1691) 0x4338e4 ADD X6, X6, #32 |
(1691) 0x4338e8 STR D0, [X7, #8] |
(1691) 0x4338ec ADD X7, X7, #32 |
(1691) 0x4338f0 B.NE 4338c0 |
(1690) 0x4338f4 B 433724 |
(1690) 0x4338f8 UDIV X10, X8, X25 |
(1690) 0x4338fc ORR X24, XZR, XZR |
(1690) 0x433900 MADD X20, X10, X25, XZR |
(1690) 0x433904 UBFM X10, X28, #61, #60 |
(1690) 0x433908 SUB X30, X8, X20 |
(1690) 0x43390c UBFM X8, X4, #61, #60 |
(1690) 0x433910 ADD X6, X4, X20 |
(1690) 0x433914 ADD X21, X28, X20 |
(1690) 0x433918 ADD X28, X18, X10 |
(1690) 0x43391c ADDVL X10, X10, #1 |
(1690) 0x433920 ADD X4, X19, X8 |
(1690) 0x433924 ADDVL X8, X8, #1 |
(1690) 0x433928 ADD X10, X18, X10 |
(1690) 0x43392c ADD X8, X19, X8 |
(1690) 0x433930 HINT #0 |
(1690) 0x433934 HINT #0 |
(1690) 0x433938 HINT #0 |
(1690) 0x43393c HINT #0 |
(1696) 0x433940 LD1D {Z0.D}, P0/Z, [X28, X24,LSL #3] |
(1696) 0x433944 LD1D {Z1.D}, P0/Z, [X10, X24,LSL #3] |
(1696) 0x433948 ST1D {Z0.D}, P0, [X4, X24,LSL #3] |
(1696) 0x43394c ST1D {Z1.D}, P0, [X8, X24,LSL #3] |
(1696) 0x433950 ADD X24, X24, X25 |
(1696) 0x433954 CMP X20, X24 |
(1696) 0x433958 B.NE 433940 |
(1690) 0x43395c CBNZ X30, 433780 |
(1690) 0x433960 B 433824 |
(1690) 0x433964 UDIV X10, X8, X25 |
(1690) 0x433968 ORR X24, XZR, XZR |
(1690) 0x43396c MADD X20, X10, X25, XZR |
(1690) 0x433970 UBFM X10, X21, #61, #60 |
(1690) 0x433974 SUB X22, X8, X20 |
(1690) 0x433978 UBFM X8, X6, #61, #60 |
(1690) 0x43397c ADD X4, X6, X20 |
(1690) 0x433980 ADD X7, X21, X20 |
(1690) 0x433984 ADD X21, X1, X10 |
(1690) 0x433988 ADDVL X10, X10, #1 |
(1690) 0x43398c ADD X6, X19, X8 |
(1690) 0x433990 ADDVL X8, X8, #1 |
(1690) 0x433994 ADD X10, X1, X10 |
(1690) 0x433998 ADD X8, X19, X8 |
(1690) 0x43399c HINT #0 |
(1693) 0x4339a0 LD1D {Z0.D}, P0/Z, [X21, X24,LSL #3] |
(1693) 0x4339a4 LD1D {Z1.D}, P0/Z, [X10, X24,LSL #3] |
(1693) 0x4339a8 ST1D {Z0.D}, P0, [X6, X24,LSL #3] |
(1693) 0x4339ac ST1D {Z1.D}, P0, [X8, X24,LSL #3] |
(1693) 0x4339b0 ADD X24, X24, X25 |
(1693) 0x4339b4 CMP X20, X24 |
(1693) 0x4339b8 B.NE 4339a0 |
(1690) 0x4339bc CBNZ X22, 433860 |
(1690) 0x4339c0 B 433724 |
(1688) 0x4339c4 LDP X11, X9, [SP, #392] |
(1688) 0x4339c8 LDR X8, [SP, #648] |
(1688) 0x4339cc LDP X12, X10, [SP, #408] |
(1688) 0x4339d0 LDR X3, [SP, #568] |
(1688) 0x4339d4 STR X23, [X11, #8] |
(1688) 0x4339d8 LDR X9, [X9, X8,LSL #3] |
(1688) 0x4339dc STR X10, [X11, #40] |
(1688) 0x4339e0 STR X9, [X11, #24] |
(1688) 0x4339e4 LDR X9, [X12, X8,LSL #3] |
(1688) 0x4339e8 STR X9, [X11, #56] |
(1688) 0x4339ec LDR X8, [X12, X8,LSL #3] |
(1688) 0x4339f0 LDR X22, [X8, X10,LSL #3] |
(1688) 0x4339f4 LDR X8, [SP, #360] |
(1688) 0x4339f8 CMP X22, X8 |
(1688) 0x4339fc B.LE 433a20 |
(1688) 0x433a00 ORR X0, XZR, X3 |
(1688) 0x433a04 BL 4ae530 |
(1688) 0x433a08 ORR X0, XZR, X22 |
(1688) 0x433a0c MOVZ W1, #8 |
(1688) 0x433a10 STR XZR, [SP, #568] |
(1688) 0x433a14 BL 4ae430 |
(1688) 0x433a18 ORR X3, XZR, X0 |
(1688) 0x433a1c STR X0, [SP, #568] |
(1688) 0x433a20 LDR X1, [SP, #392] |
(1688) 0x433a24 ORR X2, XZR, X19 |
(1688) 0x433a28 MOVZ W0, #1 |
(1688) 0x433a2c SUB X21, X29, #232 |
(1688) 0x433a30 BL 485620 |
(1688) 0x433a34 BL 485a00 |
(1688) 0x433a38 LDR X8, [SP, #648] |
(1688) 0x433a3c LDR X20, [SP, #400] |
(1688) 0x433a40 LDR X0, [X20, X8,LSL #3] |
(1688) 0x433a44 BL 4ae530 |
(1688) 0x433a48 LDR X8, [SP, #648] |
(1688) 0x433a4c STR XZR, [X20, X8,LSL #3] |
(1688) 0x433a50 LDR X20, [SP, #408] |
(1688) 0x433a54 LDR X0, [X20, X8,LSL #3] |
(1688) 0x433a58 BL 4ae530 |
(1688) 0x433a5c LDR X8, [SP, #648] |
(1688) 0x433a60 STR XZR, [X20, X8,LSL #3] |
(1688) 0x433a64 LDR X9, [SP, #752] |
(1688) 0x433a68 ADD X3, SP, #632 |
(1688) 0x433a6c SUB X4, X29, #128 |
(1688) 0x433a70 ADD X5, SP, #624 |
(1688) 0x433a74 ADD X6, SP, #480 |
(1688) 0x433a78 ADD X7, SP, #616 |
(1688) 0x433a7c ADRP X0, |
(1688) 0x433a80 ADD X0, X0, #792 |
(1688) 0x433a84 MOVZ W1, #42 |
(1688) 0x433a88 ADRP X2, 436a88 |
(1688) 0x433a8c ADD X2, X2, #3568 |
(1688) 0x433a90 ADD X8, X9, X8,LSL #3 |
(1688) 0x433a94 LDP X8, X9, [X8] |
(1688) 0x433a98 SUB X8, X9, X8 |
(1688) 0x433a9c STR X8, [SP, #464] |
(1688) 0x433aa0 SUB X8, X29, #224 |
(1688) 0x433aa4 STP X8, X21, [SP, #280] |
(1688) 0x433aa8 ADD X8, SP, #568 |
(1688) 0x433aac STR X8, [SP, #272] |
(1688) 0x433ab0 SUB X8, X29, #72 |
(1688) 0x433ab4 STR X8, [SP, #264] |
(1688) 0x433ab8 ADD X8, SP, #712 |
(1688) 0x433abc STR X8, [SP, #256] |
(1688) 0x433ac0 ADD X8, SP, #696 |
(1688) 0x433ac4 STR X8, [SP, #248] |
(1688) 0x433ac8 SUB X8, X29, #208 |
(1688) 0x433acc STR X8, [SP, #240] |
(1688) 0x433ad0 SUB X8, X29, #88 |
(1688) 0x433ad4 STR X8, [SP, #232] |
(1688) 0x433ad8 ADD X8, SP, #680 |
(1688) 0x433adc STR X8, [SP, #224] |
(1688) 0x433ae0 ADD X8, X29, #104 |
(1688) 0x433ae4 STR X8, [SP, #216] |
(1688) 0x433ae8 SUB X8, X29, #80 |
(1688) 0x433aec STR X8, [SP, #208] |
(1688) 0x433af0 SUB X8, X29, #40 |
(1688) 0x433af4 STR X8, [SP, #200] |
(1688) 0x433af8 SUB X8, X29, #32 |
(1688) 0x433afc STR X8, [SP, #192] |
(1688) 0x433b00 SUB X8, X29, #8 |
(1688) 0x433b04 STR X8, [SP, #184] |
(1688) 0x433b08 SUB X8, X29, #48 |
(1688) 0x433b0c STR X8, [SP, #176] |
(1688) 0x433b10 SUB X8, X29, #64 |
(1688) 0x433b14 STR X8, [SP, #168] |
(1688) 0x433b18 SUB X8, X29, #56 |
(1688) 0x433b1c STR X8, [SP, #160] |
(1688) 0x433b20 ADD X8, SP, #576 |
(1688) 0x433b24 STR X8, [SP, #152] |
(1688) 0x433b28 SUB X8, X29, #120 |
(1688) 0x433b2c STR X8, [SP, #144] |
(1688) 0x433b30 SUB X8, X29, #112 |
(1688) 0x433b34 STR X8, [SP, #136] |
(1688) 0x433b38 ADD X8, SP, #584 |
(1688) 0x433b3c STR X8, [SP, #128] |
(1688) 0x433b40 SUB X8, X29, #104 |
(1688) 0x433b44 STR X8, [SP, #120] |
(1688) 0x433b48 SUB X8, X29, #96 |
(1688) 0x433b4c STR X8, [SP, #112] |
(1688) 0x433b50 SUB X8, X29, #176 |
(1688) 0x433b54 STR X8, [SP, #104] |
(1688) 0x433b58 SUB X8, X29, #160 |
(1688) 0x433b5c STR X8, [SP, #96] |
(1688) 0x433b60 ADD X8, SP, #720 |
(1688) 0x433b64 STR X8, [SP, #88] |
(1688) 0x433b68 SUB X8, X29, #168 |
(1688) 0x433b6c STR X8, [SP, #80] |
(1688) 0x433b70 ADD X8, SP, #736 |
(1688) 0x433b74 STR X8, [SP, #72] |
(1688) 0x433b78 SUB X8, X29, #152 |
(1688) 0x433b7c STR X8, [SP, #64] |
(1688) 0x433b80 SUB X8, X29, #136 |
(1688) 0x433b84 STR X8, [SP, #56] |
(1688) 0x433b88 ADD X8, SP, #728 |
(1688) 0x433b8c STR X8, [SP, #48] |
(1688) 0x433b90 SUB X8, X29, #144 |
(1688) 0x433b94 STR X8, [SP, #40] |
(1688) 0x433b98 ADD X8, SP, #744 |
(1688) 0x433b9c STR X8, [SP, #32] |
(1688) 0x433ba0 ADD X8, SP, #760 |
(1688) 0x433ba4 STR X8, [SP, #24] |
(1688) 0x433ba8 ADD X8, SP, #464 |
(1688) 0x433bac STR X8, [SP, #16] |
(1688) 0x433bb0 ADD X8, SP, #648 |
(1688) 0x433bb4 STR X8, [SP, #8] |
(1688) 0x433bb8 ADD X8, SP, #752 |
(1688) 0x433bbc STR X8, [SP] |
(1688) 0x433bc0 BL 40fa00 |
(1688) 0x433bc4 LDR X8, [SP, #728] |
(1688) 0x433bc8 LDR X9, [SP, #648] |
(1688) 0x433bcc LDR X0, [X8, X9,LSL #3] |
(1688) 0x433bd0 BL 4ae530 |
(1688) 0x433bd4 LDR X9, [SP, #728] |
(1688) 0x433bd8 LDR X8, [SP, #648] |
(1688) 0x433bdc STR XZR, [X9, X8,LSL #3] |
(1688) 0x433be0 LDR X9, [SP, #528] |
(1688) 0x433be4 CMP X9, #2 |
(1688) 0x433be8 B.LT 43364c |
(1688) 0x433bec LDR X9, [SP, #720] |
(1688) 0x433bf0 LDR X0, [X9, X8,LSL #3] |
(1688) 0x433bf4 BL 4ae530 |
(1688) 0x433bf8 LDR X8, [SP, #720] |
(1688) 0x433bfc LDR X9, [SP, #648] |
(1688) 0x433c00 STR XZR, [X8, X9,LSL #3] |
(1688) 0x433c04 LDR X8, [SP, #712] |
(1688) 0x433c08 LDR X0, [X8, X9,LSL #3] |
(1688) 0x433c0c BL 4ae530 |
(1688) 0x433c10 LDR X9, [SP, #712] |
(1688) 0x433c14 LDR X8, [SP, #648] |
(1688) 0x433c18 STR XZR, [X9, X8,LSL #3] |
(1688) 0x433c1c B 43364c |
(1671) 0x433c20 LDR X19, [SP, #640] |
(1671) 0x433c24 STP XZR, XZR, [SP, #400] |
(1671) 0x433c28 MOVZ W8, #2 |
(1671) 0x433c2c CMP X19, #3 |
(1671) 0x433c30 STR X8, [SP, #648] |
(1671) 0x433c34 B.LT 4333ac |
(1671) 0x433c38 LDR X19, [SP, #400] |
(1671) 0x433c3c ORR X25, XZR, XZR |
(1671) 0x433c40 ORR X20, XZR, XZR |
(1671) 0x433c44 SUB X22, X30, #8 |
(1671) 0x433c48 SUB X23, X29, #168 |
(1671) 0x433c4c SUB X26, X29, #144 |
(1671) 0x433c50 STP XZR, XZR, [SP, #360] |
(1671) 0x433c54 STR X22, [SP, #352] |
(1671) 0x433c58 B 433d70 |
0x433c5c HINT #0 |
(1698) 0x433c60 LDR X8, [SP, #752] |
(1698) 0x433c64 LDR X9, [SP, #648] |
(1698) 0x433c68 ADD X3, SP, #464 |
(1698) 0x433c6c ADD X4, SP, #752 |
(1698) 0x433c70 ADD X5, SP, #648 |
(1698) 0x433c74 ADD X6, SP, #624 |
(1698) 0x433c78 ADD X7, SP, #480 |
(1698) 0x433c7c ADRP X0, |
(1698) 0x433c80 ADD X0, X0, #672 |
(1698) 0x433c84 MOVZ W1, #29 |
(1698) 0x433c88 ADRP X2, 435c88 |
(1698) 0x433c8c ADD X2, X2, #2576 |
(1698) 0x433c90 ADD X8, X8, X9,LSL #3 |
(1698) 0x433c94 LDP X8, X9, [X8] |
(1698) 0x433c98 SUB X8, X9, X8 |
(1698) 0x433c9c STR X8, [SP, #464] |
(1698) 0x433ca0 ADD X8, SP, #528 |
(1698) 0x433ca4 STR X8, [SP, #184] |
(1698) 0x433ca8 ADD X8, SP, #512 |
(1698) 0x433cac STR X8, [SP, #176] |
(1698) 0x433cb0 ADD X8, SP, #656 |
(1698) 0x433cb4 STR X8, [SP, #168] |
(1698) 0x433cb8 ADD X8, SP, #448 |
(1698) 0x433cbc STR X8, [SP, #160] |
(1698) 0x433cc0 ADD X8, SP, #440 |
(1698) 0x433cc4 STR X8, [SP, #152] |
(1698) 0x433cc8 ADD X8, SP, #456 |
(1698) 0x433ccc STR X8, [SP, #144] |
(1698) 0x433cd0 ADD X8, SP, #712 |
(1698) 0x433cd4 STR X8, [SP, #136] |
(1698) 0x433cd8 ADD X8, SP, #696 |
(1698) 0x433cdc STR X8, [SP, #128] |
(1698) 0x433ce0 SUB X8, X29, #208 |
(1698) 0x433ce4 STR X8, [SP, #120] |
(1698) 0x433ce8 ADD X8, SP, #576 |
(1698) 0x433cec STR X8, [SP, #112] |
(1698) 0x433cf0 SUB X8, X29, #120 |
(1698) 0x433cf4 STR X8, [SP, #104] |
(1698) 0x433cf8 SUB X8, X29, #112 |
(1698) 0x433cfc STR X8, [SP, #96] |
(1698) 0x433d00 ADD X8, SP, #720 |
(1698) 0x433d04 STP X23, X8, [SP, #80] |
(1698) 0x433d08 ADD X8, SP, #728 |
(1698) 0x433d0c STP X26, X8, [SP, #64] |
(1698) 0x433d10 ADD X8, SP, #584 |
(1698) 0x433d14 STR X8, [SP, #56] |
(1698) 0x433d18 SUB X8, X29, #104 |
(1698) 0x433d1c STR X8, [SP, #48] |
(1698) 0x433d20 SUB X8, X29, #96 |
(1698) 0x433d24 STR X8, [SP, #40] |
(1698) 0x433d28 ADD X8, SP, #736 |
(1698) 0x433d2c STR X8, [SP, #32] |
(1698) 0x433d30 ADD X8, SP, #744 |
(1698) 0x433d34 STR X8, [SP, #24] |
(1698) 0x433d38 ADD X8, SP, #760 |
(1698) 0x433d3c STR X8, [SP, #16] |
(1698) 0x433d40 ADD X8, SP, #616 |
(1698) 0x433d44 STR X8, [SP, #8] |
(1698) 0x433d48 ADD X8, SP, #488 |
(1698) 0x433d4c STR X8, [SP] |
(1698) 0x433d50 BL 40fa00 |
(1698) 0x433d54 LDR X8, [SP, #648] |
(1698) 0x433d58 LDR X9, [SP, #640] |
(1698) 0x433d5c LDR X30, [SP, #432] |
(1698) 0x433d60 ADD X8, X8, #1 |
(1698) 0x433d64 CMP X8, X9 |
(1698) 0x433d68 STR X8, [SP, #648] |
(1698) 0x433d6c B.GE 4333b4 |
(1698) 0x433d70 LDR X8, [SP, #528] |
(1698) 0x433d74 CMP X8, #1 |
(1698) 0x433d78 B.LE 433e9c |
(1698) 0x433d7c LDUR X8, [X29, #328] |
(1698) 0x433d80 MOVZ W1, #8 |
(1698) 0x433d84 ADD X0, X8, #1 |
(1698) 0x433d88 BL 4ae430 |
(1698) 0x433d8c LDR X8, [SP, #648] |
(1698) 0x433d90 MOVZ W1, #8 |
(1698) 0x433d94 STR X0, [X19, X8,LSL #3] |
(1698) 0x433d98 LDR X0, [SP, #344] |
(1698) 0x433d9c BL 4ae430 |
(1698) 0x433da0 LDR X8, [SP, #648] |
(1698) 0x433da4 LDR X9, [SP, #408] |
(1698) 0x433da8 STR X0, [X9, X8,LSL #3] |
(1698) 0x433dac STR XZR, [SP, #504] |
(1698) 0x433db0 LDR X8, [X19, X8,LSL #3] |
(1698) 0x433db4 STR XZR, [X8] |
(1698) 0x433db8 STR XZR, [SP, #560] |
(1698) 0x433dbc LDUR X8, [X29, #328] |
(1698) 0x433dc0 CMP X8, #1 |
(1698) 0x433dc4 B.LT 433e44 |
(1698) 0x433dc8 ADRP X26, 435dc8 |
(1698) 0x433dcc ADD X26, X26, #2112 |
(1698) 0x433dd0 ADD X28, SP, #504 |
(1698) 0x433dd4 SUB X24, X29, #168 |
(1698) 0x433dd8 SUB X23, X29, #144 |
(1698) 0x433ddc HINT #0 |
(1710) 0x433de0 ORR X2, XZR, X26 |
(1710) 0x433de4 SUB X3, X29, #192 |
(1710) 0x433de8 ADD X4, SP, #560 |
(1710) 0x433dec SUB X5, X29, #200 |
(1710) 0x433df0 STP X24, X28, [SP, #16] |
(1710) 0x433df4 ADD X6, SP, #584 |
(1710) 0x433df8 ADD X7, SP, #648 |
(1710) 0x433dfc SUB X8, X29, #216 |
(1710) 0x433e00 ADRP X0, |
(1710) 0x433e04 ADD X0, X0, #576 |
(1710) 0x433e08 STP X8, X23, [SP] |
(1710) 0x433e0c MOVZ W1, #9 |
(1710) 0x433e10 BL 40fa00 |
(1710) 0x433e14 LDR X9, [SP, #648] |
(1710) 0x433e18 LDR X10, [SP, #560] |
(1710) 0x433e1c LDR X8, [SP, #504] |
(1710) 0x433e20 LDR X9, [X19, X9,LSL #3] |
(1710) 0x433e24 ADD X9, X9, X10,LSL #3 |
(1710) 0x433e28 STR X8, [X9, #8] |
(1710) 0x433e2c LDR X8, [SP, #560] |
(1710) 0x433e30 LDUR X9, [X29, #328] |
(1710) 0x433e34 ADD X8, X8, #1 |
(1710) 0x433e38 CMP X8, X9 |
(1710) 0x433e3c STR X8, [SP, #560] |
(1710) 0x433e40 B.LT 433de0 |
(1698) 0x433e44 LDR X8, [SP, #696] |
(1698) 0x433e48 LDUR X2, [X29, #296] |
(1698) 0x433e4c LDR X1, [SP, #376] |
(1698) 0x433e50 MOVZ W0, #11 |
(1698) 0x433e54 ADD X3, X8, #8 |
(1698) 0x433e58 BL 485620 |
(1698) 0x433e5c BL 485a00 |
(1698) 0x433e60 LDR X8, [SP, #504] |
(1698) 0x433e64 LDR X9, [SP, #368] |
(1698) 0x433e68 CMP X8, X9 |
(1698) 0x433e6c B.LE 433e8c |
(1698) 0x433e70 ORR X0, XZR, X20 |
(1698) 0x433e74 BL 4ae530 |
(1698) 0x433e78 LDR X0, [SP, #504] |
(1698) 0x433e7c MOVZ W1, #8 |
(1698) 0x433e80 BL 4ae430 |
(1698) 0x433e84 LDR X8, [SP, #504] |
(1698) 0x433e88 ORR X20, XZR, X0 |
(1698) 0x433e8c LDR X30, [SP, #432] |
(1698) 0x433e90 SUB X23, X29, #168 |
(1698) 0x433e94 SUB X26, X29, #144 |
(1698) 0x433e98 STR X8, [SP, #368] |
(1698) 0x433e9c LDUR X13, [X29, #328] |
(1698) 0x433ea0 STR XZR, [SP, #560] |
(1698) 0x433ea4 CMP X13, #1 |
(1698) 0x433ea8 B.LT 434000 |
(1698) 0x433eac LDP X9, X8, [X29, #824] |
(1698) 0x433eb0 LDR X11, [SP, #584] |
(1698) 0x433eb4 ORR X10, XZR, XZR |
(1698) 0x433eb8 ORR X0, XZR, XZR |
(1698) 0x433ebc B 433ed0 |
(1705) 0x433ec0 LDUR X13, [X29, #328] |
(1705) 0x433ec4 CMP X0, X13 |
(1705) 0x433ec8 STR X0, [SP, #560] |
(1705) 0x433ecc B.GE 434000 |
(1705) 0x433ed0 LDR X12, [X8, X0,LSL #3] |
(1705) 0x433ed4 ADD X0, X0, #1 |
(1705) 0x433ed8 LDR X14, [X8, X0,LSL #3] |
(1705) 0x433edc CMP X12, X14 |
(1705) 0x433ee0 B.GE 433ec4 |
(1705) 0x433ee4 LDR X18, [SP, #728] |
(1705) 0x433ee8 LDR X13, [SP, #744] |
(1705) 0x433eec LDUR X14, [X29, #368] |
(1705) 0x433ef0 SUB X18, X18, #8 |
(1705) 0x433ef4 LDR X15, [SP, #736] |
(1705) 0x433ef8 LDUR X16, [X29, #344] |
(1705) 0x433efc LDR X17, [SP, #720] |
(1705) 0x433f00 B 433f1c |
(1706) 0x433f04 LDR X0, [SP, #560] |
(1706) 0x433f08 ADD X12, X12, #1 |
(1706) 0x433f0c ADD X0, X0, #1 |
(1706) 0x433f10 LDR X1, [X8, X0,LSL #3] |
(1706) 0x433f14 CMP X12, X1 |
(1706) 0x433f18 B.GE 433ec0 |
(1706) 0x433f1c LDR X0, [X9, X12,LSL #3] |
(1706) 0x433f20 LDR X2, [SP, #648] |
(1706) 0x433f24 LDR X1, [X11, X0,LSL #3] |
(1706) 0x433f28 SUB X2, X2, #1 |
(1706) 0x433f2c CMP X1, X2 |
(1706) 0x433f30 B.NE 433f04 |
(1706) 0x433f34 ADD X1, X0, #1 |
(1706) 0x433f38 LDR X3, [X14, X1,LSL #3] |
(1706) 0x433f3c CMP X3, #1 |
(1706) 0x433f40 B.LT 433f70 |
(1706) 0x433f44 LDR X2, [X13, X0,LSL #3] |
(1706) 0x433f48 ADD X3, X3, X2 |
(1709) 0x433f4c LDR X4, [SP, #648] |
(1709) 0x433f50 LDR X4, [X18, X4,LSL #3] |
(1709) 0x433f54 LDR X4, [X4, X2,LSL #3] |
(1709) 0x433f58 ADD X2, X2, #1 |
(1709) 0x433f5c CMP X2, X3 |
(1709) 0x433f60 ADD X4, X4, X27 |
(1709) 0x433f64 STR X4, [X20, X10,LSL #3] |
(1709) 0x433f68 ADD X10, X10, #1 |
(1709) 0x433f6c B.LT 433f4c |
(1706) 0x433f70 LDR X1, [X16, X1,LSL #3] |
(1706) 0x433f74 CMP X1, #1 |
(1706) 0x433f78 B.LT 433f04 |
(1706) 0x433f7c LDR X0, [X15, X0,LSL #3] |
(1706) 0x433f80 ADD X1, X1, X0 |
(1706) 0x433f84 B 433f94 |
(1707) 0x433f88 ADD X0, X0, #1 |
(1707) 0x433f8c CMP X0, X1 |
(1707) 0x433f90 B.GE 433f04 |
(1707) 0x433f94 LDR X2, [SP, #648] |
(1707) 0x433f98 LDR X4, [SP, #704] |
(1707) 0x433f9c ORR X5, XZR, X22 |
(1707) 0x433fa0 SUB X3, X2, #1 |
(1707) 0x433fa4 ADD X4, X4, #8 |
(1707) 0x433fa8 LDR X2, [X17, X3,LSL #3] |
(1707) 0x433fac CMP X3, #0 |
(1707) 0x433fb0 CSEL X3, X3, XZR, #12 |
(1707) 0x433fb4 LDR X2, [X2, X0,LSL #3] |
(1707) 0x433fb8 HINT #0 |
(1707) 0x433fbc HINT #0 |
(1708) 0x433fc0 CBZ X3, 433f88 |
(1708) 0x433fc4 LDR X6, [X4], #8 |
(1708) 0x433fc8 ADD X5, X5, #8 |
(1708) 0x433fcc SUB X3, X3, #1 |
(1708) 0x433fd0 CMP X2, X6 |
(1708) 0x433fd4 B.GE 433fc0 |
(1707) 0x433fd8 LDUR X3, [X4, #496] |
(1707) 0x433fdc SUB X2, X2, X3 |
(1707) 0x433fe0 LDR X3, [X5] |
(1707) 0x433fe4 LDR X2, [X3, X2,LSL #3] |
(1707) 0x433fe8 STR X2, [X20, X10,LSL #3] |
(1707) 0x433fec ADD X10, X10, #1 |
(1707) 0x433ff0 B 433f88 |
0x433ff4 HINT #0 |
0x433ff8 HINT #0 |
0x433ffc HINT #0 |
(1698) 0x434000 LDR X8, [SP, #528] |
(1698) 0x434004 CMP X8, #1 |
(1698) 0x434008 B.LE 43418c |
(1698) 0x43400c LDR X8, [SP, #648] |
(1698) 0x434010 LDR X9, [SP, #408] |
(1698) 0x434014 LDR X8, [X9, X8,LSL #3] |
(1698) 0x434018 STR XZR, [X8] |
(1698) 0x43401c LDR X8, [SP, #416] |
(1698) 0x434020 STR XZR, [SP, #560] |
(1698) 0x434024 CMP X8, #1 |
(1698) 0x434028 B.LT 4340c8 |
(1698) 0x43402c LDR X8, [SP, #576] |
(1698) 0x434030 ORR X24, XZR, XZR |
(1698) 0x434034 ORR X9, XZR, XZR |
(1698) 0x434038 B 434068 |
0x43403c HINT #0 |
(1703) 0x434040 LDR X9, [SP, #648] |
(1703) 0x434044 LDR X10, [SP, #408] |
(1703) 0x434048 LDR X9, [X10, X9,LSL #3] |
(1703) 0x43404c LDR X10, [SP, #416] |
(1703) 0x434050 STR X24, [X9, X13,LSL #3] |
(1703) 0x434054 LDR X9, [SP, #560] |
(1703) 0x434058 ADD X9, X9, #1 |
(1703) 0x43405c CMP X9, X10 |
(1703) 0x434060 STR X9, [SP, #560] |
(1703) 0x434064 B.GE 4340cc |
(1703) 0x434068 ADD X13, X9, #1 |
(1703) 0x43406c LDR X10, [X21, X9,LSL #3] |
(1703) 0x434070 LDR X11, [X21, X13,LSL #3] |
(1703) 0x434074 CMP X10, X11 |
(1703) 0x434078 B.GE 434040 |
(1703) 0x43407c LDR X12, [SP, #696] |
(1703) 0x434080 LDUR X11, [X29, #304] |
(1703) 0x434084 ADD X12, X12, #8 |
(1703) 0x434088 B 4340a0 |
(1704) 0x43408c ADD X13, X9, #1 |
(1704) 0x434090 ADD X10, X10, #1 |
(1704) 0x434094 LDR X14, [X21, X13,LSL #3] |
(1704) 0x434098 CMP X10, X14 |
(1704) 0x43409c B.GE 434040 |
(1704) 0x4340a0 LDR X14, [SP, #648] |
(1704) 0x4340a4 LDR X13, [X8, X10,LSL #3] |
(1704) 0x4340a8 SUB X14, X14, #1 |
(1704) 0x4340ac CMP X13, X14 |
(1704) 0x4340b0 B.NE 43408c |
(1704) 0x4340b4 STR X24, [X11, X10,LSL #3] |
(1704) 0x4340b8 LDR X9, [X12, X10,LSL #3] |
(1704) 0x4340bc ADD X24, X9, X24 |
(1704) 0x4340c0 LDR X9, [SP, #560] |
(1704) 0x4340c4 B 43408c |
(1698) 0x4340c8 ORR X24, XZR, XZR |
(1698) 0x4340cc LDP X8, X10, [SP, #384] |
(1698) 0x4340d0 LDR X11, [SP, #416] |
(1698) 0x4340d4 STR X8, [X10] |
(1698) 0x4340d8 LDR X8, [SP, #336] |
(1698) 0x4340dc LDUR X9, [X29, #328] |
(1698) 0x4340e0 STP X9, X8, [X10, #8] |
(1698) 0x4340e4 LDR X8, [SP, #648] |
(1698) 0x4340e8 LDR X9, [X19, X8,LSL #3] |
(1698) 0x4340ec STR X9, [X10, #24] |
(1698) 0x4340f0 LDR X9, [SP, #328] |
(1698) 0x4340f4 STP X11, X9, [X10, #40] |
(1698) 0x4340f8 LDR X9, [SP, #408] |
(1698) 0x4340fc LDR X9, [X9, X8,LSL #3] |
(1698) 0x434100 STR X9, [X10, #56] |
(1698) 0x434104 CBZ X24, 434134 |
(1698) 0x434108 ORR X0, XZR, X24 |
(1698) 0x43410c MOVZ W1, #8 |
(1698) 0x434110 BL 4ae430 |
(1698) 0x434114 LDR X8, [SP, #712] |
(1698) 0x434118 LDR X9, [SP, #648] |
(1698) 0x43411c MOVZ W1, #8 |
(1698) 0x434120 STR X0, [X8, X9,LSL #3] |
(1698) 0x434124 ORR X0, XZR, X24 |
(1698) 0x434128 BL 4ae430 |
(1698) 0x43412c LDR X8, [SP, #648] |
(1698) 0x434130 B 434140 |
(1698) 0x434134 LDR X9, [SP, #712] |
(1698) 0x434138 ORR X0, XZR, XZR |
(1698) 0x43413c STR XZR, [X9, X8,LSL #3] |
(1698) 0x434140 STR X0, [X22, X8,LSL #3] |
(1698) 0x434144 LDR X1, [SP, #392] |
(1698) 0x434148 LDR X19, [SP, #360] |
(1698) 0x43414c ORR X2, XZR, X20 |
(1698) 0x434150 MOVZ W0, #11 |
(1698) 0x434154 LDR X9, [SP, #712] |
(1698) 0x434158 LDR X3, [X9, X8,LSL #3] |
(1698) 0x43415c BL 485620 |
(1698) 0x434160 BL 485a00 |
(1698) 0x434164 CMP X24, X19 |
(1698) 0x434168 B.LE 434184 |
(1698) 0x43416c ORR X0, XZR, X25 |
(1698) 0x434170 BL 4ae530 |
(1698) 0x434174 ORR X0, XZR, X24 |
(1698) 0x434178 MOVZ W1, #8 |
(1698) 0x43417c BL 4ae430 |
(1698) 0x434180 ORR X25, XZR, X0 |
(1698) 0x434184 LDR X30, [SP, #432] |
(1698) 0x434188 STR X24, [SP, #360] |
(1698) 0x43418c LDR X8, [SP, #416] |
(1698) 0x434190 STR XZR, [SP, #560] |
(1698) 0x434194 CMP X8, #1 |
(1698) 0x434198 B.LT 434420 |
(1698) 0x43419c LDR X28, [X21, XZR,LSL #3] |
(1698) 0x4341a0 ORR X19, XZR, XZR |
(1698) 0x4341a4 ORR X22, XZR, XZR |
(1698) 0x4341a8 ORR X8, XZR, XZR |
(1698) 0x4341ac B 4341cc |
0x4341b0 HINT #0 |
0x4341b4 HINT #0 |
0x4341b8 HINT #0 |
0x4341bc HINT #0 |
(1700) 0x4341c0 LDR X8, [SP, #560] |
(1700) 0x4341c4 LDR X21, [SP, #424] |
(1700) 0x4341c8 ORR X22, XZR, X9 |
(1700) 0x4341cc ADD X9, X8, #1 |
(1700) 0x4341d0 LDR X10, [X21, X9,LSL #3] |
(1700) 0x4341d4 CMP X28, X10 |
(1700) 0x4341d8 B.GE 43432c |
(1700) 0x4341dc LDR X9, [SP, #576] |
(1700) 0x4341e0 LDR X10, [SP, #648] |
(1700) 0x4341e4 LDR X9, [X9, X28,LSL #3] |
(1700) 0x4341e8 SUB X10, X10, #1 |
(1700) 0x4341ec ADD X28, X28, #1 |
(1700) 0x4341f0 CMP X9, X10 |
(1700) 0x4341f4 B.NE 4341cc |
(1700) 0x4341f8 LDR X9, [SP, #696] |
(1700) 0x4341fc LDR X9, [X9, X28,LSL #3] |
(1700) 0x434200 CMP X9, #1 |
(1700) 0x434204 B.LT 434324 |
(1700) 0x434208 LDR X8, [SP, #712] |
(1700) 0x43420c ORR X26, XZR, X22 |
(1700) 0x434210 B 434240 |
0x434214 HINT #0 |
0x434218 HINT #0 |
0x43421c HINT #0 |
(1701) 0x434220 ORN X9, XZR, X11 |
(1701) 0x434224 STR X9, [X10, X26,LSL #3] |
(1701) 0x434228 LDR X9, [SP, #696] |
(1701) 0x43422c ADD X26, X26, #1 |
(1701) 0x434230 LDR X9, [X9, X28,LSL #3] |
(1701) 0x434234 ADD X9, X9, X22 |
(1701) 0x434238 CMP X26, X9 |
(1701) 0x43423c B.GE 4341c0 |
(1701) 0x434240 LDR X9, [SP, #648] |
(1701) 0x434244 LDR X10, [X8, X9,LSL #3] |
(1701) 0x434248 LDR X24, [X10, X26,LSL #3] |
(1701) 0x43424c SUBS X11, X24, X27 |
(1701) 0x434250 B.MI 434260 |
(1701) 0x434254 LDR X12, [SP, #624] |
(1701) 0x434258 CMP X11, X12 |
(1701) 0x43425c B.LT 434220 |
(1701) 0x434260 CMP X9, #2 |
(1701) 0x434264 B.LT 4342c8 |
(1701) 0x434268 ORR X23, XZR, X25 |
(1701) 0x43426c ORR X25, XZR, X27 |
(1701) 0x434270 LDR X27, [SP, #704] |
(1701) 0x434274 ORR X21, XZR, XZR |
(1701) 0x434278 HINT #0 |
(1701) 0x43427c HINT #0 |
(1702) 0x434280 UBFM X8, X21, #61, #60 |
(1702) 0x434284 ORR X1, XZR, X24 |
(1702) 0x434288 LDR X0, [X30, X8] |
(1702) 0x43428c ADD X8, X27, X8 |
(1702) 0x434290 LDP X8, X9, [X8] |
(1702) 0x434294 SUB X2, X9, X8 |
(1702) 0x434298 BL 4ad5e0 |
(1702) 0x43429c TBZ X0, #63, 434300 |
(1702) 0x4342a0 LDR X9, [SP, #648] |
(1702) 0x4342a4 LDR X30, [SP, #432] |
(1702) 0x4342a8 ADD X21, X21, #1 |
(1702) 0x4342ac SUB X10, X9, #1 |
(1702) 0x4342b0 CMP X21, X10 |
(1702) 0x4342b4 B.LT 434280 |
(1701) 0x4342b8 LDR X8, [SP, #712] |
(1701) 0x4342bc ORR X27, XZR, X25 |
(1701) 0x4342c0 ORR X25, XZR, X23 |
(1701) 0x4342c4 B 4342cc |
(1701) 0x4342c8 SUB X10, X9, #1 |
(1701) 0x4342cc LDR X9, [X8, X9,LSL #3] |
(1701) 0x4342d0 LDR X10, [X30, X10,LSL #3] |
(1701) 0x4342d4 LDR X9, [X9, X26,LSL #3] |
(1701) 0x4342d8 STR X9, [X10, X19,LSL #3] |
(1701) 0x4342dc STR X26, [X25, X19,LSL #3] |
(1701) 0x4342e0 ADD X19, X19, #1 |
(1701) 0x4342e4 LDR X9, [SP, #696] |
(1701) 0x4342e8 ADD X26, X26, #1 |
(1701) 0x4342ec LDR X9, [X9, X28,LSL #3] |
(1701) 0x4342f0 ADD X9, X9, X22 |
(1701) 0x4342f4 CMP X26, X9 |
(1701) 0x4342f8 B.LT 434240 |
(1700) 0x4342fc B 4341c0 |
(1701) 0x434300 LDR X8, [X27, X21,LSL #3] |
(1701) 0x434304 LDR X10, [SP, #648] |
(1701) 0x434308 LDR X30, [SP, #432] |
(1701) 0x43430c ORR X27, XZR, X25 |
(1701) 0x434310 ORR X25, XZR, X23 |
(1701) 0x434314 ADD X9, X8, X0 |
(1701) 0x434318 LDR X8, [SP, #712] |
(1701) 0x43431c LDR X10, [X8, X10,LSL #3] |
(1701) 0x434320 B 434224 |
(1700) 0x434324 ADD X22, X9, X22 |
(1700) 0x434328 B 4341cc |
(1700) 0x43432c LDR X8, [SP, #416] |
(1700) 0x434330 STR X9, [SP, #560] |
(1700) 0x434334 CMP X9, X8 |
(1700) 0x434338 ORR X8, XZR, X9 |
(1700) 0x43433c B.GE 434348 |
(1700) 0x434340 LDR X28, [X21, X8,LSL #3] |
(1700) 0x434344 B 4341cc |
(1698) 0x434348 LDR X22, [SP, #352] |
(1698) 0x43434c SUB X23, X29, #168 |
(1698) 0x434350 SUB X26, X29, #144 |
(1698) 0x434354 CBZ X19, 434420 |
(1698) 0x434358 LDR X8, [SP, #648] |
(1698) 0x43435c ORR X1, XZR, X25 |
(1698) 0x434360 ORR X2, XZR, XZR |
(1698) 0x434364 SUB X3, X19, #1 |
(1698) 0x434368 LDR X0, [X22, X8,LSL #3] |
(1698) 0x43436c BL 4aef20 |
(1698) 0x434370 LDR X9, [SP, #648] |
(1698) 0x434374 LDR X8, [SP, #704] |
(1698) 0x434378 CMP X19, #2 |
(1698) 0x43437c UBFM X10, X9, #61, #60 |
(1698) 0x434380 ADD X9, X10, X8 |
(1698) 0x434384 LDUR X11, [X9, #504] |
(1698) 0x434388 LDR X9, [SP, #712] |
(1698) 0x43438c STR X11, [SP, #488] |
(1698) 0x434390 LDR X12, [X25] |
(1698) 0x434394 LDR X10, [X9, X10] |
(1698) 0x434398 STR X11, [X10, X12,LSL #3] |
(1698) 0x43439c MOVZ W10, #1 |
(1698) 0x4343a0 STR X10, [SP, #560] |
(1698) 0x4343a4 B.LT 434460 |
(1698) 0x4343a8 ORR X10, XZR, XZR |
(1698) 0x4343ac MOVZ W11, #1 |
(1698) 0x4343b0 B 4343fc |
0x4343b4 HINT #0 |
0x4343b8 HINT #0 |
0x4343bc HINT #0 |
(1699) 0x4343c0 ADD X10, X10, #1 |
(1699) 0x4343c4 STR X14, [X13, X10,LSL #3] |
(1699) 0x4343c8 LDR X11, [SP, #488] |
(1699) 0x4343cc LDR X12, [SP, #648] |
(1699) 0x4343d0 ADD X13, X11, #1 |
(1699) 0x4343d4 LDR X11, [SP, #560] |
(1699) 0x4343d8 STR X13, [SP, #488] |
(1699) 0x4343dc LDR X12, [X9, X12,LSL #3] |
(1699) 0x4343e0 LDR X11, [X25, X11,LSL #3] |
(1699) 0x4343e4 STR X13, [X12, X11,LSL #3] |
(1699) 0x4343e8 LDR X11, [SP, #560] |
(1699) 0x4343ec ADD X11, X11, #1 |
(1699) 0x4343f0 CMP X11, X19 |
(1699) 0x4343f4 STR X11, [SP, #560] |
(1699) 0x4343f8 B.GE 434460 |
(1699) 0x4343fc LDR X12, [SP, #648] |
(1699) 0x434400 LDR X13, [X22, X12,LSL #3] |
(1699) 0x434404 LDR X14, [X13, X11,LSL #3] |
(1699) 0x434408 LDR X15, [X13, X10,LSL #3] |
(1699) 0x43440c CMP X14, X15 |
(1699) 0x434410 B.GT 4343c0 |
(1699) 0x434414 LDR X13, [SP, #488] |
(1699) 0x434418 B 4343dc |
0x43441c HINT #0 |
(1698) 0x434420 LDR X8, [SP, #528] |
(1698) 0x434424 LDR X19, [SP, #400] |
(1698) 0x434428 CMP X8, #1 |
(1698) 0x43442c B.LE 434444 |
(1698) 0x434430 LDR X8, [SP, #704] |
(1698) 0x434434 LDR X9, [SP, #648] |
(1698) 0x434438 ADD X8, X8, X9,LSL #3 |
(1698) 0x43443c LDUR X9, [X8, #504] |
(1698) 0x434440 STR X9, [X8] |
(1698) 0x434444 LDP X9, X8, [SP, #480] |
(1698) 0x434448 CMP X9, X8 |
(1698) 0x43444c B.GT 433c60 |
(1698) 0x434450 B 434480 |
0x434454 HINT #0 |
0x434458 HINT #0 |
0x43445c HINT #0 |
(1698) 0x434460 LDR X9, [SP, #488] |
(1698) 0x434464 LDR X10, [SP, #648] |
(1698) 0x434468 LDR X19, [SP, #400] |
(1698) 0x43446c ADD X9, X9, #1 |
(1698) 0x434470 STR X9, [X8, X10,LSL #3] |
(1698) 0x434474 LDP X9, X8, [SP, #480] |
(1698) 0x434478 CMP X9, X8 |
(1698) 0x43447c B.GT 433c60 |
(1698) 0x434480 ADD X8, X8, #1 |
(1698) 0x434484 STR X8, [SP, #480] |
(1698) 0x434488 B 433c60 |
(1671) 0x43448c STP X9, X8, [SP, #200] |
(1671) 0x434490 SUB X8, X29, #160 |
(1671) 0x434494 SUB X10, X29, #72 |
(1671) 0x434498 SUB X11, X29, #232 |
(1671) 0x43449c SUB X9, X29, #88 |
(1671) 0x4344a0 STP X21, X22, [SP, #80] |
(1671) 0x4344a4 STP X10, X8, [SP, #184] |
(1671) 0x4344a8 SUB X8, X29, #224 |
(1671) 0x4344ac STR X9, [SP, #160] |
(1671) 0x4344b0 ADD X9, X29, #104 |
(1671) 0x4344b4 SUB X10, X29, #32 |
(1671) 0x4344b8 ADD X12, SP, #728 |
(1671) 0x4344bc ADRP X0, |
(1671) 0x4344c0 ADD X0, X0, #816 |
(1671) 0x4344c4 STP X12, X20, [SP, #16] |
(1671) 0x4344c8 STP X8, X11, [SP, #168] |
(1671) 0x4344cc ADD X8, SP, #680 |
(1671) 0x4344d0 SUB X11, X29, #56 |
(1671) 0x4344d4 ADRP X2, 4374d4 |
(1671) 0x4344d8 ADD X2, X2, #2352 |
(1671) 0x4344dc STP X9, X8, [SP, #144] |
(1671) 0x4344e0 SUB X8, X29, #80 |
(1671) 0x4344e4 SUB X9, X29, #256 |
(1671) 0x4344e8 STP X9, X8, [SP, #128] |
(1671) 0x4344ec ADD X8, SP, #720 |
(1671) 0x4344f0 SUB X9, X29, #168 |
(1671) 0x4344f4 ADD X3, SP, #632 |
(1671) 0x4344f8 SUB X4, X29, #128 |
(1671) 0x4344fc STP X9, X8, [SP, #112] |
(1671) 0x434500 ADD X8, SP, #736 |
(1671) 0x434504 SUB X9, X29, #40 |
(1671) 0x434508 ADD X5, SP, #752 |
(1671) 0x43450c ADD X6, SP, #464 |
(1671) 0x434510 STP X24, X8, [SP, #96] |
(1671) 0x434514 SUB X8, X29, #48 |
(1671) 0x434518 ADD X7, SP, #760 |
(1671) 0x43451c MOVZ W1, #32 |
(1671) 0x434520 STP X9, X8, [SP, #64] |
(1671) 0x434524 SUB X8, X29, #8 |
(1671) 0x434528 SUB X9, X29, #64 |
(1671) 0x43452c STP X8, X10, [SP, #48] |
(1671) 0x434530 ADD X8, SP, #744 |
(1671) 0x434534 STP X11, X9, [SP, #32] |
(1671) 0x434538 STP X8, X19, [SP] |
(1671) 0x43453c BL 40fa00 |
(1671) 0x434540 LDR X8, [SP, #624] |
(1671) 0x434544 CBZ X8, 434554 |
(1671) 0x434548 LDUR X0, [X29, #264] |
(1671) 0x43454c BL 4ae530 |
(1671) 0x434550 STUR XZR, [X29, #264] |
(1671) 0x434554 LDUR X0, [X29, #256] |
(1671) 0x434558 BL 4ae530 |
(1671) 0x43455c LDR X8, [SP, #728] |
(1671) 0x434560 STUR XZR, [X29, #256] |
(1671) 0x434564 LDR X0, [X8, #8] |
(1671) 0x434568 BL 4ae530 |
(1671) 0x43456c LDR X8, [SP, #728] |
(1671) 0x434570 STR XZR, [X8, #8] |
(1671) 0x434574 LDR X8, [SP, #528] |
(1671) 0x434578 CMP X8, #2 |
(1671) 0x43457c B.LT 434594 |
(1671) 0x434580 LDR X8, [SP, #720] |
(1671) 0x434584 LDR X0, [X8, #8] |
(1671) 0x434588 BL 4ae530 |
(1671) 0x43458c LDR X8, [SP, #720] |
(1671) 0x434590 STR XZR, [X8, #8] |
(1671) 0x434594 LDR X24, [SP, #640] |
(1671) 0x434598 MOVZ W8, #2 |
(1671) 0x43459c STR X8, [SP, #648] |
(1671) 0x4345a0 CMP X24, #2 |
(1671) 0x4345a4 B.LE 434bc8 |
(1671) 0x4345a8 RDVL X9, #1 |
(1671) 0x4345ac ORR X22, XZR, XZR |
(1671) 0x4345b0 MOVZ W8, #2 |
(1671) 0x4345b4 MOVZ W26, #16 |
(1671) 0x4345b8 SUB X21, X29, #232 |
(1671) 0x4345bc STP XZR, X24, [SP, #368] |
(1671) 0x4345c0 ORR X19, XZR, XZR |
(1671) 0x4345c4 CNTW X25, ALL |
(1671) 0x4345c8 UBFM X27, X9, #4, #63 |
(1671) 0x4345cc PTRUE P0.D, ALL |
(1671) 0x4345d0 B 4345f8 |
0x4345d4 HINT #0 |
0x4345d8 HINT #0 |
0x4345dc HINT #0 |
(1679) 0x4345e0 LDR X9, [SP, #376] |
(1679) 0x4345e4 PTRUE P0.D, ALL |
(1679) 0x4345e8 ADD X8, X8, #1 |
(1679) 0x4345ec STR X8, [SP, #648] |
(1679) 0x4345f0 CMP X8, X9 |
(1679) 0x4345f4 B.GE 434bc0 |
(1679) 0x4345f8 LDR X9, [SP, #528] |
(1679) 0x4345fc CMP X9, #2 |
(1679) 0x434600 B.LT 434a04 |
(1679) 0x434604 LDR X9, [SP, #400] |
(1679) 0x434608 LDUR X23, [X29, #328] |
(1679) 0x43460c LDR X8, [X9, X8,LSL #3] |
(1679) 0x434610 LDR X9, [SP, #368] |
(1679) 0x434614 LDR X8, [X8, X23,LSL #3] |
(1679) 0x434618 CMP X8, X9 |
(1679) 0x43461c STR X8, [SP, #504] |
(1679) 0x434620 B.LE 434648 |
(1679) 0x434624 ORR X0, XZR, X19 |
(1679) 0x434628 BL 4ae530 |
(1679) 0x43462c LDR X0, [SP, #504] |
(1679) 0x434630 MOVZ W1, #8 |
(1679) 0x434634 BL 4ae430 |
(1679) 0x434638 LDR X8, [SP, #504] |
(1679) 0x43463c LDUR X23, [X29, #328] |
(1679) 0x434640 PTRUE P0.D, ALL |
(1679) 0x434644 ORR X19, XZR, X0 |
(1679) 0x434648 STP X22, X8, [SP, #360] |
(1679) 0x43464c CMP X23, #1 |
(1679) 0x434650 STR XZR, [SP, #560] |
(1679) 0x434654 B.LT 434964 |
(1679) 0x434658 LDP X11, X10, [X29, #824] |
(1679) 0x43465c LDR X8, [SP, #648] |
(1679) 0x434660 LDR X12, [SP, #584] |
(1679) 0x434664 ORR X4, XZR, XZR |
(1679) 0x434668 ORR X9, XZR, XZR |
(1679) 0x43466c ADD X14, X19, #16 |
(1679) 0x434670 SUB X13, X8, #1 |
(1679) 0x434674 STR X10, [SP, #424] |
(1679) 0x434678 B 434690 |
0x43467c HINT #0 |
(1680) 0x434680 LDR X10, [SP, #424] |
(1680) 0x434684 CMP X9, X23 |
(1680) 0x434688 STR X9, [SP, #560] |
(1680) 0x43468c B.EQ 434964 |
(1680) 0x434690 LDR X15, [X10, X9,LSL #3] |
(1680) 0x434694 ADD X9, X9, #1 |
(1680) 0x434698 LDR X16, [X10, X9,LSL #3] |
(1680) 0x43469c CMP X15, X16 |
(1680) 0x4346a0 B.GE 434684 |
(1680) 0x4346a4 LDP X17, X18, [X29, #880] |
(1680) 0x4346a8 LDP X0, X1, [X29, #856] |
(1680) 0x4346ac ADD X2, X18, #16 |
(1680) 0x4346b0 ADD X3, X1, #16 |
(1680) 0x4346b4 B 4346d0 |
0x4346b8 HINT #0 |
0x4346bc HINT #0 |
(1681) 0x4346c0 ORR X4, XZR, X6 |
(1681) 0x4346c4 ADD X15, X15, #1 |
(1681) 0x4346c8 CMP X15, X16 |
(1681) 0x4346cc B.EQ 434680 |
(1681) 0x4346d0 LDR X5, [X11, X15,LSL #3] |
(1681) 0x4346d4 LDR X8, [X12, X5,LSL #3] |
(1681) 0x4346d8 CMP X8, X13 |
(1681) 0x4346dc B.NE 4346c4 |
(1681) 0x4346e0 ADD X7, X5, #1 |
(1681) 0x4346e4 LDR X28, [X17, X5,LSL #3] |
(1681) 0x4346e8 LDR X22, [X17, X7,LSL #3] |
(1681) 0x4346ec SUBS X8, X22, X28 |
(1681) 0x4346f0 B.LE 4347c0 |
(1681) 0x4346f4 CMP X25, #16 |
(1681) 0x4346f8 CSEL X10, X25, X26, #8 |
(1681) 0x4346fc CMP X8, X10 |
(1681) 0x434700 B.CC 434718 |
(1681) 0x434704 ADD X10, X19, X4,LSL #3 |
(1681) 0x434708 ADD X6, X18, X28,LSL #3 |
(1681) 0x43470c SUB X10, X10, X6 |
(1681) 0x434710 CMP X10, X27,LSL #5 |
(1681) 0x434714 B.CS 434898 |
(1681) 0x434718 ORR X6, XZR, X4 |
(1681) 0x43471c ORR X21, XZR, X28 |
(1681) 0x434720 SUB W8, W22, W21 |
(1681) 0x434724 ORR X4, XZR, X21 |
(1681) 0x434728 ANDS X20, X8, #4160 |
(1681) 0x43472c B.EQ 434758 |
(1681) 0x434730 HINT #0 |
(1681) 0x434734 HINT #0 |
(1681) 0x434738 HINT #0 |
(1681) 0x43473c HINT #0 |
(1686) 0x434740 LDR D0, [X18, X4,LSL #3] |
(1686) 0x434744 ADD X4, X4, #1 |
(1686) 0x434748 SUBS X20, X20, #1 |
(1686) 0x43474c STR D0, [X19, X6,LSL #3] |
(1686) 0x434750 ADD X6, X6, #1 |
(1686) 0x434754 B.NE 434740 |
(1681) 0x434758 ORN X8, XZR, X21 |
(1681) 0x43475c ADD X8, X22, X8 |
(1681) 0x434760 CMP X8, #3 |
(1681) 0x434764 B.CC 4347c4 |
(1681) 0x434768 SUB X22, X22, X4 |
(1681) 0x43476c ADD X4, X2, X4,LSL #3 |
(1681) 0x434770 ADD X20, X14, X6,LSL #3 |
(1681) 0x434774 HINT #0 |
(1681) 0x434778 HINT #0 |
(1681) 0x43477c HINT #0 |
(1685) 0x434780 LDUR D0, [X4, #496] |
(1685) 0x434784 ADD X6, X6, #4 |
(1685) 0x434788 SUBS X22, X22, #4 |
(1685) 0x43478c STUR D0, [X20, #496] |
(1685) 0x434790 LDUR D0, [X4, #504] |
(1685) 0x434794 STUR D0, [X20, #504] |
(1685) 0x434798 LDR D0, [X4] |
(1685) 0x43479c STR D0, [X20] |
(1685) 0x4347a0 LDR D0, [X4, #8] |
(1685) 0x4347a4 ADD X4, X4, #32 |
(1685) 0x4347a8 STR D0, [X20, #8] |
(1685) 0x4347ac ADD X20, X20, #32 |
(1685) 0x4347b0 B.NE 434780 |
(1681) 0x4347b4 B 4347c4 |
0x4347b8 HINT #0 |
0x4347bc HINT #0 |
(1681) 0x4347c0 ORR X6, XZR, X4 |
(1681) 0x4347c4 LDR X21, [X0, X5,LSL #3] |
(1681) 0x4347c8 LDR X5, [X0, X7,LSL #3] |
(1681) 0x4347cc SUBS X8, X5, X21 |
(1681) 0x4347d0 B.LE 4346c0 |
(1681) 0x4347d4 CMP X25, #16 |
(1681) 0x4347d8 CSEL X10, X25, X26, #8 |
(1681) 0x4347dc CMP X8, X10 |
(1681) 0x4347e0 B.CC 4347f8 |
(1681) 0x4347e4 ADD X10, X19, X6,LSL #3 |
(1681) 0x4347e8 ADD X4, X1, X21,LSL #3 |
(1681) 0x4347ec SUB X10, X10, X4 |
(1681) 0x4347f0 CMP X10, X27,LSL #5 |
(1681) 0x4347f4 B.CS 434904 |
(1681) 0x4347f8 ORR X4, XZR, X6 |
(1681) 0x4347fc ORR X7, XZR, X21 |
(1681) 0x434800 SUB W8, W5, W7 |
(1681) 0x434804 ORR X6, XZR, X7 |
(1681) 0x434808 ANDS X20, X8, #4160 |
(1681) 0x43480c B.EQ 434838 |
(1681) 0x434810 HINT #0 |
(1681) 0x434814 HINT #0 |
(1681) 0x434818 HINT #0 |
(1681) 0x43481c HINT #0 |
(1683) 0x434820 LDR D0, [X1, X6,LSL #3] |
(1683) 0x434824 ADD X6, X6, #1 |
(1683) 0x434828 SUBS X20, X20, #1 |
(1683) 0x43482c STR D0, [X19, X4,LSL #3] |
(1683) 0x434830 ADD X4, X4, #1 |
(1683) 0x434834 B.NE 434820 |
(1681) 0x434838 ORN X8, XZR, X7 |
(1681) 0x43483c ADD X8, X5, X8 |
(1681) 0x434840 CMP X8, #3 |
(1681) 0x434844 B.CC 4346c4 |
(1681) 0x434848 SUB X5, X5, X6 |
(1681) 0x43484c ADD X6, X3, X6,LSL #3 |
(1681) 0x434850 ADD X7, X14, X4,LSL #3 |
(1681) 0x434854 HINT #0 |
(1681) 0x434858 HINT #0 |
(1681) 0x43485c HINT #0 |
(1682) 0x434860 LDUR D0, [X6, #496] |
(1682) 0x434864 ADD X4, X4, #4 |
(1682) 0x434868 SUBS X5, X5, #4 |
(1682) 0x43486c STUR D0, [X7, #496] |
(1682) 0x434870 LDUR D0, [X6, #504] |
(1682) 0x434874 STUR D0, [X7, #504] |
(1682) 0x434878 LDR D0, [X6] |
(1682) 0x43487c STR D0, [X7] |
(1682) 0x434880 LDR D0, [X6, #8] |
(1682) 0x434884 ADD X6, X6, #32 |
(1682) 0x434888 STR D0, [X7, #8] |
(1682) 0x43488c ADD X7, X7, #32 |
(1682) 0x434890 B.NE 434860 |
(1681) 0x434894 B 4346c4 |
(1681) 0x434898 UDIV X10, X8, X25 |
(1681) 0x43489c ORR X24, XZR, XZR |
(1681) 0x4348a0 MADD X20, X10, X25, XZR |
(1681) 0x4348a4 UBFM X10, X28, #61, #60 |
(1681) 0x4348a8 SUB X30, X8, X20 |
(1681) 0x4348ac UBFM X8, X4, #61, #60 |
(1681) 0x4348b0 ADD X6, X4, X20 |
(1681) 0x4348b4 ADD X21, X28, X20 |
(1681) 0x4348b8 ADD X28, X18, X10 |
(1681) 0x4348bc ADDVL X10, X10, #1 |
(1681) 0x4348c0 ADD X4, X19, X8 |
(1681) 0x4348c4 ADDVL X8, X8, #1 |
(1681) 0x4348c8 ADD X10, X18, X10 |
(1681) 0x4348cc ADD X8, X19, X8 |
(1681) 0x4348d0 HINT #0 |
(1681) 0x4348d4 HINT #0 |
(1681) 0x4348d8 HINT #0 |
(1681) 0x4348dc HINT #0 |
(1687) 0x4348e0 LD1D {Z0.D}, P0/Z, [X28, X24,LSL #3] |
(1687) 0x4348e4 LD1D {Z1.D}, P0/Z, [X10, X24,LSL #3] |
(1687) 0x4348e8 ST1D {Z0.D}, P0, [X4, X24,LSL #3] |
(1687) 0x4348ec ST1D {Z1.D}, P0, [X8, X24,LSL #3] |
(1687) 0x4348f0 ADD X24, X24, X25 |
(1687) 0x4348f4 CMP X20, X24 |
(1687) 0x4348f8 B.NE 4348e0 |
(1681) 0x4348fc CBNZ X30, 434720 |
(1681) 0x434900 B 4347c4 |
(1681) 0x434904 UDIV X10, X8, X25 |
(1681) 0x434908 ORR X24, XZR, XZR |
(1681) 0x43490c MADD X20, X10, X25, XZR |
(1681) 0x434910 UBFM X10, X21, #61, #60 |
(1681) 0x434914 SUB X22, X8, X20 |
(1681) 0x434918 UBFM X8, X6, #61, #60 |
(1681) 0x43491c ADD X4, X6, X20 |
(1681) 0x434920 ADD X7, X21, X20 |
(1681) 0x434924 ADD X21, X1, X10 |
(1681) 0x434928 ADDVL X10, X10, #1 |
(1681) 0x43492c ADD X6, X19, X8 |
(1681) 0x434930 ADDVL X8, X8, #1 |
(1681) 0x434934 ADD X10, X1, X10 |
(1681) 0x434938 ADD X8, X19, X8 |
(1681) 0x43493c HINT #0 |
(1684) 0x434940 LD1D {Z0.D}, P0/Z, [X21, X24,LSL #3] |
(1684) 0x434944 LD1D {Z1.D}, P0/Z, [X10, X24,LSL #3] |
(1684) 0x434948 ST1D {Z0.D}, P0, [X6, X24,LSL #3] |
(1684) 0x43494c ST1D {Z1.D}, P0, [X8, X24,LSL #3] |
(1684) 0x434950 ADD X24, X24, X25 |
(1684) 0x434954 CMP X20, X24 |
(1684) 0x434958 B.NE 434940 |
(1681) 0x43495c CBNZ X22, 434800 |
(1681) 0x434960 B 4346c4 |
(1679) 0x434964 LDP X11, X9, [SP, #392] |
(1679) 0x434968 LDR X8, [SP, #648] |
(1679) 0x43496c LDP X12, X10, [SP, #408] |
(1679) 0x434970 LDR X3, [SP, #568] |
(1679) 0x434974 STR X23, [X11, #8] |
(1679) 0x434978 LDR X9, [X9, X8,LSL #3] |
(1679) 0x43497c STR X10, [X11, #40] |
(1679) 0x434980 STR X9, [X11, #24] |
(1679) 0x434984 LDR X9, [X12, X8,LSL #3] |
(1679) 0x434988 STR X9, [X11, #56] |
(1679) 0x43498c LDR X8, [X12, X8,LSL #3] |
(1679) 0x434990 LDR X22, [X8, X10,LSL #3] |
(1679) 0x434994 LDR X8, [SP, #360] |
(1679) 0x434998 CMP X22, X8 |
(1679) 0x43499c B.LE 4349c0 |
(1679) 0x4349a0 ORR X0, XZR, X3 |
(1679) 0x4349a4 BL 4ae530 |
(1679) 0x4349a8 ORR X0, XZR, X22 |
(1679) 0x4349ac MOVZ W1, #8 |
(1679) 0x4349b0 STR XZR, [SP, #568] |
(1679) 0x4349b4 BL 4ae430 |
(1679) 0x4349b8 ORR X3, XZR, X0 |
(1679) 0x4349bc STR X0, [SP, #568] |
(1679) 0x4349c0 LDR X1, [SP, #392] |
(1679) 0x4349c4 ORR X2, XZR, X19 |
(1679) 0x4349c8 MOVZ W0, #1 |
(1679) 0x4349cc SUB X21, X29, #232 |
(1679) 0x4349d0 BL 485620 |
(1679) 0x4349d4 BL 485a00 |
(1679) 0x4349d8 LDR X8, [SP, #648] |
(1679) 0x4349dc LDR X20, [SP, #400] |
(1679) 0x4349e0 LDR X0, [X20, X8,LSL #3] |
(1679) 0x4349e4 BL 4ae530 |
(1679) 0x4349e8 LDR X8, [SP, #648] |
(1679) 0x4349ec STR XZR, [X20, X8,LSL #3] |
(1679) 0x4349f0 LDR X20, [SP, #408] |
(1679) 0x4349f4 LDR X0, [X20, X8,LSL #3] |
(1679) 0x4349f8 BL 4ae530 |
(1679) 0x4349fc LDR X8, [SP, #648] |
(1679) 0x434a00 STR XZR, [X20, X8,LSL #3] |
(1679) 0x434a04 LDR X9, [SP, #752] |
(1679) 0x434a08 ADD X3, SP, #632 |
(1679) 0x434a0c SUB X4, X29, #128 |
(1679) 0x434a10 ADD X5, SP, #624 |
(1679) 0x434a14 ADD X6, SP, #480 |
(1679) 0x434a18 ADD X7, SP, #616 |
(1679) 0x434a1c ADRP X0, |
(1679) 0x434a20 ADD X0, X0, #840 |
(1679) 0x434a24 MOVZ W1, #42 |
(1679) 0x434a28 ADRP X2, 438a28 |
(1679) 0x434a2c ADD X2, X2, #224 |
(1679) 0x434a30 ADD X8, X9, X8,LSL #3 |
(1679) 0x434a34 LDP X8, X9, [X8] |
(1679) 0x434a38 SUB X8, X9, X8 |
(1679) 0x434a3c STR X8, [SP, #464] |
(1679) 0x434a40 SUB X8, X29, #224 |
(1679) 0x434a44 STP X8, X21, [SP, #280] |
(1679) 0x434a48 ADD X8, SP, #568 |
(1679) 0x434a4c STR X8, [SP, #272] |
(1679) 0x434a50 SUB X8, X29, #72 |
(1679) 0x434a54 STR X8, [SP, #264] |
(1679) 0x434a58 ADD X8, SP, #712 |
(1679) 0x434a5c STR X8, [SP, #256] |
(1679) 0x434a60 ADD X8, SP, #696 |
(1679) 0x434a64 STR X8, [SP, #248] |
(1679) 0x434a68 SUB X8, X29, #208 |
(1679) 0x434a6c STR X8, [SP, #240] |
(1679) 0x434a70 SUB X8, X29, #88 |
(1679) 0x434a74 STR X8, [SP, #232] |
(1679) 0x434a78 ADD X8, SP, #680 |
(1679) 0x434a7c STR X8, [SP, #224] |
(1679) 0x434a80 ADD X8, X29, #104 |
(1679) 0x434a84 STR X8, [SP, #216] |
(1679) 0x434a88 SUB X8, X29, #80 |
(1679) 0x434a8c STR X8, [SP, #208] |
(1679) 0x434a90 SUB X8, X29, #40 |
(1679) 0x434a94 STR X8, [SP, #200] |
(1679) 0x434a98 SUB X8, X29, #32 |
(1679) 0x434a9c STR X8, [SP, #192] |
(1679) 0x434aa0 SUB X8, X29, #8 |
(1679) 0x434aa4 STR X8, [SP, #184] |
(1679) 0x434aa8 SUB X8, X29, #48 |
(1679) 0x434aac STR X8, [SP, #176] |
(1679) 0x434ab0 SUB X8, X29, #64 |
(1679) 0x434ab4 STR X8, [SP, #168] |
(1679) 0x434ab8 SUB X8, X29, #56 |
(1679) 0x434abc STR X8, [SP, #160] |
(1679) 0x434ac0 ADD X8, SP, #576 |
(1679) 0x434ac4 STR X8, [SP, #152] |
(1679) 0x434ac8 SUB X8, X29, #120 |
(1679) 0x434acc STR X8, [SP, #144] |
(1679) 0x434ad0 SUB X8, X29, #112 |
(1679) 0x434ad4 STR X8, [SP, #136] |
(1679) 0x434ad8 ADD X8, SP, #584 |
(1679) 0x434adc STR X8, [SP, #128] |
(1679) 0x434ae0 SUB X8, X29, #104 |
(1679) 0x434ae4 STR X8, [SP, #120] |
(1679) 0x434ae8 SUB X8, X29, #96 |
(1679) 0x434aec STR X8, [SP, #112] |
(1679) 0x434af0 SUB X8, X29, #176 |
(1679) 0x434af4 STR X8, [SP, #104] |
(1679) 0x434af8 SUB X8, X29, #160 |
(1679) 0x434afc STR X8, [SP, #96] |
(1679) 0x434b00 ADD X8, SP, #720 |
(1679) 0x434b04 STR X8, [SP, #88] |
(1679) 0x434b08 SUB X8, X29, #168 |
(1679) 0x434b0c STR X8, [SP, #80] |
(1679) 0x434b10 ADD X8, SP, #736 |
(1679) 0x434b14 STR X8, [SP, #72] |
(1679) 0x434b18 SUB X8, X29, #152 |
(1679) 0x434b1c STR X8, [SP, #64] |
(1679) 0x434b20 SUB X8, X29, #136 |
(1679) 0x434b24 STR X8, [SP, #56] |
(1679) 0x434b28 ADD X8, SP, #728 |
(1679) 0x434b2c STR X8, [SP, #48] |
(1679) 0x434b30 SUB X8, X29, #144 |
(1679) 0x434b34 STR X8, [SP, #40] |
(1679) 0x434b38 ADD X8, SP, #744 |
(1679) 0x434b3c STR X8, [SP, #32] |
(1679) 0x434b40 ADD X8, SP, #760 |
(1679) 0x434b44 STR X8, [SP, #24] |
(1679) 0x434b48 ADD X8, SP, #464 |
(1679) 0x434b4c STR X8, [SP, #16] |
(1679) 0x434b50 ADD X8, SP, #648 |
(1679) 0x434b54 STR X8, [SP, #8] |
(1679) 0x434b58 ADD X8, SP, #752 |
(1679) 0x434b5c STR X8, [SP] |
(1679) 0x434b60 BL 40fa00 |
(1679) 0x434b64 LDR X8, [SP, #728] |
(1679) 0x434b68 LDR X9, [SP, #648] |
(1679) 0x434b6c LDR X0, [X8, X9,LSL #3] |
(1679) 0x434b70 BL 4ae530 |
(1679) 0x434b74 LDR X9, [SP, #728] |
(1679) 0x434b78 LDR X8, [SP, #648] |
(1679) 0x434b7c STR XZR, [X9, X8,LSL #3] |
(1679) 0x434b80 LDR X9, [SP, #528] |
(1679) 0x434b84 CMP X9, #2 |
(1679) 0x434b88 B.LT 4345e0 |
(1679) 0x434b8c LDR X9, [SP, #720] |
(1679) 0x434b90 LDR X0, [X9, X8,LSL #3] |
(1679) 0x434b94 BL 4ae530 |
(1679) 0x434b98 LDR X8, [SP, #720] |
(1679) 0x434b9c LDR X9, [SP, #648] |
(1679) 0x434ba0 STR XZR, [X8, X9,LSL #3] |
(1679) 0x434ba4 LDR X8, [SP, #712] |
(1679) 0x434ba8 LDR X0, [X8, X9,LSL #3] |
(1679) 0x434bac BL 4ae530 |
(1679) 0x434bb0 LDR X9, [SP, #712] |
(1679) 0x434bb4 LDR X8, [SP, #648] |
(1679) 0x434bb8 STR XZR, [X9, X8,LSL #3] |
(1679) 0x434bbc B 4345e0 |
(1671) 0x434bc0 LDR X24, [SP, #376] |
(1671) 0x434bc4 B 434bcc |
(1671) 0x434bc8 ORR X19, XZR, XZR |
(1671) 0x434bcc LDUR X0, [X29, #288] |
(1671) 0x434bd0 BL 4ae530 |
(1671) 0x434bd4 LDR X0, [SP, #400] |
(1671) 0x434bd8 STUR XZR, [X29, #288] |
(1671) 0x434bdc BL 4ae530 |
(1671) 0x434be0 LDR X0, [SP, #408] |
(1671) 0x434be4 BL 4ae530 |
(1671) 0x434be8 LDUR X0, [X29, #280] |
(1671) 0x434bec BL 4ae530 |
(1671) 0x434bf0 ORR X0, XZR, X19 |
(1671) 0x434bf4 STUR XZR, [X29, #280] |
(1671) 0x434bf8 BL 4ae530 |
(1671) 0x434bfc LDR X0, [SP, #568] |
(1671) 0x434c00 BL 4ae530 |
(1671) 0x434c04 LDR X0, [SP, #728] |
(1671) 0x434c08 STR XZR, [SP, #568] |
(1671) 0x434c0c BL 4ae530 |
(1671) 0x434c10 LDR X0, [SP, #720] |
(1671) 0x434c14 STR XZR, [SP, #728] |
(1671) 0x434c18 BL 4ae530 |
(1671) 0x434c1c LDR X0, [SP, #712] |
(1671) 0x434c20 STR XZR, [SP, #720] |
(1671) 0x434c24 BL 4ae530 |
(1671) 0x434c28 LDR X0, [SP, #744] |
(1671) 0x434c2c STR XZR, [SP, #712] |
(1671) 0x434c30 BL 4ae530 |
(1671) 0x434c34 LDR X0, [SP, #736] |
(1671) 0x434c38 STR XZR, [SP, #744] |
(1671) 0x434c3c BL 4ae530 |
(1671) 0x434c40 LDUR X0, [X29, #304] |
(1671) 0x434c44 STR XZR, [SP, #736] |
(1671) 0x434c48 BL 4ae530 |
(1671) 0x434c4c LDR X0, [SP, #696] |
(1671) 0x434c50 STUR XZR, [X29, #304] |
(1671) 0x434c54 BL 4ae530 |
(1671) 0x434c58 LDR X0, [SP, #592] |
(1671) 0x434c5c STR XZR, [SP, #696] |
(1671) 0x434c60 BL 4ae530 |
(1671) 0x434c64 LDR X0, [SP, #584] |
(1671) 0x434c68 STR XZR, [SP, #592] |
(1671) 0x434c6c BL 4ae530 |
(1671) 0x434c70 LDR X0, [SP, #576] |
(1671) 0x434c74 STR XZR, [SP, #584] |
(1671) 0x434c78 BL 4ae530 |
(1671) 0x434c7c LDR X0, [SP, #752] |
(1671) 0x434c80 STR XZR, [SP, #576] |
(1671) 0x434c84 BL 4ae530 |
(1671) 0x434c88 LDR X0, [SP, #760] |
(1671) 0x434c8c STR XZR, [SP, #752] |
(1671) 0x434c90 BL 4ae530 |
(1671) 0x434c94 LDR X0, [SP, #688] |
(1671) 0x434c98 STR XZR, [SP, #760] |
(1671) 0x434c9c BL 4ae530 |
(1671) 0x434ca0 LDR X0, [SP, #680] |
(1671) 0x434ca4 STR XZR, [SP, #688] |
(1671) 0x434ca8 BL 4ae530 |
(1671) 0x434cac LDR X8, [SP, #528] |
(1671) 0x434cb0 STR XZR, [SP, #680] |
(1671) 0x434cb4 CMP X8, #2 |
(1671) 0x434cb8 B.LT 434cc4 |
(1671) 0x434cbc LDR X0, [SP, #392] |
(1671) 0x434cc0 BL 4ae530 |
(1671) 0x434cc4 LDP X8, X4, [SP, #312] |
(1671) 0x434cc8 LDR X9, [SP, #632] |
(1671) 0x434ccc LDR X2, [SP, #520] |
(1671) 0x434cd0 ORR X5, XZR, XZR |
(1671) 0x434cd4 LDR X0, [SP, #384] |
(1671) 0x434cd8 LDR X1, [X8, #8] |
(1671) 0x434cdc LDR X3, [X8, #104] |
(1671) 0x434ce0 LDUR X8, [X29, #368] |
(1671) 0x434ce4 LDR X6, [X8, X9,LSL #3] |
(1671) 0x434ce8 LDUR X8, [X29, #344] |
(1671) 0x434cec LDR X7, [X8, X9,LSL #3] |
(1671) 0x434cf0 BL 48f500 |
(1671) 0x434cf4 LDR X20, [X0, #56] |
(1671) 0x434cf8 LDUR X8, [X29, #376] |
(1671) 0x434cfc LDR X1, [SP, #304] |
(1671) 0x434d00 ORR X19, XZR, X0 |
(1671) 0x434d04 FCMP D8, #0 |
(1671) 0x434d08 STR X8, [X20, #48] |
(1671) 0x434d0c LDUR X8, [X29, #368] |
(1671) 0x434d10 STR X8, [X20] |
(1671) 0x434d14 LDUR X8, [X29, #360] |
(1671) 0x434d18 STR X8, [X20, #8] |
(1671) 0x434d1c LDUR X8, [X29, #352] |
(1671) 0x434d20 LDR X22, [X0, #64] |
(1671) 0x434d24 STR X8, [X22, #48] |
(1671) 0x434d28 LDUR X8, [X29, #344] |
(1671) 0x434d2c STR X8, [X22] |
(1671) 0x434d30 LDUR X8, [X29, #336] |
(1671) 0x434d34 STR X8, [X22, #8] |
(1671) 0x434d38 STR XZR, [X0, #136] |
(1671) 0x434d3c B.NE 434d60 |
(1671) 0x434d40 CBNZ X1, 434d60 |
(1671) 0x434d44 LDUR X8, [X29, #344] |
(1671) 0x434d48 LDR X9, [SP, #632] |
(1671) 0x434d4c LDR X20, [X8, X9,LSL #3] |
(1671) 0x434d50 STR XZR, [SP, #472] |
(1671) 0x434d54 STR X20, [SP, #496] |
(1671) 0x434d58 CBNZ X20, 434da0 |
(1671) 0x434d5c B 434fb4 |
(1671) 0x434d60 ORR X0, XZR, X19 |
(1671) 0x434d64 FMOV D0, D8 |
(1671) 0x434d68 BL 429c50 |
(1671) 0x434d6c LDR X8, [X20, #48] |
(1671) 0x434d70 STUR X8, [X29, #376] |
(1671) 0x434d74 LDP X8, X9, [X20] |
(1671) 0x434d78 STP X9, X8, [X29, #872] |
(1671) 0x434d7c LDR X8, [X22, #48] |
(1671) 0x434d80 STUR X8, [X29, #352] |
(1671) 0x434d84 LDP X8, X9, [X22] |
(1671) 0x434d88 STP X9, X8, [X29, #848] |
(1671) 0x434d8c LDR X9, [SP, #632] |
(1671) 0x434d90 LDR X20, [X8, X9,LSL #3] |
(1671) 0x434d94 STR XZR, [SP, #472] |
(1671) 0x434d98 STR X20, [SP, #496] |
(1671) 0x434d9c CBZ X20, 434fb4 |
(1671) 0x434da0 LDR X8, [SP, #480] |
(1671) 0x434da4 LDUR X9, [X29, #384] |
(1671) 0x434da8 MOVZ W1, #8 |
(1671) 0x434dac CMP X8, X9 |
(1671) 0x434db0 CSEL X0, X8, X9, #12 |
(1671) 0x434db4 BL 4ae430 |
(1671) 0x434db8 STUR X0, [X29, #272] |
(1671) 0x434dbc ADRP X0, |
(1671) 0x434dc0 ADD X0, X0, #912 |
(1671) 0x434dc4 ADRP X2, 438dc4 |
(1671) 0x434dc8 ADD X2, X2, #3104 |
(1671) 0x434dcc ADD X3, SP, #480 |
(1671) 0x434dd0 SUB X4, X29, #240 |
(1671) 0x434dd4 MOVZ W1, #2 |
(1671) 0x434dd8 BL 40fa00 |
(1671) 0x434ddc CMP X20, #1 |
(1671) 0x434de0 STR XZR, [SP, #472] |
(1671) 0x434de4 STR XZR, [SP, #560] |
(1671) 0x434de8 B.LT 434e44 |
(1671) 0x434dec LDUR X8, [X29, #336] |
(1671) 0x434df0 LDUR X9, [X29, #272] |
(1671) 0x434df4 ORR X10, XZR, XZR |
(1671) 0x434df8 MOVZ W11, #1 |
(1671) 0x434dfc B 434e10 |
(1678) 0x434e00 ADD X10, X10, #1 |
(1678) 0x434e04 CMP X10, X20 |
(1678) 0x434e08 STR X10, [SP, #560] |
(1678) 0x434e0c B.GE 434e38 |
(1678) 0x434e10 LDR X12, [X8, X10,LSL #3] |
(1678) 0x434e14 LDR X13, [X9, X12,LSL #3] |
(1678) 0x434e18 CBNZ X13, 434e00 |
(1678) 0x434e1c LDR X10, [SP, #472] |
(1678) 0x434e20 ADD X10, X10, #1 |
(1678) 0x434e24 STR X10, [SP, #472] |
(1678) 0x434e28 STR X11, [X9, X12,LSL #3] |
(1678) 0x434e2c LDR X10, [SP, #560] |
(1678) 0x434e30 LDR X20, [SP, #496] |
(1678) 0x434e34 B 434e00 |
(1671) 0x434e38 LDR X20, [SP, #472] |
(1671) 0x434e3c LDR X24, [SP, #640] |
(1671) 0x434e40 B 434e48 |
(1671) 0x434e44 ORR X20, XZR, XZR |
(1671) 0x434e48 ORR X0, XZR, X20 |
(1671) 0x434e4c MOVZ W1, #8 |
(1671) 0x434e50 BL 4ae430 |
(1671) 0x434e54 LDR X8, [SP, #704] |
(1671) 0x434e58 STR X0, [SP, #672] |
(1671) 0x434e5c ORR X21, XZR, X0 |
(1671) 0x434e60 MOVZ W1, #8 |
(1671) 0x434e64 ADD X8, X8, X24,LSL #3 |
(1671) 0x434e68 LDUR X0, [X8, #504] |
(1671) 0x434e6c BL 4ae430 |
(1671) 0x434e70 STR X0, [SP, #664] |
(1671) 0x434e74 ADRP X0, |
(1671) 0x434e78 ADD X0, X0, #984 |
(1671) 0x434e7c ADRP X2, 438e7c |
(1671) 0x434e80 ADD X2, X2, #3360 |
(1671) 0x434e84 ADD X3, SP, #704 |
(1671) 0x434e88 ADD X4, SP, #640 |
(1671) 0x434e8c ADD X5, SP, #664 |
(1671) 0x434e90 MOVZ W1, #3 |
(1671) 0x434e94 BL 40fa00 |
(1671) 0x434e98 LDR X13, [SP, #640] |
(1671) 0x434e9c STR XZR, [SP, #560] |
(1671) 0x434ea0 CMP X13, #1 |
(1671) 0x434ea4 B.LE 434f48 |
(1671) 0x434ea8 LDR X9, [SP, #704] |
(1671) 0x434eac LDUR X10, [X29, #272] |
(1671) 0x434eb0 LDR X17, [SP, #432] |
(1671) 0x434eb4 ORR X8, XZR, XZR |
(1671) 0x434eb8 ORR X11, XZR, XZR |
(1671) 0x434ebc B 434ed8 |
(1676) 0x434ec0 LDR X13, [SP, #640] |
(1676) 0x434ec4 SUB X11, X13, #1 |
(1676) 0x434ec8 STR X15, [SP, #560] |
(1676) 0x434ecc CMP X15, X11 |
(1676) 0x434ed0 ORR X11, XZR, X15 |
(1676) 0x434ed4 B.GE 434f40 |
(1676) 0x434ed8 ADD X15, X11, #1 |
(1676) 0x434edc LDR X12, [X9, X11,LSL #3] |
(1676) 0x434ee0 LDR X14, [X9, X15,LSL #3] |
(1676) 0x434ee4 CMP X12, X14 |
(1676) 0x434ee8 B.GE 434ec4 |
(1676) 0x434eec LDR X13, [SP, #672] |
(1676) 0x434ef0 LDR X14, [SP, #664] |
(1676) 0x434ef4 B 434f14 |
0x434ef8 HINT #0 |
0x434efc HINT #0 |
(1677) 0x434f00 ADD X15, X11, #1 |
(1677) 0x434f04 ADD X12, X12, #1 |
(1677) 0x434f08 LDR X16, [X9, X15,LSL #3] |
(1677) 0x434f0c CMP X12, X16 |
(1677) 0x434f10 B.GE 434ec0 |
(1677) 0x434f14 LDR X15, [X10, X12,LSL #3] |
(1677) 0x434f18 CBZ X15, 434f00 |
(1677) 0x434f1c LDR X15, [X17, X11,LSL #3] |
(1677) 0x434f20 LDR X11, [X9, X11,LSL #3] |
(1677) 0x434f24 SUB X11, X15, X11,LSL #3 |
(1677) 0x434f28 LDR X11, [X11, X12,LSL #3] |
(1677) 0x434f2c STR X11, [X13, X8,LSL #3] |
(1677) 0x434f30 STR X11, [X14, X12,LSL #3] |
(1677) 0x434f34 ADD X8, X8, #1 |
(1677) 0x434f38 LDR X11, [SP, #560] |
(1677) 0x434f3c B 434f00 |
(1671) 0x434f40 LDR X21, [SP, #672] |
(1671) 0x434f44 LDR X20, [SP, #472] |
(1671) 0x434f48 ORR X0, XZR, X21 |
(1671) 0x434f4c ORR X1, XZR, XZR |
(1671) 0x434f50 SUB X2, X20, #1 |
(1671) 0x434f54 BL 4aebd0 |
(1671) 0x434f58 ADRP X0, |
(1671) 0x434f5c ADD X0, X0, #1056 |
(1671) 0x434f60 ADRP X2, 438f60 |
(1671) 0x434f64 ADD X2, X2, #3616 |
(1671) 0x434f68 ADD X3, SP, #704 |
(1671) 0x434f6c ADD X4, SP, #640 |
(1671) 0x434f70 ADD X5, SP, #664 |
(1671) 0x434f74 ADD X6, SP, #672 |
(1671) 0x434f78 ADD X7, SP, #472 |
(1671) 0x434f7c MOVZ W1, #5 |
(1671) 0x434f80 BL 40fa00 |
(1671) 0x434f84 ADRP X0, |
(1671) 0x434f88 ADD X0, X0, #1128 |
(1671) 0x434f8c ADRP X2, 438f8c |
(1671) 0x434f90 ADD X2, X2, #3872 |
(1671) 0x434f94 ADD X3, SP, #496 |
(1671) 0x434f98 SUB X4, X29, #176 |
(1671) 0x434f9c ADD X5, SP, #664 |
(1671) 0x434fa0 MOVZ W1, #3 |
(1671) 0x434fa4 BL 40fa00 |
(1671) 0x434fa8 LDUR X0, [X29, #272] |
(1671) 0x434fac BL 4ae530 |
(1671) 0x434fb0 STUR XZR, [X29, #272] |
(1671) 0x434fb4 LDR X8, [SP, #528] |
(1671) 0x434fb8 CMP X8, #2 |
(1671) 0x434fbc B.LT 43500c |
(1671) 0x434fc0 LDR X8, [SP, #640] |
(1671) 0x434fc4 STR XZR, [SP, #560] |
(1671) 0x434fc8 CMP X8, #2 |
(1671) 0x434fcc B.LT 43500c |
(1671) 0x434fd0 LDR X10, [SP, #432] |
(1671) 0x434fd4 ORR X8, XZR, XZR |
(1671) 0x434fd8 HINT #0 |
(1671) 0x434fdc HINT #0 |
(1675) 0x434fe0 LDR X0, [X10, X8,LSL #3] |
(1675) 0x434fe4 BL 4ae530 |
(1675) 0x434fe8 LDR X10, [SP, #432] |
(1675) 0x434fec LDR X8, [SP, #560] |
(1675) 0x434ff0 STR XZR, [X10, X8,LSL #3] |
(1675) 0x434ff4 ADD X8, X8, #1 |
(1675) 0x434ff8 LDR X9, [SP, #640] |
(1675) 0x434ffc STR X8, [SP, #560] |
(1675) 0x435000 SUB X9, X9, #1 |
(1675) 0x435004 CMP X8, X9 |
(1675) 0x435008 B.LT 434fe0 |
(1671) 0x43500c LDR X0, [SP, #664] |
(1671) 0x435010 BL 4ae530 |
(1671) 0x435014 LDR X0, [SP, #432] |
(1671) 0x435018 STR XZR, [SP, #664] |
(1671) 0x43501c BL 4ae530 |
(1671) 0x435020 LDR X0, [SP, #704] |
(1671) 0x435024 BL 4ae530 |
(1671) 0x435028 LDR X8, [SP, #472] |
(1671) 0x43502c STR XZR, [SP, #704] |
(1671) 0x435030 CBZ X8, 435040 |
(1671) 0x435034 LDR X9, [SP, #672] |
(1671) 0x435038 STR X9, [X19, #88] |
(1671) 0x43503c STR X8, [X22, #24] |
(1671) 0x435040 LDR X20, [X29, #112] |
(1671) 0x435044 LDR X8, [SP, #608] |
(1671) 0x435048 CBZ X8, 43506c |
(1671) 0x43504c ADRP X0, |
(1671) 0x435050 ADD X0, X0, #1200 |
(1671) 0x435054 ADRP X2, 439054 |
(1671) 0x435058 ADD X2, X2, #48 |
(1671) 0x43505c ADD X3, SP, #632 |
(1671) 0x435060 SUB X4, X29, #8 |
(1671) 0x435064 MOVZ W1, #2 |
(1671) 0x435068 BL 40fa00 |
(1671) 0x43506c LDR X8, [SP, #528] |
(1671) 0x435070 CMP X8, #2 |
(1671) 0x435074 B.LT 435080 |
(1671) 0x435078 ORR X0, XZR, X19 |
(1671) 0x43507c BL 486250 |
(1671) 0x435080 STR X19, [X20] |
(1671) 0x435084 ORR X0, XZR, XZR |
(1671) 0x435088 ADD SP, SP, #1008 |
(1671) 0x43508c LDP X20, X19, [SP, #96] |
(1671) 0x435090 LDP X22, X21, [SP, #80] |
(1671) 0x435094 LDP X24, X23, [SP, #64] |
(1671) 0x435098 LDP X26, X25, [SP, #48] |
(1671) 0x43509c LDP X28, X27, [SP, #32] |
(1671) 0x4350a0 LDP X29, X30, [SP, #16] |
(1671) 0x4350a4 LDR D8, [SP], #112 |
(1671) 0x4350a8 RET |
(1671) 0x4350ac ORR X8, XZR, XZR |
(1671) 0x4350b0 STR X8, [X0, #8] |
(1671) 0x4350b4 ORR X0, XZR, X21 |
(1671) 0x4350b8 MOVZ W1, #8 |
(1671) 0x4350bc BL 4ae430 |
(1671) 0x4350c0 ORR X19, XZR, X0 |
(1671) 0x4350c4 ADD X0, X21, #1 |
(1671) 0x4350c8 MOVZ W1, #8 |
(1671) 0x4350cc BL 4ae430 |
(1671) 0x4350d0 STR X0, [SP, #704] |
(1671) 0x4350d4 STR XZR, [X0] |
(1671) 0x4350d8 ORR X30, XZR, X19 |
(1671) 0x4350dc LDR X8, [SP, #616] |
(1671) 0x4350e0 STR X8, [X0, #8] |
(1671) 0x4350e4 STR X8, [SP, #480] |
(1671) 0x4350e8 STR X26, [X19] |
(1671) 0x4350ec LDR X9, [SP, #752] |
(1671) 0x4350f0 LDR X21, [SP, #424] |
(1671) 0x4350f4 LDP X1, X8, [X9, #8] |
(1671) 0x4350f8 CMP X1, X8 |
(1671) 0x4350fc STR X1, [SP, #560] |
(1671) 0x435100 B.GE 4332a0 |
(1672) 0x435104 LDR X11, [SP, #760] |
(1672) 0x435108 LDR X12, [SP, #744] |
(1672) 0x43510c LDR X13, [SP, #736] |
(1672) 0x435110 ORR X8, XZR, XZR |
(1672) 0x435114 ORR X10, XZR, XZR |
(1672) 0x435118 LDP X15, X14, [X29, #920] |
(1672) 0x43511c LDUR X16, [X29, #504] |
(1672) 0x435120 LDP X18, X17, [X29, #904] |
(1672) 0x435124 LDUR X0, [X29, #288] |
(1672) 0x435128 B 435144 |
(1672) 0x43512c LDR X1, [SP, #560] |
(1672) 0x435130 LDR X2, [X9, #16] |
(1672) 0x435134 ADD X1, X1, #1 |
(1672) 0x435138 CMP X1, X2 |
(1672) 0x43513c STR X1, [SP, #560] |
(1672) 0x435140 B.GE 4332a8 |
(1672) 0x435144 LDR X2, [X11, X1,LSL #3] |
(1672) 0x435148 STR X10, [X12, X2,LSL #3] |
(1672) 0x43514c STR X8, [X13, X2,LSL #3] |
(1672) 0x435150 ADD X1, X2, #1 |
(1672) 0x435154 LDR X3, [X14, X2,LSL #3] |
(1672) 0x435158 LDR X5, [X14, X1,LSL #3] |
(1672) 0x43515c CMP X3, X5 |
(1672) 0x435160 B.GE 4351c0 |
(1672) 0x435164 LDR X4, [SP, #592] |
(1672) 0x435168 LDR X6, [SP, #728] |
(1672) 0x43516c B 43518c |
0x435170 HINT #0 |
0x435174 HINT #0 |
0x435178 HINT #0 |
0x43517c HINT #0 |
(1674) 0x435180 ADD X3, X3, #1 |
(1674) 0x435184 CMP X3, X5 |
(1674) 0x435188 B.GE 4351c0 |
(1674) 0x43518c LDR X7, [X15, X3,LSL #3] |
(1674) 0x435190 LDR X19, [X16, X7,LSL #3] |
(1674) 0x435194 CMP X19, #1 |
(1674) 0x435198 B.NE 435180 |
(1674) 0x43519c LDR X5, [X4, X7,LSL #3] |
(1674) 0x4351a0 LDR X7, [X6, #8] |
(1674) 0x4351a4 STR X5, [X7, X10,LSL #3] |
(1674) 0x4351a8 ADD X10, X10, #1 |
(1674) 0x4351ac LDR X5, [X14, X1,LSL #3] |
(1674) 0x4351b0 B 435180 |
0x4351b4 HINT #0 |
0x4351b8 HINT #0 |
0x4351bc HINT #0 |
(1672) 0x4351c0 LDR X2, [X17, X2,LSL #3] |
(1672) 0x4351c4 LDR X4, [X17, X1,LSL #3] |
(1672) 0x4351c8 CMP X2, X4 |
(1672) 0x4351cc B.GE 43512c |
(1673) 0x4351d0 LDR X3, [SP, #688] |
(1673) 0x4351d4 LDR X5, [SP, #720] |
(1673) 0x4351d8 B 4351ec |
0x4351dc HINT #0 |
(1673) 0x4351e0 ADD X2, X2, #1 |
(1673) 0x4351e4 CMP X2, X4 |
(1673) 0x4351e8 B.GE 43512c |
(1673) 0x4351ec LDR X6, [X18, X2,LSL #3] |
(1673) 0x4351f0 LDR X7, [X0, X6,LSL #3] |
(1673) 0x4351f4 CMP X7, #1 |
(1673) 0x4351f8 B.NE 4351e0 |
(1673) 0x4351fc LDR X4, [X3, X6,LSL #3] |
(1673) 0x435200 LDR X6, [X5, #8] |
(1673) 0x435204 STR X4, [X6, X8,LSL #3] |
(1673) 0x435208 ADD X8, X8, #1 |
(1673) 0x43520c LDR X4, [X17, X1,LSL #3] |
(1673) 0x435210 B 4351e0 |
0x435214 HINT #0 |
0x435218 HINT #0 |
0x43521c HINT #0 |
| Coverage (%) | Name | Source Location | Module |
|---|
| Path / |
| Source file and lines | par_multi_interp.c:41-2060 |
| Module | exec |
| nb instructions | 559 |
| loop length | 2236 |
| nb stack references | 0 |
| front end | 61.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| cycles | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 61.13 |
| Overall L1 | 76.67 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB SP, SP, #1008 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X22, X23, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X1, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X5, X4, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMOV D8, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR X24, [X0, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X7, X0, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X3, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X22, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [X23, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X9, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STP XZR, X9, [X29, #952] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP XZR, X8, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X25, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X9, X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X28, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X8, X9, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X2, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR XZR, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #840] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #808] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #792] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #712] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #704] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #696] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #672] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #664] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #568] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X9, X10, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVN X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X8, XZR, [SP, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4b05a0 <hypre_NumThreads> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432650 <hypre_BoomerAMGBuildMultipass+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X1, SP, #528 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4afa30 <hypre_MPI_Comm_size> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4afa60 <hypre_MPI_Comm_rank> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #536] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X3, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X8, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 43268c <hypre_BoomerAMGBuildMultipass+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADRP X2, <4ef690> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #520 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X27, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X2, [X2, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4b0030 <hypre_MPI_Bcast> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 432784 <hypre_BoomerAMGBuildMultipass+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X21, 4326dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [X23, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X23, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X8, 4326e8 <hypre_BoomerAMGBuildMultipass+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X22, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 432700 <hypre_BoomerAMGBuildMultipass+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADRP X0, <4ec700> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 435708 <.omp_outlined..5+0xe8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #592 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X3, SP, #632 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #624 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #608 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40fa00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X10, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS X28, X8, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 432758 <hypre_BoomerAMGBuildMultipass+0x278> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 4327c8 <hypre_BoomerAMGBuildMultipass+0x2e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 4327cc <hypre_BoomerAMGBuildMultipass+0x2ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X8, 4327a8 <hypre_BoomerAMGBuildMultipass+0x2c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X19, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 486250 <hypre_MatvecCommPkgCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X19, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X21, 4326cc <hypre_BoomerAMGBuildMultipass+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 4326dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432804 <hypre_BoomerAMGBuildMultipass+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432834 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432834 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432890 <hypre_BoomerAMGBuildMultipass+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X11, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X8, X9, [X11, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X9, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X9, X10, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X10, [X29, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X11, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X9, X8, [X29, #832] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X9, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X10, X19, [X11, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X10, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 4328ac <hypre_BoomerAMGBuildMultipass+0x3cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4328c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR XZR, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4328c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4328ec <hypre_BoomerAMGBuildMultipass+0x40c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432954 <hypre_BoomerAMGBuildMultipass+0x474> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4329f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4329d4 <hypre_BoomerAMGBuildMultipass+0x4f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432990 <hypre_BoomerAMGBuildMultipass+0x4b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 4329f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X0, <4ec9f8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 435a00 <.omp_outlined..10+0x1c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #1104 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X19, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X3, X29, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #616 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #600 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40fa00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432a74 <hypre_BoomerAMGBuildMultipass+0x594> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432a7c <hypre_BoomerAMGBuildMultipass+0x59c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X12, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X23, X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X13, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432b74 <hypre_BoomerAMGBuildMultipass+0x694> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X11, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X18, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X15, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDUR X17, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X13, X13, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432b20 <hypre_BoomerAMGBuildMultipass+0x640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432bfc <hypre_BoomerAMGBuildMultipass+0x71c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X9, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X10, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432bac <hypre_BoomerAMGBuildMultipass+0x6cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432c20 <hypre_BoomerAMGBuildMultipass+0x740> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X3, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X22, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432c4c <hypre_BoomerAMGBuildMultipass+0x76c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432d1c <hypre_BoomerAMGBuildMultipass+0x83c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X9, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X11, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432c90 <hypre_BoomerAMGBuildMultipass+0x7b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae530 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 432db4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP X21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X0, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432db4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432d8c <hypre_BoomerAMGBuildMultipass+0x8ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X22, [SP, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X22, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STP XZR, XZR, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #512] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X9, [SP, #656] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432f0c <hypre_BoomerAMGBuildMultipass+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X11, X10, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X12, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X14, X13, [X29, #904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X15, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X18, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432e20 <hypre_BoomerAMGBuildMultipass+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [X8, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432f90 <hypre_BoomerAMGBuildMultipass+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X9, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432f4c <hypre_BoomerAMGBuildMultipass+0xa6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432fb4 <hypre_BoomerAMGBuildMultipass+0xad4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X3, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X3, <4effb8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X4, <4effbc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #544 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X8, X28, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #552 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X3, [X3, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X4, #3784] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X5, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4b0270 <hypre_MPI_Allreduce> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #552] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 4331f8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 4331f8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X21, <4efffc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X24, <4ef000> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [X21, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X24, [X24, #3784] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae530 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X21, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X21, [SP, #640] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #744] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 433284 <hypre_BoomerAMGBuildMultipass+0xda4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X19, 4350ac <hypre_BoomerAMGBuildMultipass+0x2bcc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B 4350b0 <hypre_BoomerAMGBuildMultipass+0x2bd0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X30, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X9, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X1, X8, [X9, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP X1, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 435104 <hypre_BoomerAMGBuildMultipass+0x2c24> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
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| Source file and lines | par_multi_interp.c:41-2060 |
| Module | exec |
| nb instructions | 559 |
| loop length | 2236 |
| nb stack references | 0 |
| front end | 61.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| cycles | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 61.13 |
| Overall L1 | 76.67 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB SP, SP, #1008 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X22, X23, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X1, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X5, X4, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMOV D8, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR X24, [X0, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X7, X0, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X3, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X22, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [X23, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X9, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STP XZR, X9, [X29, #952] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP XZR, X8, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X25, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X9, X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X28, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X8, X9, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X2, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR XZR, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #840] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #808] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #792] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #712] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #704] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #696] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #672] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #664] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #568] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X9, X10, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVN X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X8, XZR, [SP, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4b05a0 <hypre_NumThreads> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432650 <hypre_BoomerAMGBuildMultipass+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X1, SP, #528 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4afa30 <hypre_MPI_Comm_size> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4afa60 <hypre_MPI_Comm_rank> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #536] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X3, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X8, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 43268c <hypre_BoomerAMGBuildMultipass+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADRP X2, <4ef690> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #520 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X27, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X2, [X2, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4b0030 <hypre_MPI_Bcast> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 432784 <hypre_BoomerAMGBuildMultipass+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X21, 4326dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [X23, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X23, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X8, 4326e8 <hypre_BoomerAMGBuildMultipass+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X22, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 432700 <hypre_BoomerAMGBuildMultipass+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADRP X0, <4ec700> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #240 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 435708 <.omp_outlined..5+0xe8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #592 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X3, SP, #632 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #624 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #608 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40fa00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X10, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS X28, X8, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 432758 <hypre_BoomerAMGBuildMultipass+0x278> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 4327c8 <hypre_BoomerAMGBuildMultipass+0x2e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 4327cc <hypre_BoomerAMGBuildMultipass+0x2ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X8, 4327a8 <hypre_BoomerAMGBuildMultipass+0x2c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X19, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 486250 <hypre_MatvecCommPkgCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X19, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X21, 4326cc <hypre_BoomerAMGBuildMultipass+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 4326dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432804 <hypre_BoomerAMGBuildMultipass+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432834 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432834 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432890 <hypre_BoomerAMGBuildMultipass+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X11, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X8, X9, [X11, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X9, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X9, X10, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X10, [X29, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X11, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X9, X8, [X29, #832] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X9, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X10, X19, [X11, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X10, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 4328ac <hypre_BoomerAMGBuildMultipass+0x3cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4328c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR XZR, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4328c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432930 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4328ec <hypre_BoomerAMGBuildMultipass+0x40c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432954 <hypre_BoomerAMGBuildMultipass+0x474> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4329f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4329d4 <hypre_BoomerAMGBuildMultipass+0x4f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432990 <hypre_BoomerAMGBuildMultipass+0x4b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 4329f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X0, <4ec9f8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 435a00 <.omp_outlined..10+0x1c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #1104 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X19, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X3, X29, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #616 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #600 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40fa00 <@plt_start@+0x610> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432a74 <hypre_BoomerAMGBuildMultipass+0x594> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432a7c <hypre_BoomerAMGBuildMultipass+0x59c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X12, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X23, X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X13, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432b74 <hypre_BoomerAMGBuildMultipass+0x694> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X11, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X18, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X15, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDUR X17, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X13, X13, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432b20 <hypre_BoomerAMGBuildMultipass+0x640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432bfc <hypre_BoomerAMGBuildMultipass+0x71c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X9, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X10, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432bac <hypre_BoomerAMGBuildMultipass+0x6cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432c20 <hypre_BoomerAMGBuildMultipass+0x740> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X3, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X22, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 432c4c <hypre_BoomerAMGBuildMultipass+0x76c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432d1c <hypre_BoomerAMGBuildMultipass+0x83c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X9, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X11, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432c90 <hypre_BoomerAMGBuildMultipass+0x7b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae530 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 432db4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP X21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X0, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432db4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432d8c <hypre_BoomerAMGBuildMultipass+0x8ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X22, [SP, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X22, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STP XZR, XZR, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #512] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X9, [SP, #656] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432f0c <hypre_BoomerAMGBuildMultipass+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X11, X10, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X12, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X14, X13, [X29, #904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X15, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X18, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432e20 <hypre_BoomerAMGBuildMultipass+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [X8, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 432f90 <hypre_BoomerAMGBuildMultipass+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X9, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 432f4c <hypre_BoomerAMGBuildMultipass+0xa6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 432fb4 <hypre_BoomerAMGBuildMultipass+0xad4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X3, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 485620 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 485a00 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X3, <4effb8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X4, <4effbc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #544 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X8, X28, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #552 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X3, [X3, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X4, #3784] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X5, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4b0270 <hypre_MPI_Allreduce> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #552] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 4331f8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 4331f8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X21, <4efffc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X24, <4ef000> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [X21, #3928] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X24, [X24, #3784] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae530 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X21, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X21, [SP, #640] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #744] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 433284 <hypre_BoomerAMGBuildMultipass+0xda4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X19, 4350ac <hypre_BoomerAMGBuildMultipass+0x2bcc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4ae430 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B 4350b0 <hypre_BoomerAMGBuildMultipass+0x2bd0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X30, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X9, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X1, X8, [X9, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP X1, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 435104 <hypre_BoomerAMGBuildMultipass+0x2c24> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
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| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼hypre_BoomerAMGBuildMultipass– | 0.27 | 0.1 |
| ▼Loop 1730 - par_multi_interp.c:385-400 - exec– | 0.03 | 0.64 |
| ○Loop 1731 - par_multi_interp.c:385-395 - exec | 0 | 0.01 |
| ○Loop 1729 - par_multi_interp.c:399-400 - exec | 0.01 | 0.29 |
| ▼Loop 1719 - par_multi_interp.c:488-514 - exec– | 0.01 | 0.17 |
| ○Loop 1721 - par_multi_interp.c:491-498 - exec | 0.07 | 1.36 |
| ○Loop 1720 - par_multi_interp.c:501-508 - exec | 0 | 0 |
| ▼Loop 1732 - par_multi_interp.c:323-327 - exec– | 0 | 0 |
| ○Loop 1733 - par_multi_interp.c:326-327 - exec | 0 | 0 |
| ▼Loop 1725 - par_multi_interp.c:440-457 - exec– | 0 | 0 |
| ▼Loop 1726 - par_multi_interp.c:440-457 - exec– | 0 | 0 |
| ○Loop 1724 - par_multi_interp.c:440-457 - exec | 0 | 0 |
| ▼Loop 1717 - par_multi_interp.c:526-530 - exec– | 0 | 0 |
| ○Loop 1718 - par_multi_interp.c:529-530 - exec | 0 | 0 |
| ▼Loop 1711 - par_multi_interp.c:548-600 - exec– | 0 | 0 |
| ▼Loop 1714 - par_multi_interp.c:550-571 - exec– | 0.01 | 0.25 |
| ○Loop 1716 - par_multi_interp.c:554-557 - exec | 0.05 | 1.12 |
| ○Loop 1715 - par_multi_interp.c:568-571 - exec | 0 | 0 |
| ▼Loop 1712 - par_multi_interp.c:590-594 - exec– | 0 | 0 |
| ○Loop 1713 - par_multi_interp.c:593-594 - exec | 0 | 0 |
| ▼Loop 1734 - par_multi_interp.c:307-311 - exec– | 0 | 0 |
| ○Loop 1735 - par_multi_interp.c:310-311 - exec | 0 | 0 |
| ▼Loop 1673 - par_multi_interp.c:628-2060 - exec– | 0 | 0 |
| ▼Loop 1672 - par_multi_interp.c:628-2060 - exec– | 0.02 | 0.48 |
| ○Loop 1674 - par_multi_interp.c:651-655 - exec | 0.06 | 1.24 |
| ▼Loop 1671 - par_multi_interp.c:628-2060 - exec– | 0 | 0 |
| ○Loop 1697 - par_multi_interp.c:1158-1161 - exec | 0.01 | 0.16 |
| ○Loop 1678 - par_multi_interp.c:1962-1968 - exec | 0 | 0 |
| ▼Loop 1698 - par_multi_interp.c:693-891 - exec– | 0 | 0 |
| ▼Loop 1705 - par_multi_interp.c:733-758 - exec– | 0 | 0 |
| ▼Loop 1706 - par_multi_interp.c:735-758 - exec– | 0 | 0 |
| ▼Loop 1707 - par_multi_interp.c:749-758 - exec– | 0 | 0 |
| ○Loop 1708 - par_multi_interp.c:753-755 - exec | 0 | 0 |
| ○Loop 1709 - par_multi_interp.c:742-745 - exec | 0 | 0 |
| ▼Loop 1703 - par_multi_interp.c:773-784 - exec– | 0 | 0 |
| ○Loop 1704 - par_multi_interp.c:775-780 - exec | 0 | 0 |
| ○Loop 1699 - par_multi_interp.c:872-879 - exec | 0 | 0 |
| ○Loop 1710 - par_multi_interp.c:703-717 - exec | 0 | 0 |
| ▼Loop 1700 - par_multi_interp.c:823-856 - exec– | 0 | 0 |
| ▼Loop 1701 - par_multi_interp.c:829-856 - exec– | 0 | 0 |
| ○Loop 1702 - par_multi_interp.c:839-843 - exec | 0 | 0 |
| ▼Loop 1679 - par_multi_interp.c:1674-1888 - exec– | 0 | 0 |
| ▼Loop 1680 - par_multi_interp.c:1688-1705 - exec– | 0 | 0 |
| ▼Loop 1681 - par_multi_interp.c:1690-1705 - exec– | 0 | 0 |
| ○Loop 1685 - par_multi_interp.c:1697-1699 - exec | 0 | 0 |
| ○Loop 1683 - par_multi_interp.c:1703-1705 - exec | 0 | 0 |
| ○Loop 1687 - par_multi_interp.c:1699-1699 - exec | 0 | 0 |
| ○Loop 1686 - par_multi_interp.c:1697-1699 - exec | 0 | 0 |
| ○Loop 1682 - par_multi_interp.c:1703-1705 - exec | 0 | 0 |
| ○Loop 1684 - par_multi_interp.c:1705-1705 - exec | 0 | 0 |
| ▼Loop 1688 - par_multi_interp.c:1310-1566 - exec– | 0 | 0 |
| ▼Loop 1689 - par_multi_interp.c:1324-1338 - exec– | 0 | 0 |
| ▼Loop 1690 - par_multi_interp.c:1326-1338 - exec– | 0 | 0 |
| ○Loop 1695 - par_multi_interp.c:1333-1334 - exec | 0 | 0 |
| ○Loop 1691 - par_multi_interp.c:1337-1338 - exec | 0 | 0 |
| ○Loop 1693 - par_multi_interp.c:1338-1338 - exec | 0 | 0 |
| ○Loop 1696 - par_multi_interp.c:1334-1334 - exec | 0 | 0 |
| ○Loop 1692 - par_multi_interp.c:1337-1338 - exec | 0 | 0 |
| ○Loop 1694 - par_multi_interp.c:1333-1334 - exec | 0 | 0 |
| ○Loop 1675 - par_multi_interp.c:2016-2017 - exec | 0 | 0 |
| ▼Loop 1676 - par_multi_interp.c:1982-1989 - exec– | 0 | 0 |
| ○Loop 1677 - par_multi_interp.c:1984-1989 - exec | 0 | 0 |
| ▼Loop 1722 - par_multi_interp.c:466-468 - exec– | 0 | 0 |
| ○Loop 1723 - par_multi_interp.c:466-468 - exec | 0 | 0 |
| ▼Loop 1727 - par_multi_interp.c:415-423 - exec– | 0 | 0 |
| ○Loop 1728 - par_multi_interp.c:418-423 - exec | 0 | 0 |
| ○Loop 1736 - par_multi_interp.c:205-208 - exec | 0 | 0 |