OV - exec - Function hypre

	Function: hypre_qsort2abs	Module: exec	Source: par_interp.c:3180-3192	Coverage: 0.06%

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3180 - 3192

--------------------------------------------------------------------------------

3180:    if (left >= right)

3181:       return;

3182:    hypre_swap2( v, w, left, (left+right)/2);

3183:    last = left;

3184:    for (i = left+1; i <= right; i++)

3185:       if (fabs(w[i]) > fabs(w[left]))

3186:       {

3187:          hypre_swap2(v, w, ++last, i);

3188:       }

3189:    hypre_swap2(v, w, left, last);

3190:    hypre_qsort2abs(v, w, left, last-1);

3191:    hypre_qsort2abs(v, w, last+1, right);

3192: }

0x42de50 CMP	X2, X3

0x42de54 B.GE	42df58

0x42de58 STP	X29, X30, [SP, #944]!

0x42de5c STR	X25, [SP, #16]

0x42de60 STP	X24, X23, [SP, #32]

0x42de64 STP	X22, X21, [SP, #48]

0x42de68 STP	X20, X19, [SP, #64]

0x42de6c ADD	X29, SP, #0

0x42de70 ORR	X19, XZR, X3

0x42de74 ORR	X22, XZR, X2

0x42de78 ORR	X20, XZR, X1

0x42de7c ORR	X21, XZR, X0

0x42de80 SUB	X25, XZR, X3

0x42de84 B	42debc

  (1461) 0x42de88 ORR	X0, XZR, X21

  (1461) 0x42de8c ORR	X1, XZR, X20

  (1461) 0x42de90 ORR	X2, XZR, X22

  (1461) 0x42de94 ORR	X3, XZR, X23

  (1461) 0x42de98 BL	4ae6e0

  (1461) 0x42de9c ORR	X0, XZR, X21

  (1461) 0x42dea0 ORR	X1, XZR, X20

  (1461) 0x42dea4 SUB	X3, X23, #1

  (1461) 0x42dea8 ORR	X2, XZR, X22

  (1461) 0x42deac BL	42de50

  (1461) 0x42deb0 ADD	X22, X23, #1

  (1461) 0x42deb4 CMP	X22, X19

  (1461) 0x42deb8 B.GE	42df44

  (1461) 0x42debc ADD	X8, X22, X19

  (1461) 0x42dec0 ORR	X0, XZR, X21

  (1461) 0x42dec4 CMP	X8, #0

  (1461) 0x42dec8 ORR	X1, XZR, X20

  (1461) 0x42decc ORR	X2, XZR, X22

  (1461) 0x42ded0 CSINC	X8, X8, X8, #10

  (1461) 0x42ded4 SBFM	X3, X8, #1, #63

  (1461) 0x42ded8 BL	4ae6e0

  (1461) 0x42dedc ORR	X23, XZR, X22

  (1461) 0x42dee0 CMP	X22, X19

  (1461) 0x42dee4 B.GE	42de88

(1462) 0x42dee8 ORR	X23, XZR, X22

(1462) 0x42deec ADD	X24, X22, #1

(1462) 0x42def0 B	42df10

0x42def4 HINT	#0

0x42def8 HINT	#0

0x42defc HINT	#0

(1462) 0x42df00 ADD	X24, X24, #1

(1462) 0x42df04 ADD	X8, X25, X24

(1462) 0x42df08 CMP	X8, #1

(1462) 0x42df0c B.EQ	42de88

(1462) 0x42df10 LDR	D0, [X20, X24,LSL #3]

(1462) 0x42df14 LDR	D1, [X20, X22,LSL #3]

(1462) 0x42df18 FABS	D0, D0

(1462) 0x42df1c FABS	D1, D1

(1462) 0x42df20 FCMP	D0, D1

(1462) 0x42df24 B.LE	42df00

(1462) 0x42df28 ADD	X23, X23, #1

(1462) 0x42df2c ORR	X0, XZR, X21

(1462) 0x42df30 ORR	X1, XZR, X20

(1462) 0x42df34 ORR	X3, XZR, X24

(1462) 0x42df38 ORR	X2, XZR, X23

(1462) 0x42df3c BL	4ae6e0

(1462) 0x42df40 B	42df00

0x42df44 LDP	X20, X19, [SP, #64]

0x42df48 LDP	X22, X21, [SP, #48]

0x42df4c LDP	X24, X23, [SP, #32]

0x42df50 LDR	X25, [SP, #16]

0x42df54 LDP	X29, X30, [SP], #80

0x42df58 RET

0x42df5c HINT	#0

Coverage (%)	Name	Source Location	Module
►50.00+	hypre_qsort2abs	par_interp.c:3191	exec
○	hypre_qsort2abs	par_interp.c:3191	exec
○	.omp_outlined..46	par_interp.c:2912	exec
○	__kmp_invoke_microtask		libomp.so
►50.00+	.omp_outlined..46	par_interp.c:2912	exec
○	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_interp.c:3180-3192
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3180-3192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.88 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50
cycles	1.50	1.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

21% of peak load performance is reached (20.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42de50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42df58 <hypre_qsort2abs+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42debc <hypre_qsort2abs+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	par_interp.c:3180-3192
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3180-3192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50
cycles	1.50	1.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	2.50	2.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

21% of peak load performance is reached (20.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42de50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42df58 <hypre_qsort2abs+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42debc <hypre_qsort2abs+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_qsort2abs–	0.06	0.01
▼Loop 1462 - par_interp.c:3180-3191 - exec–	0.06	0.01
○Loop 1461 - par_interp.c:3180-3191 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code