OV - exec - Function hypre_BoomerAMGCoarsenPMIS

	Function: hypre_BoomerAMGCoarsenPMIS	Module: exec	Source: par_coarsen.c:1980-2624 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 1980 - 2624

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1980: {

1981: #ifdef HYPRE_PROFILE

1982:    hypre_profile_times[HYPRE_TIMER_ID_PMIS] -= hypre_MPI_Wtime();

1983: #endif

1984:

1985:    MPI_Comm 	       comm            = hypre_ParCSRMatrixComm(S);

1986:    hypre_ParCSRCommPkg      *comm_pkg        = hypre_ParCSRMatrixCommPkg(S);

1987:    hypre_ParCSRCommHandle   *comm_handle;

1988:

1989:    hypre_CSRMatrix    *S_diag          = hypre_ParCSRMatrixDiag(S);

1990:    HYPRE_Int                *S_diag_i        = hypre_CSRMatrixI(S_diag);

1991:    HYPRE_Int                *S_diag_j        = hypre_CSRMatrixJ(S_diag);

1992:

1993:    hypre_CSRMatrix    *S_offd          = hypre_ParCSRMatrixOffd(S);

1994:    HYPRE_Int                *S_offd_i        = hypre_CSRMatrixI(S_offd);

1995:    HYPRE_Int                *S_offd_j;

1996:

1997:    HYPRE_Int                 num_variables   = hypre_CSRMatrixNumRows(S_diag);

[...]

2058:    if (debug_flag == 3) wall_time = time_getWallclockSeconds();

2059:    hypre_MPI_Comm_size(comm,&num_procs);

2060:    hypre_MPI_Comm_rank(comm,&my_id);

2061:

2062:    if (!comm_pkg)

2063:    {

2064:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2065:    }

2066:

2067:    if (!comm_pkg)

2068:    {

2069:         hypre_MatvecCommPkgCreate(A);

2070:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2071:    }

2072:

2073:    num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

2074:

2075:    int_buf_data = hypre_CTAlloc(HYPRE_Int, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2076:                                                 num_sends));

2077:    buf_data = hypre_CTAlloc(HYPRE_Real, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2078:                                                 num_sends));

2079:

2080:    num_cols_offd = hypre_CSRMatrixNumCols(S_offd);

2081:

2082:    S_diag_j = hypre_CSRMatrixJ(S_diag);

2083:

2084:    if (num_cols_offd)

2085:    {

2086:       S_offd_j = hypre_CSRMatrixJ(S_offd);

[...]

2100:    measure_array = hypre_CTAlloc(HYPRE_Real, num_variables+num_cols_offd);

2101:

2102:    /* first calculate the local part of the sums for the external nodes */

2103: #ifdef HYPRE_USING_OPENMP

2104:    HYPRE_Int *measure_array_temp = hypre_CTAlloc(HYPRE_Int, num_variables+num_cols_offd);

2105:

2106: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2113: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2126:    if (num_procs > 1)

2127:    comm_handle = hypre_ParCSRCommHandleCreate(2, comm_pkg,

2128:                         &measure_array[num_variables], buf_data);

2129:

2130:    /* calculate the local part for the local nodes */

2131: #ifdef HYPRE_USING_OPENMP

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2139: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2145:    hypre_TFree(measure_array_temp);

[...]

2154:    if (num_procs > 1)

2155:    hypre_ParCSRCommHandleDestroy(comm_handle);

2156:

2157:    /* now add the externally calculated part of the local nodes to the local nodes */

2158:    index = 0;

2159:    for (i=0; i < num_sends; i++)

2160:    {

2161:       start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2162:       for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2163:             measure_array[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)]

2164:                         += buf_data[index++];

2165:    }

2166:

2167:    /* set the measures of the external nodes to zero */

2168:    for (i=num_variables; i < num_variables+num_cols_offd; i++)

2169:    {

2170:       measure_array[i] = 0;

[...]

2176:    if (CF_init == 2 || CF_init == 4)

2177:       hypre_BoomerAMGIndepSetInit(S, measure_array, 1);

2178:    else

2179:       hypre_BoomerAMGIndepSetInit(S, measure_array, 0);

[...]

2186:    if (num_cols_offd)

2187:       graph_array_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2188:    else

2189:       graph_array_offd = NULL;

2190:

2191:    for (ig = 0; ig < num_cols_offd; ig++)

2192:       graph_array_offd[ig] = ig;

2193:

2194:    graph_offd_size = num_cols_offd;

2195:

2196:    /* now the local part of the graph array, and the local CF_marker array */

2197:    graph_array = hypre_CTAlloc(HYPRE_Int, num_variables);

2198:

2199:    if (CF_init==1)

2200:    {

2201:       CF_marker = *CF_marker_ptr;

2202:       cnt = 0;

2203:       for (i=0; i < num_variables; i++)

2204:       {

2205:          if ( (S_offd_i[i+1]-S_offd_i[i]) > 0 || CF_marker[i] == -1)

[...]

2211:             if (measure_array[i] >= 1.0 ||

2212:                 (S_diag_i[i+1]-S_diag_i[i]) > 0)

[...]

2219:                CF_marker[i] = F_PT;

2220:             }

2221:          }

2222:          else if (CF_marker[i] == SF_PT)

2223:             measure_array[i] = 0;

[...]

2230:       CF_marker = hypre_CTAlloc(HYPRE_Int, num_variables);

2231:       cnt = 0;

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

2241:          }

2242:          else

2243:             graph_array[cnt++] = i;

2244:       }

2245:    }

2246:    graph_size = cnt;

2247:

2248:    /* now the off-diagonal part of CF_marker */

2249:    if (num_cols_offd)

2250:      CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2251:    else

2252:      CF_marker_offd = NULL;

2253:

2254:    for (i=0; i < num_cols_offd; i++)

2255: 	CF_marker_offd[i] = 0;

[...]

2262:    for (i = 0; i < num_sends; i++)

2263:      {

2264:        start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2265:        for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2266: 	 {

2267: 	   jrow = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2268: 	   buf_data[index++] = measure_array[jrow];

2269:          }

2270:      }

2271:

2272:    if (num_procs > 1)

2273:      {

2274:        comm_handle = hypre_ParCSRCommHandleCreate(1, comm_pkg, buf_data,

2275: 						  &measure_array[num_variables]);

2276:

2277:        hypre_ParCSRCommHandleDestroy(comm_handle);

2278:

2279:      }

2280:

2281:    if (debug_flag == 3)

2282:    {

2283:       wall_time = time_getWallclockSeconds() - wall_time;

2284:       hypre_printf("Proc = %d    Initialize CLJP phase = %f\n",

2285:                      my_id, wall_time);

2286:    }

2287:

2288:    HYPRE_Int                *graph_array2 = hypre_CTAlloc(HYPRE_Int, num_variables);

2289:    HYPRE_Int *graph_array_offd2 = NULL;

2290:    if (num_cols_offd)

2291:      graph_array_offd2 = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

[...]

2305:      hypre_MPI_Allreduce(&graph_size,&global_graph_size,1,HYPRE_MPI_INT,hypre_MPI_SUM,comm);

2306:

2307:      if (global_graph_size == 0)

[...]

2320:       if (!CF_init || iter)

[...]

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2338: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

[...]

2393:       if (num_procs > 1)

2394:       {

2395:          comm_handle = hypre_ParCSRCommHandleCreate(12, comm_pkg,

2396: 		CF_marker_offd, int_buf_data);

2397:

2398:          hypre_ParCSRCommHandleDestroy(comm_handle);

2399:       }

2400:

2401:       index = 0;

2402:       for (i = 0; i < num_sends; i++)

2403:       {

2404:          start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2405:          for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2406:          {

2407:             elmt = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2408:             if (!int_buf_data[index] && CF_marker[elmt] > 0)

2409:             {

2410:                CF_marker[elmt] = 0;

2411:                index++;

2412:             }

2413:             else

2414:             {

2415:                int_buf_data[index++] = CF_marker[elmt];

2416:             }

2417:          }

2418:       }

2419:

2420:       if (num_procs > 1)

2421:       {

2422:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2423:         	CF_marker_offd);

2424:

2425:          hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

[...]

2492:       for (i = 0; i < num_sends; i++)

2493:       {

2494:         start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2495:         for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2496:                 int_buf_data[index++]

2497:                  = CF_marker[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

2498:       }

2499:

2500:       if (num_procs > 1)

2501:       {

2502:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2503:         CF_marker_offd);

2504:

2505:       hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2513:     prefix_sum_workspace = hypre_TAlloc(HYPRE_Int, 2*(hypre_NumThreads() + 1));

2514:

2515: #ifdef HYPRE_USING_OPENMP

2516: #pragma omp parallel private(ig,i)

[...]

2581:      HYPRE_Int *temp = graph_array;

2582:      graph_array = graph_array2;

2583:      graph_array2 = temp;

[...]

2589:      hypre_TFree(prefix_sum_workspace);

[...]

2608:    hypre_TFree(measure_array);

2609:    hypre_TFree(graph_array);

2610:    hypre_TFree(graph_array2);

2611:    hypre_TFree(graph_array_offd2);

2612:    if (num_cols_offd) hypre_TFree(graph_array_offd);

2613:    hypre_TFree(buf_data);

2614:    hypre_TFree(int_buf_data);

2615:    hypre_TFree(CF_marker_offd);

2616:    /*if (num_procs > 1) hypre_CSRMatrixDestroy(S_ext);*/

2617:

2618:    *CF_marker_ptr   = CF_marker;

[...]

2624:    return (ierr);

0x420730 SUB	SP, SP, #352

0x420734 STR	D8, [SP, #240]

0x420738 STP	X29, X30, [SP, #256]

0x42073c STP	X28, X27, [SP, #272]

0x420740 STP	X26, X25, [SP, #288]

0x420744 STP	X24, X23, [SP, #304]

0x420748 STP	X22, X21, [SP, #320]

0x42074c STP	X20, X19, [SP, #336]

0x420750 ADD	X29, SP, #256

0x420754 LDR	X8, [X0]

0x420758 LDP	X26, X27, [X0, #56]

0x42075c LDR	X22, [X0, #112]

0x420760 ORR	X28, XZR, X4

0x420764 ORR	X25, XZR, X3

0x420768 ORR	X20, XZR, X1

0x42076c CMP	X3, #3

0x420770 STP	X2, X8, [SP, #64]

0x420774 LDP	X8, X9, [X26]

0x420778 ORR	X19, XZR, X0

0x42077c STUR	X8, [X29, #504]

0x420780 STUR	X9, [X29, #480]

0x420784 LDR	X8, [X27]

0x420788 STUR	X8, [X29, #472]

0x42078c LDR	X8, [X26, #16]

0x420790 STP	XZR, X8, [X29, #960]

0x420794 B.NE	4207a0

0x420798 BL	4b0670

0x42079c FMOV	D8, D0

0x4207a0 LDR	X21, [SP, #72]

0x4207a4 ADD	X1, SP, #112

0x4207a8 ORR	X0, XZR, X21

0x4207ac BL	4afa30

0x4207b0 ORR	X0, XZR, X21

0x4207b4 ADD	X1, SP, #120

0x4207b8 BL	4afa60

0x4207bc CBNZ	X22, 4207d4

0x4207c0 LDR	X22, [X20, #112]

0x4207c4 CBNZ	X22, 4207d4

0x4207c8 ORR	X0, XZR, X20

0x4207cc BL	486250

0x4207d0 LDR	X22, [X20, #112]

0x4207d4 LDR	X21, [X22, #8]

0x4207d8 LDR	X8, [X22, #24]

0x4207dc MOVZ	W1, #8

0x4207e0 LDR	X0, [X8, X21,LSL #3]

0x4207e4 BL	4ae430

0x4207e8 LDR	X8, [X22, #24]

0x4207ec ORR	X23, XZR, X0

0x4207f0 MOVZ	W1, #8

0x4207f4 LDR	X0, [X8, X21,LSL #3]

0x4207f8 BL	4ae430

0x4207fc LDR	X8, [X27, #24]

0x420800 LDR	X9, [X26, #8]

0x420804 ORR	X24, XZR, X0

0x420808 STUR	X8, [X29, #448]

0x42080c STUR	X9, [X29, #480]

0x420810 CBZ	X8, 42081c

0x420814 LDR	X9, [X27, #8]

0x420818 STUR	X9, [X29, #464]

0x42081c LDUR	X9, [X29, #456]

0x420820 MOVZ	W1, #8

0x420824 ADD	X0, X9, X8

0x420828 BL	4ae430

0x42082c LDP	X9, X8, [X29, #960]

0x420830 STUR	X0, [X29, #424]

0x420834 MOVZ	W1, #8

0x420838 ADD	X0, X9, X8

0x42083c BL	4ae430

0x420840 STR	X0, [SP, #96]

0x420844 ADRP	X0,

0x420848 ADD	X0, X0, #448

0x42084c ADRP	X2, 42184c

0x420850 ADD	X2, X2, #800

0x420854 SUB	X3, X29, #40

0x420858 SUB	X4, X29, #56

0x42085c ADD	X5, SP, #96

0x420860 SUB	X6, X29, #48

0x420864 MOVZ	W1, #4

0x420868 BL	40fa00

0x42086c ADRP	X0,

0x420870 ADD	X0, X0, #520

0x420874 ADRP	X2, 421874

0x420878 ADD	X2, X2, #1152

0x42087c SUB	X3, X29, #64

0x420880 SUB	X4, X29, #88

0x420884 SUB	X5, X29, #56

0x420888 ADD	X6, SP, #96

0x42088c MOVZ	W1, #4

0x420890 BL	40fa00

0x420894 LDR	X8, [SP, #112]

0x420898 CMP	X8, #2

0x42089c B.LT	4208c0

0x4208a0 LDUR	X8, [X29, #424]

0x4208a4 LDUR	X9, [X29, #456]

0x4208a8 ORR	X1, XZR, X22

0x4208ac ORR	X3, XZR, X24

0x4208b0 MOVZ	W0, #2

0x4208b4 ADD	X2, X8, X9,LSL #3

0x4208b8 BL	485620

0x4208bc ORR	X20, XZR, X0

0x4208c0 ADRP	X0,

0x4208c4 ADD	X0, X0, #592

0x4208c8 ADRP	X2, 4218c8

0x4208cc ADD	X2, X2, #1504

0x4208d0 SUB	X3, X29, #8

0x4208d4 SUB	X4, X29, #56

0x4208d8 ADD	X5, SP, #96

0x4208dc SUB	X6, X29, #32

0x4208e0 MOVZ	W1, #4

0x4208e4 BL	40fa00

0x4208e8 ADRP	X0,

0x4208ec ADD	X0, X0, #664

0x4208f0 ADRP	X2, 4218f0

0x4208f4 ADD	X2, X2, #1808

0x4208f8 SUB	X3, X29, #56

0x4208fc SUB	X4, X29, #88

0x420900 ADD	X5, SP, #96

0x420904 MOVZ	W1, #3

0x420908 BL	40fa00

0x42090c LDR	X0, [SP, #96]

0x420910 BL	4ae530

0x420914 LDR	X8, [SP, #112]

0x420918 STR	XZR, [SP, #96]

0x42091c CMP	X8, #1

0x420920 B.LE	42092c

0x420924 ORR	X0, XZR, X20

0x420928 BL	485a00

0x42092c LDR	X20, [SP, #64]

0x420930 CMP	X21, #1

0x420934 B.LT	420a64

0x420938 LDR	X9, [X22, #24]

0x42093c LDUR	X10, [X29, #424]

0x420940 ORR	X14, XZR, XZR

0x420944 ORR	X8, XZR, XZR

0x420948 ADD	X11, X24, #16

0x42094c LDR	X12, [X9]

0x420950 B	420970

0x420954 HINT	#0

0x420958 HINT	#0

0x42095c HINT	#0

(444) 0x420960 ORR	X13, XZR, X14

  (445) 0x420964 ORR	X14, XZR, X13

  (445) 0x420968 CMP	X8, X21

  (445) 0x42096c B.EQ	420a64

  (445) 0x420970 ADD	X8, X8, #1

  (445) 0x420974 ORR	X15, XZR, X12

  (445) 0x420978 LDR	X12, [X9, X8,LSL #3]

  (445) 0x42097c CMP	X12, X15

  (445) 0x420980 B.LE	420960

  (445) 0x420984 LDR	X16, [X22, #32]

  (445) 0x420988 ADD	X13, X14, X12

  (445) 0x42098c SUB	W17, W12, W15

  (445) 0x420990 ANDS	X0, X17, #4160

  (445) 0x420994 SUB	X13, X13, X15

  (445) 0x420998 ORR	X17, XZR, X14

  (445) 0x42099c ORR	X18, XZR, X15

  (445) 0x4209a0 B.EQ	4209d0

  (445) 0x4209a4 ORR	X17, XZR, X14

  (445) 0x4209a8 ORR	X18, XZR, X15

    (447) 0x4209ac LDR	X1, [X16, X18,LSL #3]

    (447) 0x4209b0 LDR	D0, [X24, X17,LSL #3]

    (447) 0x4209b4 ADD	X17, X17, #1

    (447) 0x4209b8 ADD	X18, X18, #1

    (447) 0x4209bc SUBS	X0, X0, #1

    (447) 0x4209c0 LDR	D1, [X10, X1,LSL #3]

    (447) 0x4209c4 FADD	D0, D0, D1

    (447) 0x4209c8 STR	D0, [X10, X1,LSL #3]

    (447) 0x4209cc B.NE	4209ac

  (445) 0x4209d0 ORN	X0, XZR, X15

  (445) 0x4209d4 ADD	X0, X12, X0

  (445) 0x4209d8 CMP	X0, #3

  (445) 0x4209dc B.CC	420964

  (445) 0x4209e0 ADD	X14, X14, X12

  (445) 0x4209e4 ADD	X16, X16, X18,LSL #3

  (445) 0x4209e8 ADD	X16, X16, #16

  (445) 0x4209ec SUB	X14, X14, X17

  (445) 0x4209f0 SUB	X14, X14, X15

  (445) 0x4209f4 ADD	X15, X11, X17,LSL #3

  (445) 0x4209f8 HINT	#0

  (445) 0x4209fc HINT	#0

    (446) 0x420a00 LDUR	X17, [X16, #496]

    (446) 0x420a04 LDUR	D0, [X15, #496]

    (446) 0x420a08 SUBS	X14, X14, #4

    (446) 0x420a0c LDR	D1, [X10, X17,LSL #3]

    (446) 0x420a10 FADD	D0, D0, D1

    (446) 0x420a14 STR	D0, [X10, X17,LSL #3]

    (446) 0x420a18 LDUR	X17, [X16, #504]

    (446) 0x420a1c LDUR	D0, [X15, #504]

    (446) 0x420a20 LDR	D1, [X10, X17,LSL #3]

    (446) 0x420a24 FADD	D0, D0, D1

    (446) 0x420a28 STR	D0, [X10, X17,LSL #3]

    (446) 0x420a2c LDR	X17, [X16]

    (446) 0x420a30 LDR	D0, [X15]

    (446) 0x420a34 LDR	D1, [X10, X17,LSL #3]

    (446) 0x420a38 FADD	D0, D0, D1

    (446) 0x420a3c STR	D0, [X10, X17,LSL #3]

    (446) 0x420a40 LDR	X17, [X16, #8]

    (446) 0x420a44 LDR	D0, [X15, #8]

    (446) 0x420a48 ADD	X16, X16, #32

    (446) 0x420a4c ADD	X15, X15, #32

    (446) 0x420a50 LDR	D1, [X10, X17,LSL #3]

    (446) 0x420a54 FADD	D0, D0, D1

    (446) 0x420a58 STR	D0, [X10, X17,LSL #3]

    (446) 0x420a5c B.NE	420a00

  (445) 0x420a60 B	420964

0x420a64 LDUR	X8, [X29, #448]

0x420a68 CMP	X8, #1

0x420a6c B.LT	420ad0

0x420a70 LDUR	X9, [X29, #456]

0x420a74 LDUR	X10, [X29, #424]

0x420a78 ADD	X8, X8, X9

0x420a7c ADD	X0, X10, X9,LSL #3

0x420a80 ADD	X10, X9, #1

0x420a84 CMP	X8, X10

0x420a88 CSINC	X8, X8, X9, #12

0x420a8c SUB	X8, X8, X9

0x420a90 UBFM	X2, X8, #61, #60

0x420a94 RDVL	X8, #1

0x420a98 CMP	X8, #17

0x420a9c B.CS	420aac

0x420aa0 ORR	W1, WZR, WZR

0x420aa4 BL	40f6f0

0x420aa8 B	420ad0

0x420aac WHILELO	P0.B, XZR, X2

0x420ab0 ORR	X8, XZR, XZR

0x420ab4 DUP	Z0.B, #0

0x420ab8 HINT	#0

0x420abc HINT	#0

(443) 0x420ac0 ST1B	{Z0.B}, P0, [X0, X8]

(443) 0x420ac4 INCP	X8, P0.B

(443) 0x420ac8 WHILELO	P0.B, X8, X2

(443) 0x420acc B.MI	420ac0

0x420ad0 CMP	X20, #4

0x420ad4 B.EQ	420ae0

0x420ad8 CMP	X20, #2

0x420adc B.NE	420b38

0x420ae0 LDUR	X1, [X29, #424]

0x420ae4 ORR	X0, XZR, X19

0x420ae8 MOVZ	W2, #1

0x420aec BL	4276e0

0x420af0 LDUR	X0, [X29, #448]

0x420af4 CBZ	X0, 420b50

0x420af8 MOVZ	W1, #8

0x420afc BL	4ae430

0x420b00 LDUR	X8, [X29, #448]

0x420b04 STUR	X0, [X29, #408]

0x420b08 CMP	X8, #1

0x420b0c B.LT	420b58

0x420b10 ORR	X9, XZR, XZR

0x420b14 HINT	#0

0x420b18 HINT	#0

0x420b1c HINT	#0

(442) 0x420b20 STR	X9, [X0, X9,LSL #3]

(442) 0x420b24 ADD	X9, X9, #1

(442) 0x420b28 LDUR	X8, [X29, #448]

(442) 0x420b2c CMP	X9, X8

(442) 0x420b30 B.LT	420b20

0x420b34 B	420b58

0x420b38 LDUR	X1, [X29, #424]

0x420b3c ORR	X0, XZR, X19

0x420b40 ORR	X2, XZR, XZR

0x420b44 BL	4276e0

0x420b48 LDUR	X0, [X29, #448]

0x420b4c CBNZ	X0, 420af8

0x420b50 ORR	X8, XZR, XZR

0x420b54 STUR	XZR, [X29, #408]

0x420b58 LDUR	X0, [X29, #456]

0x420b5c MOVZ	W1, #8

0x420b60 STUR	X8, [X29, #392]

0x420b64 BL	4ae430

0x420b68 CMP	X20, #1

0x420b6c STUR	X0, [X29, #416]

0x420b70 B.NE	420c20

0x420b74 LDUR	X8, [X29, #456]

0x420b78 LDR	X9, [X28]

0x420b7c CMP	X8, #1

0x420b80 STUR	X9, [X29, #440]

0x420b84 B.LT	420ccc

0x420b88 LDUR	X11, [X29, #472]

0x420b8c LDUR	X12, [X29, #424]

0x420b90 LDUR	X13, [X29, #504]

0x420b94 ORR	X8, XZR, XZR

0x420b98 ORR	X10, XZR, XZR

0x420b9c FMOV	D0, #1.0000000

0x420ba0 MOVN	X14, #0

0x420ba4 B	420bbc

(441) 0x420ba8 STR	XZR, [X12, X10,LSL #3]

(441) 0x420bac LDUR	X15, [X29, #456]

(441) 0x420bb0 ADD	X10, X10, #1

(441) 0x420bb4 CMP	X10, X15

(441) 0x420bb8 B.GE	420cd0

(441) 0x420bbc ADD	X15, X11, X10,LSL #3

(441) 0x420bc0 LDP	X15, X16, [X15]

(441) 0x420bc4 CMP	X16, X15

(441) 0x420bc8 B.GT	420c08

(441) 0x420bcc LDR	X15, [X9, X10,LSL #3]

(441) 0x420bd0 CMN	X15, #3

(441) 0x420bd4 B.EQ	420ba8

(441) 0x420bd8 CMN	X15, #2

(441) 0x420bdc B.EQ	420bec

(441) 0x420be0 CMN	X15, #1

(441) 0x420be4 B.EQ	420c08

(441) 0x420be8 B	420c0c

(441) 0x420bec LDR	D1, [X12, X10,LSL #3]

(441) 0x420bf0 FCMP	D1, D0

(441) 0x420bf4 B.GE	420c08

(441) 0x420bf8 ADD	X15, X13, X10,LSL #3

(441) 0x420bfc LDP	X15, X16, [X15]

(441) 0x420c00 CMP	X16, X15

(441) 0x420c04 B.LE	420c18

(441) 0x420c08 STR	XZR, [X9, X10,LSL #3]

(441) 0x420c0c STR	X10, [X0, X8,LSL #3]

(441) 0x420c10 ADD	X8, X8, #1

(441) 0x420c14 B	420bac

(441) 0x420c18 STR	X14, [X9, X10,LSL #3]

(441) 0x420c1c B	420bac

0x420c20 LDUR	X0, [X29, #456]

0x420c24 MOVZ	W1, #8

0x420c28 BL	4ae430

0x420c2c LDUR	X8, [X29, #456]

0x420c30 STUR	X0, [X29, #440]

0x420c34 CMP	X8, #1

0x420c38 B.LT	420d20

0x420c3c SUB	X10, X20, #3

0x420c40 ORR	X8, XZR, XZR

0x420c44 ORR	X9, XZR, XZR

0x420c48 CMP	X10, #2

0x420c4c MOVN	X10, #2

0x420c50 CSINC	X10, X10, XZR, #2

0x420c54 B	420c7c

0x420c58 HINT	#0

0x420c5c HINT	#0

(439) 0x420c60 LDUR	X11, [X29, #416]

(439) 0x420c64 STR	X9, [X11, X8,LSL #3]

(439) 0x420c68 ADD	X8, X8, #1

(439) 0x420c6c LDUR	X11, [X29, #456]

(439) 0x420c70 ADD	X9, X9, #1

(439) 0x420c74 CMP	X9, X11

(439) 0x420c78 B.GE	420cd0

  (440) 0x420c7c UBFM	X11, X9, #61, #60

  (440) 0x420c80 STR	XZR, [X0, X11]

  (440) 0x420c84 LDUR	X12, [X29, #504]

  (440) 0x420c88 ADD	X11, X12, X11

  (440) 0x420c8c LDP	X11, X12, [X11]

  (440) 0x420c90 CMP	X12, X11

  (440) 0x420c94 B.NE	420c60

  (440) 0x420c98 LDUR	X11, [X29, #472]

  (440) 0x420c9c ADD	X11, X11, X9,LSL #3

  (440) 0x420ca0 LDP	X11, X12, [X11]

  (440) 0x420ca4 CMP	X12, X11

  (440) 0x420ca8 B.NE	420c60

  (440) 0x420cac STR	X10, [X0, X9,LSL #3]

  (440) 0x420cb0 LDUR	X11, [X29, #424]

  (440) 0x420cb4 STR	XZR, [X11, X9,LSL #3]

  (440) 0x420cb8 LDUR	X11, [X29, #456]

  (440) 0x420cbc ADD	X9, X9, #1

  (440) 0x420cc0 CMP	X9, X11

  (440) 0x420cc4 B.LT	420c7c

0x420cc8 B	420cd0

0x420ccc ORR	X8, XZR, XZR

0x420cd0 LDUR	X0, [X29, #448]

0x420cd4 STUR	X8, [X29, #400]

0x420cd8 CBZ	X0, 420d30

0x420cdc MOVZ	W1, #8

0x420ce0 BL	4ae430

0x420ce4 LDUR	X8, [X29, #448]

0x420ce8 STUR	X0, [X29, #432]

0x420cec CMP	X8, #1

0x420cf0 B.LT	420d14

0x420cf4 ORR	X8, XZR, XZR

0x420cf8 HINT	#0

0x420cfc HINT	#0

(438) 0x420d00 STR	XZR, [X0, X8,LSL #3]

(438) 0x420d04 ADD	X8, X8, #1

(438) 0x420d08 LDUR	X9, [X29, #448]

(438) 0x420d0c CMP	X8, X9

(438) 0x420d10 B.LT	420d00

0x420d14 CMP	X21, #1

0x420d18 B.GE	420d3c

0x420d1c B	420e44

0x420d20 ORR	X8, XZR, XZR

0x420d24 LDUR	X0, [X29, #448]

0x420d28 STUR	XZR, [X29, #400]

0x420d2c CBNZ	X0, 420cdc

0x420d30 STUR	XZR, [X29, #432]

0x420d34 CMP	X21, #1

0x420d38 B.LT	420e44

0x420d3c LDR	X9, [X22, #24]

0x420d40 LDUR	X10, [X29, #424]

0x420d44 ORR	X14, XZR, XZR

0x420d48 ORR	X8, XZR, XZR

0x420d4c ADD	X11, X24, #16

0x420d50 LDR	X12, [X9]

0x420d54 B	420d70

0x420d58 HINT	#0

0x420d5c HINT	#0

(434) 0x420d60 ORR	X13, XZR, X14

  (435) 0x420d64 ORR	X14, XZR, X13

  (435) 0x420d68 CMP	X8, X21

  (435) 0x420d6c B.EQ	420e44

  (435) 0x420d70 ADD	X8, X8, #1

  (435) 0x420d74 ORR	X15, XZR, X12

  (435) 0x420d78 LDR	X12, [X9, X8,LSL #3]

  (435) 0x420d7c CMP	X12, X15

  (435) 0x420d80 B.LE	420d60

  (435) 0x420d84 LDR	X16, [X22, #32]

  (435) 0x420d88 ADD	X13, X14, X12

  (435) 0x420d8c SUB	W17, W12, W15

  (435) 0x420d90 ANDS	X0, X17, #4160

  (435) 0x420d94 SUB	X13, X13, X15

  (435) 0x420d98 ORR	X17, XZR, X14

  (435) 0x420d9c ORR	X18, XZR, X15

  (435) 0x420da0 B.EQ	420dc8

  (435) 0x420da4 ORR	X17, XZR, X14

  (435) 0x420da8 ORR	X18, XZR, X15

    (437) 0x420dac LDR	X1, [X16, X18,LSL #3]

    (437) 0x420db0 ADD	X18, X18, #1

    (437) 0x420db4 SUBS	X0, X0, #1

    (437) 0x420db8 LDR	D0, [X10, X1,LSL #3]

    (437) 0x420dbc STR	D0, [X24, X17,LSL #3]

    (437) 0x420dc0 ADD	X17, X17, #1

    (437) 0x420dc4 B.NE	420dac

  (435) 0x420dc8 ORN	X0, XZR, X15

  (435) 0x420dcc ADD	X0, X12, X0

  (435) 0x420dd0 CMP	X0, #3

  (435) 0x420dd4 B.CC	420d64

  (435) 0x420dd8 ADD	X14, X14, X12

  (435) 0x420ddc ADD	X16, X16, X18,LSL #3

  (435) 0x420de0 ADD	X16, X16, #16

  (435) 0x420de4 SUB	X14, X14, X17

  (435) 0x420de8 SUB	X14, X14, X15

  (435) 0x420dec ADD	X15, X11, X17,LSL #3

  (435) 0x420df0 HINT	#0

  (435) 0x420df4 HINT	#0

  (435) 0x420df8 HINT	#0

  (435) 0x420dfc HINT	#0

    (436) 0x420e00 LDUR	X17, [X16, #496]

    (436) 0x420e04 SUBS	X14, X14, #4

    (436) 0x420e08 LDR	D0, [X10, X17,LSL #3]

    (436) 0x420e0c STUR	D0, [X15, #496]

    (436) 0x420e10 LDUR	X17, [X16, #504]

    (436) 0x420e14 LDR	D0, [X10, X17,LSL #3]

    (436) 0x420e18 STUR	D0, [X15, #504]

    (436) 0x420e1c LDR	X17, [X16]

    (436) 0x420e20 LDR	D0, [X10, X17,LSL #3]

    (436) 0x420e24 STR	D0, [X15]

    (436) 0x420e28 LDR	X17, [X16, #8]

    (436) 0x420e2c ADD	X16, X16, #32

    (436) 0x420e30 LDR	D0, [X10, X17,LSL #3]

    (436) 0x420e34 STR	D0, [X15, #8]

    (436) 0x420e38 ADD	X15, X15, #32

    (436) 0x420e3c B.NE	420e00

  (435) 0x420e40 B	420d64

0x420e44 LDR	X8, [SP, #112]

0x420e48 CMP	X8, #1

0x420e4c B.LE	420e70

0x420e50 LDUR	X8, [X29, #424]

0x420e54 LDUR	X9, [X29, #456]

0x420e58 ORR	X1, XZR, X22

0x420e5c ORR	X2, XZR, X24

0x420e60 MOVZ	W0, #1

0x420e64 ADD	X3, X8, X9,LSL #3

0x420e68 BL	485620

0x420e6c BL	485a00

0x420e70 CMP	X25, #3

0x420e74 B.NE	420e90

0x420e78 BL	4b0670

0x420e7c LDR	X1, [SP, #120]

0x420e80 FSUB	D0, D0, S8

0x420e84 ADRP	X0,

0x420e88 ADD	X0, X0, #120

0x420e8c BL	4ae640

0x420e90 LDUR	X0, [X29, #456]

0x420e94 MOVZ	W1, #8

0x420e98 STR	X28, [SP, #56]

0x420e9c BL	4ae430

0x420ea0 STP	XZR, X0, [SP, #80]

0x420ea4 LDUR	X0, [X29, #448]

0x420ea8 CBZ	X0, 420eb8

0x420eac MOVZ	W1, #8

0x420eb0 BL	4ae430

0x420eb4 STR	X0, [SP, #80]

0x420eb8 ADRP	X3,

0x420ebc ADRP	X4,

0x420ec0 SUB	X0, X29, #112

0x420ec4 ADD	X1, SP, #128

0x420ec8 LDR	X3, [X3, #3928]

0x420ecc LDR	X4, [X4, #3784]

0x420ed0 LDR	X5, [SP, #72]

0x420ed4 MOVZ	W2, #1

0x420ed8 BL	4b0270

0x420edc LDR	X8, [SP, #128]

0x420ee0 CBZ	X8, 421284

0x420ee4 ORR	X26, XZR, XZR

0x420ee8 AND	X27, X21, #8127

0x420eec SUB	X28, X29, #56

0x420ef0 SUB	X19, X29, #80

0x420ef4 SUB	X25, X29, #48

0x420ef8 SUB	X20, X29, #40

0x420efc B	420fac

    (426) 0x420f00 ADD	X26, X26, #1

    (426) 0x420f04 BL	4b05a0

    (426) 0x420f08 UBFM	X8, X0, #60, #59

    (426) 0x420f0c ADD	X0, X8, #16

    (426) 0x420f10 BL	4ae3c0

    (426) 0x420f14 ADD	X8, SP, #80

    (426) 0x420f18 STR	X0, [SP, #104]

    (426) 0x420f1c SUB	X3, X29, #112

    (426) 0x420f20 SUB	X4, X29, #120

    (426) 0x420f24 SUB	X5, X29, #96

    (426) 0x420f28 STR	X8, [SP, #40]

    (426) 0x420f2c ADD	X8, SP, #88

    (426) 0x420f30 SUB	X6, X29, #72

    (426) 0x420f34 SUB	X7, X29, #88

    (426) 0x420f38 ADRP	X0,

    (426) 0x420f3c ADD	X0, X0, #976

    (426) 0x420f40 STR	X8, [SP, #32]

    (426) 0x420f44 ADD	X8, SP, #104

    (426) 0x420f48 MOVZ	W1, #11

    (426) 0x420f4c ADRP	X2, 421f4c

    (426) 0x420f50 ADD	X2, X2, #3664

    (426) 0x420f54 STP	X28, X8, [SP, #16]

    (426) 0x420f58 SUB	X8, X29, #104

    (426) 0x420f5c STP	X8, X19, [SP]

    (426) 0x420f60 BL	40fa00

    (426) 0x420f64 LDP	X8, X11, [X29, #920]

    (426) 0x420f68 LDP	X9, X10, [SP, #80]

    (426) 0x420f6c LDR	X0, [SP, #104]

    (426) 0x420f70 STP	X9, X10, [X29, #920]

    (426) 0x420f74 STP	X8, X11, [SP, #80]

    (426) 0x420f78 BL	4ae530

    (426) 0x420f7c STR	XZR, [SP, #104]

    (426) 0x420f80 ADRP	X3,

    (426) 0x420f84 ADRP	X4,

    (426) 0x420f88 SUB	X0, X29, #112

    (426) 0x420f8c ADD	X1, SP, #128

    (426) 0x420f90 LDR	X3, [X3, #3928]

    (426) 0x420f94 LDR	X4, [X4, #3784]

    (426) 0x420f98 LDR	X5, [SP, #72]

    (426) 0x420f9c MOVZ	W2, #1

    (426) 0x420fa0 BL	4b0270

    (426) 0x420fa4 LDR	X8, [SP, #128]

    (426) 0x420fa8 CBZ	X8, 421284

    (426) 0x420fac LDR	X8, [SP, #64]

    (426) 0x420fb0 CBZ	X8, 420fb8

    (426) 0x420fb4 CBZ	X26, 421130

    (426) 0x420fb8 SUB	X3, X29, #112

    (426) 0x420fbc SUB	X4, X29, #96

    (426) 0x420fc0 SUB	X5, X29, #88

    (426) 0x420fc4 SUB	X6, X29, #72

    (426) 0x420fc8 ADRP	X0,

    (426) 0x420fcc ADD	X0, X0, #736

    (426) 0x420fd0 MOVZ	W1, #4

    (426) 0x420fd4 ADRP	X2, 421fd4

    (426) 0x420fd8 ADD	X2, X2, #2144

    (426) 0x420fdc BL	40fa00

    (426) 0x420fe0 SUB	X3, X29, #120

    (426) 0x420fe4 SUB	X4, X29, #104

    (426) 0x420fe8 SUB	X5, X29, #88

    (426) 0x420fec SUB	X6, X29, #56

    (426) 0x420ff0 SUB	X7, X29, #80

    (426) 0x420ff4 ADRP	X0,

    (426) 0x420ff8 ADD	X0, X0, #808

    (426) 0x420ffc MOVZ	W1, #5

    (426) 0x421000 ADRP	X2, 421000

    (426) 0x421004 ADD	X2, X2, #2528

    (426) 0x421008 BL	40fa00

    (426) 0x42100c SUB	X3, X29, #112

    (426) 0x421010 SUB	X4, X29, #96

    (426) 0x421014 SUB	X5, X29, #88

    (426) 0x421018 SUB	X6, X29, #8

    (426) 0x42101c STP	X28, X19, [SP, #24]

    (426) 0x421020 STP	X20, X25, [SP, #8]

    (426) 0x421024 SUB	X7, X29, #32

    (426) 0x421028 SUB	X8, X29, #72

    (426) 0x42102c ADRP	X0,

    (426) 0x421030 ADD	X0, X0, #880

    (426) 0x421034 STR	X8, [SP]

    (426) 0x421038 MOVZ	W1, #10

    (426) 0x42103c ADRP	X2, 42103c

    (426) 0x421040 ADD	X2, X2, #2784

    (426) 0x421044 BL	40fa00

    (426) 0x421048 LDR	X8, [SP, #112]

    (426) 0x42104c CMP	X8, #1

    (426) 0x421050 B.LE	42106c

    (426) 0x421054 LDUR	X2, [X29, #432]

    (426) 0x421058 ORR	X1, XZR, X22

    (426) 0x42105c ORR	X3, XZR, X23

    (426) 0x421060 MOVZ	W0, #12

    (426) 0x421064 BL	485620

    (426) 0x421068 BL	485a00

    (426) 0x42106c CMP	X21, #1

    (426) 0x421070 B.LT	42110c

    (426) 0x421074 LDR	X10, [X22, #24]

    (426) 0x421078 ORR	X8, XZR, XZR

    (426) 0x42107c ORR	X9, XZR, XZR

    (426) 0x421080 LDR	X11, [X10]

    (426) 0x421084 B	421094

      (431) 0x421088 ORR	X11, XZR, X14

      (431) 0x42108c CMP	X9, X21

      (431) 0x421090 B.EQ	42110c

      (431) 0x421094 ADD	X9, X9, #1

      (431) 0x421098 LDR	X14, [X10, X9,LSL #3]

      (431) 0x42109c CMP	X11, X14

      (431) 0x4210a0 B.GE	421088

      (431) 0x4210a4 LDR	X12, [X22, #32]

      (431) 0x4210a8 LDUR	X13, [X29, #440]

      (431) 0x4210ac B	4210d8

0x4210b0 HINT	#0

0x4210b4 HINT	#0

0x4210b8 HINT	#0

0x4210bc HINT	#0

        (432) 0x4210c0 STR	X15, [X23, X8,LSL #3]

        (432) 0x4210c4 LDR	X14, [X10, X9,LSL #3]

        (432) 0x4210c8 ADD	X11, X11, #1

        (432) 0x4210cc ADD	X8, X8, #1

        (432) 0x4210d0 CMP	X11, X14

        (432) 0x4210d4 B.GE	421088

        (432) 0x4210d8 LDR	X14, [X12, X11,LSL #3]

        (432) 0x4210dc LDR	X16, [X23, X8,LSL #3]

        (432) 0x4210e0 LDR	X15, [X13, X14,LSL #3]

        (432) 0x4210e4 CMP	X16, #0

        (432) 0x4210e8 CCMP	X15, #1, #8, #0

        (432) 0x4210ec B.LT	4210c0

        (432) 0x4210f0 STR	XZR, [X13, X14,LSL #3]

        (432) 0x4210f4 LDR	X14, [X10, X9,LSL #3]

        (432) 0x4210f8 ADD	X11, X11, #1

        (432) 0x4210fc ADD	X8, X8, #1

        (432) 0x421100 CMP	X11, X14

        (432) 0x421104 B.LT	4210d8

      (431) 0x421108 B	421088

    (426) 0x42110c LDR	X8, [SP, #112]

    (426) 0x421110 CMP	X8, #1

    (426) 0x421114 B.LE	421130

    (426) 0x421118 LDUR	X3, [X29, #432]

    (426) 0x42111c ORR	X1, XZR, X22

    (426) 0x421120 ORR	X2, XZR, X23

    (426) 0x421124 MOVZ	W0, #11

    (426) 0x421128 BL	485620

    (426) 0x42112c BL	485a00

    (426) 0x421130 SUB	X3, X29, #112

    (426) 0x421134 SUB	X4, X29, #96

    (426) 0x421138 SUB	X5, X29, #88

    (426) 0x42113c SUB	X6, X29, #72

    (426) 0x421140 STP	X25, X19, [SP, #16]

    (426) 0x421144 SUB	X7, X29, #8

    (426) 0x421148 SUB	X8, X29, #32

    (426) 0x42114c STP	X8, X20, [SP]

    (426) 0x421150 ADRP	X0,

    (426) 0x421154 ADD	X0, X0, #952

    (426) 0x421158 MOVZ	W1, #9

    (426) 0x42115c ADRP	X2, 42115c

    (426) 0x421160 ADD	X2, X2, #3248

    (426) 0x421164 BL	40fa00

    (426) 0x421168 CMP	X21, #1

    (426) 0x42116c B.LT	4211c4

  (430) 0x421170 LDR	X8, [X22, #24]

  (430) 0x421174 LDUR	X9, [X29, #440]

  (430) 0x421178 CMP	X21, #1

  (430) 0x42117c LDR	X10, [X8]

  (430) 0x421180 B.NE	4211ec

  (430) 0x421184 ORR	X11, XZR, XZR

  (430) 0x421188 ORR	X12, XZR, XZR

  (430) 0x42118c TBZ	W21, #0, 4211c4

  (430) 0x421190 ADD	X12, X12, #1

  (430) 0x421194 LDR	X13, [X8, X12,LSL #3]

  (430) 0x421198 CMP	X10, X13

  (430) 0x42119c B.GE	4211c4

  (430) 0x4211a0 LDR	X13, [X22, #32]

  (430) 0x4211a4 ADD	X11, X23, X11,LSL #3

    (433) 0x4211a8 LDR	X14, [X13, X10,LSL #3]

    (433) 0x4211ac ADD	X10, X10, #1

    (433) 0x4211b0 LDR	X14, [X9, X14,LSL #3]

    (433) 0x4211b4 STR	X14, [X11], #8

    (433) 0x4211b8 LDR	X14, [X8, X12,LSL #3]

    (433) 0x4211bc CMP	X10, X14

    (433) 0x4211c0 B.LT	4211a8

    (426) 0x4211c4 LDR	X8, [SP, #112]

    (426) 0x4211c8 CMP	X8, #1

    (426) 0x4211cc B.LE	420f00

    (426) 0x4211d0 LDUR	X3, [X29, #432]

    (426) 0x4211d4 ORR	X1, XZR, X22

    (426) 0x4211d8 ORR	X2, XZR, X23

    (426) 0x4211dc MOVZ	W0, #11

    (426) 0x4211e0 BL	485620

    (426) 0x4211e4 BL	485a00

    (426) 0x4211e8 B	420f00

(427) 0x4211ec ORR	X11, XZR, XZR

(427) 0x4211f0 ORR	X12, XZR, XZR

(427) 0x4211f4 B	421208

0x4211f8 HINT	#0

0x4211fc HINT	#0

(427) 0x421200 CMP	X12, X27

(427) 0x421204 B.EQ	42118c

(427) 0x421208 ORR	X14, X12, #4096

(427) 0x42120c LDR	X13, [X8, X14,LSL #3]

(427) 0x421210 CMP	X10, X13

(427) 0x421214 B.GE	421240

(427) 0x421218 LDR	X15, [X22, #32]

(427) 0x42121c HINT	#0

  (429) 0x421220 LDR	X13, [X15, X10,LSL #3]

  (429) 0x421224 ADD	X10, X10, #1

  (429) 0x421228 LDR	X13, [X9, X13,LSL #3]

  (429) 0x42122c STR	X13, [X23, X11,LSL #3]

  (429) 0x421230 ADD	X11, X11, #1

  (429) 0x421234 LDR	X13, [X8, X14,LSL #3]

  (429) 0x421238 CMP	X10, X13

  (429) 0x42123c B.LT	421220

(427) 0x421240 ADD	X12, X12, #2

(427) 0x421244 LDR	X10, [X8, X12,LSL #3]

(427) 0x421248 CMP	X13, X10

(427) 0x42124c B.GE	421200

(427) 0x421250 LDR	X14, [X22, #32]

(427) 0x421254 HINT	#0

(427) 0x421258 HINT	#0

(427) 0x42125c HINT	#0

  (428) 0x421260 LDR	X10, [X14, X13,LSL #3]

  (428) 0x421264 ADD	X13, X13, #1

  (428) 0x421268 LDR	X10, [X9, X10,LSL #3]

  (428) 0x42126c STR	X10, [X23, X11,LSL #3]

  (428) 0x421270 ADD	X11, X11, #1

  (428) 0x421274 LDR	X10, [X8, X12,LSL #3]

  (428) 0x421278 CMP	X13, X10

  (428) 0x42127c B.LT	421260

(427) 0x421280 B	421200

0x421284 LDUR	X0, [X29, #424]

0x421288 BL	4ae530

0x42128c LDUR	X0, [X29, #416]

0x421290 STUR	XZR, [X29, #424]

0x421294 BL	4ae530

0x421298 LDR	X0, [SP, #88]

0x42129c STUR	XZR, [X29, #416]

0x4212a0 BL	4ae530

0x4212a4 LDR	X0, [SP, #80]

0x4212a8 STR	XZR, [SP, #88]

0x4212ac BL	4ae530

0x4212b0 LDUR	X8, [X29, #448]

0x4212b4 STR	XZR, [SP, #80]

0x4212b8 CBZ	X8, 4212c8

0x4212bc LDUR	X0, [X29, #408]

0x4212c0 BL	4ae530

0x4212c4 STUR	XZR, [X29, #408]

0x4212c8 ORR	X0, XZR, X24

0x4212cc BL	4ae530

0x4212d0 ORR	X0, XZR, X23

0x4212d4 BL	4ae530

0x4212d8 LDUR	X0, [X29, #432]

0x4212dc BL	4ae530

0x4212e0 LDUR	X8, [X29, #440]

0x4212e4 LDR	X9, [SP, #56]

0x4212e8 STR	X8, [X9]

0x4212ec ORR	X0, XZR, XZR

0x4212f0 LDR	D8, [SP, #240]

0x4212f4 LDP	X20, X19, [SP, #336]

0x4212f8 LDP	X22, X21, [SP, #320]

0x4212fc LDP	X24, X23, [SP, #304]

0x421300 LDP	X26, X25, [SP, #288]

0x421304 LDP	X28, X27, [SP, #272]

0x421308 LDP	X29, X30, [SP, #256]

0x42130c ADD	SP, SP, #352

0x421310 RET

0x421314 HINT	#0

0x421318 HINT	#0

0x42131c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:1980-2624
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:1980-1997,2058-2086,2100-2106,2113,2126-2132,2139,2145,2154-2170,2176-2179,2186-2205,2211-2212,2219-2223,2230-2255,2262-2291,2305-2307,2320,2327,2338,2354,2393-2425,2435,2492-2505,2513-2516,2581-2583,2589,2608-2618,2624.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.00 to 5.00 cycles (8.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 44.00 to 4.41 cycles (9.99x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.00 to 18.50 cycles (2.38x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 680 bytes. The binary function is storing 368 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	353
loop length	1412
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

41.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00
cycles	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	41.25
Overall L1	44.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 44.00 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420730

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 4207a0 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4afa30 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4afa60 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 4207d4 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 4207d4 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 486250 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 42081c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4eb844>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 42184c <.omp_outlined..13+0x13c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4eb86c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 421874 <.omp_outlined..15+0x14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485620 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eb8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4218c8 <.omp_outlined..15+0x68>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4eb8e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #664	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4218f0 <.omp_outlined..15+0x90>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42092c <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485a00 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420a64 <hypre_BoomerAMGCoarsenPMIS+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 420970 <hypre_BoomerAMGCoarsenPMIS+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420ad0 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC X8, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 420aac <hypre_BoomerAMGCoarsenPMIS+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6f0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420ad0 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
CMP X20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 420ae0 <hypre_BoomerAMGCoarsenPMIS+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420b38 <hypre_BoomerAMGCoarsenPMIS+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4276e0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420b50 <hypre_BoomerAMGCoarsenPMIS+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420b58 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 420b58 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4276e0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 420af8 <hypre_BoomerAMGCoarsenPMIS+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420c20 <hypre_BoomerAMGCoarsenPMIS+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 420ccc <hypre_BoomerAMGCoarsenPMIS+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420bbc <hypre_BoomerAMGCoarsenPMIS+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420d20 <hypre_BoomerAMGCoarsenPMIS+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC X10, X10, XZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420c7c <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
B 420cd0 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 420d30 <hypre_BoomerAMGCoarsenPMIS+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420d14 <hypre_BoomerAMGCoarsenPMIS+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 420d3c <hypre_BoomerAMGCoarsenPMIS+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420e44 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 420cdc <hypre_BoomerAMGCoarsenPMIS+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420e44 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 420d70 <hypre_BoomerAMGCoarsenPMIS+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420e70 <hypre_BoomerAMGCoarsenPMIS+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485620 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 485a00 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420e90 <hypre_BoomerAMGCoarsenPMIS+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X0, <4b4e84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae640 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420eb8 <hypre_BoomerAMGCoarsenPMIS+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X3, <4efeb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X4, <4efebc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3, #3928]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X4, #3784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0270 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 421284 <hypre_BoomerAMGCoarsenPMIS+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X27, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420fac <hypre_BoomerAMGCoarsenPMIS+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 4212c8 <hypre_BoomerAMGCoarsenPMIS+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_coarsen.c:1980-2624
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.00 to 5.00 cycles (8.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.00 to 18.50 cycles (2.38x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 680 bytes. The binary function is storing 368 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	353
loop length	1412
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

41.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00
cycles	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	41.25
Overall L1	44.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 44.00 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420730

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 4207a0 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4afa30 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4afa60 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 4207d4 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 4207d4 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 486250 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 42081c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4eb844>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 42184c <.omp_outlined..13+0x13c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4eb86c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 421874 <.omp_outlined..15+0x14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4208c0 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485620 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4eb8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4218c8 <.omp_outlined..15+0x68>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4eb8e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #664	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4218f0 <.omp_outlined..15+0x90>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #1808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40fa00 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42092c <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485a00 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420a64 <hypre_BoomerAMGCoarsenPMIS+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 420970 <hypre_BoomerAMGCoarsenPMIS+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420ad0 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC X8, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 420aac <hypre_BoomerAMGCoarsenPMIS+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6f0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420ad0 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
CMP X20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 420ae0 <hypre_BoomerAMGCoarsenPMIS+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420b38 <hypre_BoomerAMGCoarsenPMIS+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4276e0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420b50 <hypre_BoomerAMGCoarsenPMIS+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420b58 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 420b58 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4276e0 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 420af8 <hypre_BoomerAMGCoarsenPMIS+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420c20 <hypre_BoomerAMGCoarsenPMIS+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 420ccc <hypre_BoomerAMGCoarsenPMIS+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420bbc <hypre_BoomerAMGCoarsenPMIS+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420d20 <hypre_BoomerAMGCoarsenPMIS+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC X10, X10, XZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420c7c <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
B 420cd0 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 420d30 <hypre_BoomerAMGCoarsenPMIS+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420d14 <hypre_BoomerAMGCoarsenPMIS+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 420d3c <hypre_BoomerAMGCoarsenPMIS+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420e44 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 420cdc <hypre_BoomerAMGCoarsenPMIS+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420e44 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 420d70 <hypre_BoomerAMGCoarsenPMIS+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 420e70 <hypre_BoomerAMGCoarsenPMIS+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 485620 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 485a00 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420e90 <hypre_BoomerAMGCoarsenPMIS+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X0, <4b4e84>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae640 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420eb8 <hypre_BoomerAMGCoarsenPMIS+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X3, <4efeb8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X4, <4efebc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3, #3928]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X4, #3784]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0270 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 421284 <hypre_BoomerAMGCoarsenPMIS+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X27, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420fac <hypre_BoomerAMGCoarsenPMIS+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 4212c8 <hypre_BoomerAMGCoarsenPMIS+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS–	0.02	0.01
▼Loop 439 - par_coarsen.c:2232-2243 - exec–	0.01	0.14
○Loop 440 - par_coarsen.c:2232-2240 - exec	0.01	0.23
○Loop 438 - par_coarsen.c:2254-2255 - exec	0	0
▼Loop 444 - par_coarsen.c:2159-2164 - exec–	0	0
▼Loop 445 - par_coarsen.c:2159-2164 - exec–	0	0
○Loop 447 - par_coarsen.c:2162-2164 - exec	0	0
○Loop 446 - par_coarsen.c:2162-2164 - exec	0	0
○Loop 443 - par_coarsen.c:2170-2170 - exec	0	0
▼Loop 427 - par_coarsen.c:2305-2589 - exec–	0	0
▼Loop 430 - par_coarsen.c:2305-2589 - exec–	0	0
○Loop 433 - par_coarsen.c:2495-2497 - exec	0	0
▼Loop 426 - par_coarsen.c:2305-2589 - exec–	0	0
▼Loop 431 - par_coarsen.c:2402-2415 - exec–	0	0
○Loop 432 - par_coarsen.c:2405-2415 - exec	0	0
○Loop 429 - par_coarsen.c:2495-2497 - exec	0	0
○Loop 428 - par_coarsen.c:2495-2497 - exec	0	0
○Loop 442 - par_coarsen.c:2191-2192 - exec	0	0
▼Loop 434 - par_coarsen.c:2262-2268 - exec–	0	0
▼Loop 435 - par_coarsen.c:2262-2268 - exec–	0	0
○Loop 436 - par_coarsen.c:2265-2268 - exec	0	0
○Loop 437 - par_coarsen.c:2265-2268 - exec	0	0
○Loop 441 - par_coarsen.c:2203-2223 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code