OV - exec - Function .omp_outlined..7#0x4a2740

	Function: .omp_outlined..7#0x4a2740	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage: 0.4%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x4a2740 SUB	SP, SP, #112

0x4a2744 STP	X29, X30, [SP, #16]

0x4a2748 STP	X28, X27, [SP, #32]

0x4a274c STP	X26, X25, [SP, #48]

0x4a2750 STP	X24, X23, [SP, #64]

0x4a2754 STP	X22, X21, [SP, #80]

0x4a2758 STP	X20, X19, [SP, #96]

0x4a275c ADD	X29, SP, #16

0x4a2760 ORR	X25, XZR, X7

0x4a2764 STR	X6, [SP, #8]

0x4a2768 ORR	X19, XZR, X5

0x4a276c ORR	X24, XZR, X4

0x4a2770 ORR	X28, XZR, X3

0x4a2774 ORR	X22, XZR, X2

0x4a2778 ORR	X27, XZR, X0

0x4a277c BL	4b05c0

0x4a2780 ORR	X26, XZR, X0

0x4a2784 BL	4b05e0

0x4a2788 ORR	X20, XZR, X0

0x4a278c LDR	X0, [X22]

0x4a2790 BL	4a4c20

0x4a2794 ORR	X21, XZR, X0

0x4a2798 LDR	X0, [X22]

0x4a279c BL	4a4cb0

0x4a27a0 ADRP	X23,

0x4a27a4 ORR	X22, XZR, X0

0x4a27a8 CMP	X21, X0

0x4a27ac LDR	X23, [X23, #4056]

0x4a27b0 B.LE	4a27e4

0x4a27b4 LDR	X0, [X23]

0x4a27b8 ADRP	X1,

0x4a27bc ADD	X1, X1, #1027

0x4a27c0 ADRP	X2,

0x4a27c4 ADD	X2, X2, #137

0x4a27c8 BL	4ae6f0

0x4a27cc ORR	X3, XZR, XZR

0x4a27d0 ADRP	X0,

0x4a27d4 ADD	X0, X0, #3768

0x4a27d8 MOVZ	W1, #471

0x4a27dc MOVZ	W2, #1

0x4a27e0 BL	4b0fc0

0x4a27e4 TBNZ	X21, #63, 4a27f4

0x4a27e8 LDR	X8, [X28]

0x4a27ec CMP	X21, X8

0x4a27f0 B.LE	4a2828

0x4a27f4 LDR	X0, [X23]

0x4a27f8 ADRP	X1,

0x4a27fc ADD	X1, X1, #1027

0x4a2800 ADRP	X2,

0x4a2804 ADD	X2, X2, #152

0x4a2808 BL	4ae6f0

0x4a280c ORR	X3, XZR, XZR

0x4a2810 ADRP	X0,

0x4a2814 ADD	X0, X0, #3768

0x4a2818 MOVZ	W1, #472

0x4a281c MOVZ	W2, #1

0x4a2820 BL	4b0fc0

0x4a2824 LDR	X8, [X28]

0x4a2828 TBNZ	X22, #63, 4a2834

0x4a282c CMP	X22, X8

0x4a2830 B.LE	4a2864

0x4a2834 LDR	X0, [X23]

0x4a2838 ADRP	X1,

0x4a283c ADD	X1, X1, #1027

0x4a2840 ADRP	X2,

0x4a2844 ADD	X2, X2, #187

0x4a2848 BL	4ae6f0

0x4a284c ORR	X3, XZR, XZR

0x4a2850 ADRP	X0,

0x4a2854 ADD	X0, X0, #3768

0x4a2858 MOVZ	W1, #473

0x4a285c MOVZ	W2, #1

0x4a2860 BL	4b0fc0

0x4a2864 LDR	X9, [X19]

0x4a2868 LDR	X8, [X24]

0x4a286c MADD	X10, X20, X9, XZR

0x4a2870 UBFM	X2, X9, #61, #60

0x4a2874 ADD	X0, X8, X10,LSL #3

0x4a2878 RDVL	X8, #1

0x4a287c CMP	X8, #17

0x4a2880 B.CS	4a2890

0x4a2884 ORR	W1, WZR, WZR

0x4a2888 BL	40f6f0

0x4a288c B	4a28b0

0x4a2890 WHILELO	P0.B, XZR, X2

0x4a2894 ORR	X8, XZR, XZR

0x4a2898 DUP	Z0.B, #0

0x4a289c HINT	#0

(1746) 0x4a28a0 ST1B	{Z0.B}, P0, [X0, X8]

(1746) 0x4a28a4 INCP	X8, P0.B

(1746) 0x4a28a8 WHILELO	P0.B, X8, X2

(1746) 0x4a28ac B.MI	4a28a0

0x4a28b0 LDR	X8, [SP, #8]

0x4a28b4 LDR	X8, [X8]

0x4a28b8 LDR	X9, [X8, X21,LSL #3]

0x4a28bc LDR	X10, [X8, X22,LSL #3]

0x4a28c0 CMP	X9, X10

0x4a28c4 B.GE	4a2908

0x4a28c8 LDR	X10, [X25]

0x4a28cc LDR	X11, [X24]

0x4a28d0 HINT	#0

0x4a28d4 HINT	#0

0x4a28d8 HINT	#0

0x4a28dc HINT	#0

(1754) 0x4a28e0 LDR	X12, [X10, X9,LSL #3]

(1754) 0x4a28e4 LDR	X13, [X19]

(1754) 0x4a28e8 ADD	X9, X9, #1

(1754) 0x4a28ec MADD	X12, X20, X13, X12

(1754) 0x4a28f0 LDR	X13, [X11, X12,LSL #3]

(1754) 0x4a28f4 ADD	X13, X13, #1

(1754) 0x4a28f8 STR	X13, [X11, X12,LSL #3]

(1754) 0x4a28fc LDR	X12, [X8, X22,LSL #3]

(1754) 0x4a2900 CMP	X9, X12

(1754) 0x4a2904 B.LT	4a28e0

0x4a2908 LDR	W27, [X27]

0x4a290c ADRP	X0,

0x4a2910 ADD	X0, X0, #336

0x4a2914 ORR	W1, WZR, W27

0x4a2918 BL	40f900

0x4a291c LDR	X9, [X19]

0x4a2920 ADD	X28, X20, #1

0x4a2924 MADD	X10, X9, X20, XZR

0x4a2928 MADD	X8, X9, X28, XZR

0x4a292c ADD	X11, X10, #1

0x4a2930 CMP	X11, X8

0x4a2934 B.GE	4a2980

0x4a2938 LDR	X8, [X24]

0x4a293c HINT	#0

(1753) 0x4a2940 SDIV	X12, X11, X26

(1753) 0x4a2944 MSUB	X13, X26, X12, X11

(1753) 0x4a2948 MADD	X12, X9, X13, X12

(1753) 0x4a294c SDIV	X13, X10, X26

(1753) 0x4a2950 MSUB	X10, X13, X26, X10

(1753) 0x4a2954 MADD	X9, X9, X10, X13

(1753) 0x4a2958 LDR	X10, [X8, X12,LSL #3]

(1753) 0x4a295c LDR	X9, [X8, X9,LSL #3]

(1753) 0x4a2960 ADD	X9, X10, X9

(1753) 0x4a2964 ORR	X10, XZR, X11

(1753) 0x4a2968 ADD	X11, X11, #1

(1753) 0x4a296c STR	X9, [X8, X12,LSL #3]

(1753) 0x4a2970 LDR	X9, [X19]

(1753) 0x4a2974 MADD	X12, X9, X28, XZR

(1753) 0x4a2978 CMP	X11, X12

(1753) 0x4a297c B.LT	4a2940

0x4a2980 LDR	X23, [X29, #96]

0x4a2984 ORR	W1, WZR, W27

0x4a2988 ADRP	X0,

0x4a298c ADD	X0, X0, #360

0x4a2990 BL	40f900

0x4a2994 ORR	W1, WZR, W27

0x4a2998 ADRP	X0,

0x4a299c ADD	X0, X0, #384

0x4a29a0 BL	40f4c0

0x4a29a4 CBZ	W0, 4a2a18

0x4a29a8 CMP	X26, #2

0x4a29ac B.LT	4a2a08

0x4a29b0 LDR	X8, [X24]

0x4a29b4 MOVZ	W9, #1

0x4a29b8 HINT	#0

0x4a29bc HINT	#0

(1752) 0x4a29c0 LDR	X10, [X19]

(1752) 0x4a29c4 MADD	X11, X10, X9, XZR

(1752) 0x4a29c8 ADD	X9, X9, #1

(1752) 0x4a29cc MADD	X12, X10, X9, XZR

(1752) 0x4a29d0 CMP	X26, X9

(1752) 0x4a29d4 SUB	X11, X11, #1

(1752) 0x4a29d8 SUB	X12, X12, #1

(1752) 0x4a29dc SDIV	X13, X11, X26

(1752) 0x4a29e0 MSUB	X11, X13, X26, X11

(1752) 0x4a29e4 SDIV	X14, X12, X26

(1752) 0x4a29e8 MSUB	X12, X14, X26, X12

(1752) 0x4a29ec MADD	X11, X10, X11, X13

(1752) 0x4a29f0 MADD	X10, X10, X12, X14

(1752) 0x4a29f4 LDR	X11, [X8, X11,LSL #3]

(1752) 0x4a29f8 LDR	X12, [X8, X10,LSL #3]

(1752) 0x4a29fc ADD	X11, X12, X11

(1752) 0x4a2a00 STR	X11, [X8, X10,LSL #3]

(1752) 0x4a2a04 B.NE	4a29c0

0x4a2a08 ORR	W1, WZR, W27

0x4a2a0c ADRP	X0,

0x4a2a10 ADD	X0, X0, #384

0x4a2a14 BL	40f990

0x4a2a18 LDR	X8, [X29, #120]

0x4a2a1c ORR	W1, WZR, W27

0x4a2a20 ADRP	X0,

0x4a2a24 ADD	X0, X0, #408

0x4a2a28 STR	X8, [SP]

0x4a2a2c BL	40f900

0x4a2a30 CMP	X20, #1

0x4a2a34 B.LT	4a2a94

0x4a2a38 LDR	X10, [X19]

0x4a2a3c MOVN	X9, #0

0x4a2a40 MADD	X8, X10, X20, XZR

0x4a2a44 MADD	X11, X10, X28, X9

0x4a2a48 CMP	X8, X11

0x4a2a4c B.GE	4a2a94

0x4a2a50 SUB	X11, X8, #1

0x4a2a54 SDIV	X12, X11, X26

0x4a2a58 MSUB	X11, X12, X26, X11

0x4a2a5c MADD	X12, X10, X11, X12

0x4a2a60 LDR	X11, [X24]

0x4a2a64 LDR	X12, [X11, X12,LSL #3]

(1751) 0x4a2a68 SDIV	X13, X8, X26

(1751) 0x4a2a6c MSUB	X14, X26, X13, X8

(1751) 0x4a2a70 ADD	X8, X8, #1

(1751) 0x4a2a74 MADD	X10, X10, X14, X13

(1751) 0x4a2a78 LDR	X13, [X11, X10,LSL #3]

(1751) 0x4a2a7c ADD	X13, X13, X12

(1751) 0x4a2a80 STR	X13, [X11, X10,LSL #3]

(1751) 0x4a2a84 LDR	X10, [X19]

(1751) 0x4a2a88 MADD	X13, X10, X28, X9

(1751) 0x4a2a8c CMP	X8, X13

(1751) 0x4a2a90 B.LT	4a2a68

0x4a2a94 ORR	W1, WZR, W27

0x4a2a98 ADRP	X0,

0x4a2a9c ADD	X0, X0, #432

0x4a2aa0 BL	40f900

0x4a2aa4 LDR	X8, [X23]

0x4a2aa8 CBZ	X8, 4a2b64

0x4a2aac CMP	X22, X21

0x4a2ab0 B.LE	4a2bfc

0x4a2ab4 LDP	X11, X10, [X29, #104]

0x4a2ab8 LDR	X8, [SP, #8]

0x4a2abc LDR	X13, [X25]

0x4a2ac0 SUB	X13, X13, #8

0x4a2ac4 LDR	X8, [X8]

0x4a2ac8 LDR	X12, [X10]

0x4a2acc LDR	X10, [X11]

0x4a2ad0 LDR	X11, [SP]

0x4a2ad4 LDR	X9, [X24]

0x4a2ad8 LDR	X11, [X11]

0x4a2adc LDR	X14, [X8, X22,LSL #3]

0x4a2ae0 SUB	X12, X12, #8

0x4a2ae4 SUB	X22, X22, #1

0x4a2ae8 LDR	X15, [X8, X22,LSL #3]

0x4a2aec CMP	X14, X15

0x4a2af0 B.GT	4a2b20

0x4a2af4 HINT	#0

0x4a2af8 HINT	#0

0x4a2afc HINT	#0

  (1750) 0x4a2b00 ORR	X14, XZR, X15

  (1750) 0x4a2b04 CMP	X22, X21

  (1750) 0x4a2b08 B.LE	4a2bfc

  (1750) 0x4a2b0c SUB	X22, X22, #1

  (1750) 0x4a2b10 LDR	X15, [X8, X22,LSL #3]

  (1750) 0x4a2b14 CMP	X14, X15

  (1750) 0x4a2b18 B.LE	4a2b00

(1749) 0x4a2b1c HINT	#0

(1749) 0x4a2b20 LDR	X15, [X13, X14,LSL #3]

(1749) 0x4a2b24 LDR	X16, [X19]

(1749) 0x4a2b28 LDR	D0, [X12, X14,LSL #3]

(1749) 0x4a2b2c SUB	X14, X14, #1

(1749) 0x4a2b30 MADD	X16, X20, X16, X15

(1749) 0x4a2b34 LDR	X17, [X9, X16,LSL #3]

(1749) 0x4a2b38 SUB	X17, X17, #1

(1749) 0x4a2b3c STR	X17, [X9, X16,LSL #3]

(1749) 0x4a2b40 LDR	X16, [X19]

(1749) 0x4a2b44 MADD	X15, X20, X16, X15

(1749) 0x4a2b48 LDR	X15, [X9, X15,LSL #3]

(1749) 0x4a2b4c STR	D0, [X10, X15,LSL #3]

(1749) 0x4a2b50 STR	X22, [X11, X15,LSL #3]

(1749) 0x4a2b54 LDR	X15, [X8, X22,LSL #3]

(1749) 0x4a2b58 CMP	X14, X15

(1749) 0x4a2b5c B.GT	4a2b20

(1749) 0x4a2b60 B	4a2b00

0x4a2b64 CMP	X22, X21

0x4a2b68 B.LE	4a2bfc

0x4a2b6c LDP	X10, X8, [SP]

0x4a2b70 LDR	X11, [X25]

0x4a2b74 LDR	X9, [X24]

0x4a2b78 SUB	X11, X11, #8

0x4a2b7c LDR	X8, [X8]

0x4a2b80 LDR	X10, [X10]

0x4a2b84 LDR	X12, [X8, X22,LSL #3]

0x4a2b88 SUB	X22, X22, #1

0x4a2b8c LDR	X13, [X8, X22,LSL #3]

0x4a2b90 CMP	X12, X13

0x4a2b94 B.GT	4a2bc0

0x4a2b98 HINT	#0

0x4a2b9c HINT	#0

  (1748) 0x4a2ba0 ORR	X12, XZR, X13

  (1748) 0x4a2ba4 CMP	X22, X21

  (1748) 0x4a2ba8 B.LE	4a2bfc

  (1748) 0x4a2bac SUB	X22, X22, #1

  (1748) 0x4a2bb0 LDR	X13, [X8, X22,LSL #3]

  (1748) 0x4a2bb4 CMP	X12, X13

  (1748) 0x4a2bb8 B.LE	4a2ba0

(1747) 0x4a2bbc HINT	#0

(1747) 0x4a2bc0 LDR	X13, [X11, X12,LSL #3]

(1747) 0x4a2bc4 LDR	X14, [X19]

(1747) 0x4a2bc8 SUB	X12, X12, #1

(1747) 0x4a2bcc MADD	X14, X20, X14, X13

(1747) 0x4a2bd0 LDR	X15, [X9, X14,LSL #3]

(1747) 0x4a2bd4 SUB	X15, X15, #1

(1747) 0x4a2bd8 STR	X15, [X9, X14,LSL #3]

(1747) 0x4a2bdc LDR	X14, [X19]

(1747) 0x4a2be0 MADD	X13, X20, X14, X13

(1747) 0x4a2be4 LDR	X13, [X9, X13,LSL #3]

(1747) 0x4a2be8 STR	X22, [X10, X13,LSL #3]

(1747) 0x4a2bec LDR	X13, [X8, X22,LSL #3]

(1747) 0x4a2bf0 CMP	X12, X13

(1747) 0x4a2bf4 B.GT	4a2bc0

(1747) 0x4a2bf8 B	4a2ba0

0x4a2bfc LDP	X20, X19, [SP, #96]

0x4a2c00 LDP	X22, X21, [SP, #80]

0x4a2c04 LDP	X24, X23, [SP, #64]

0x4a2c08 LDP	X26, X25, [SP, #48]

0x4a2c0c LDP	X28, X27, [SP, #32]

0x4a2c10 LDP	X29, X30, [SP, #16]

0x4a2c14 ADD	SP, SP, #112

0x4a2c18 RET

0x4a2c1c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.25 to 2.00 cycles (14.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 28.25 to 10.00 cycles (2.83x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.25 to 8.50 cycles (3.32x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 460 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00
cycles	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.88
Overall L1	28.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

16% of peak load performance is reached (16.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a2740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4c20 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4cb0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X23, <4ef7a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X23, [X23, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4a27e4 <.omp_outlined..7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c27b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c47c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #137	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c37d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X21, #63, 4a27f4 <.omp_outlined..7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2828 <.omp_outlined..7+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c27f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c3810>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X22, #63, 4a2834 <.omp_outlined..7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2864 <.omp_outlined..7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c2838>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4840>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #187	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c3850>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X20, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4a2890 <.omp_outlined..7+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6f0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a28b0 <.omp_outlined..7+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2908 <.omp_outlined..7+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ef90c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2980 <.omp_outlined..7+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
LDR X23, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ef988>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ef998>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4c0 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 4a2a18 <.omp_outlined..7+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a2a08 <.omp_outlined..7+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f990 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa20>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a2a94 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X11, X10, X28, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2a94 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X12, X26, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X11, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 4a2b64 <.omp_outlined..7+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2bfc <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a2b20 <.omp_outlined..7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2bfc <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a2bc0 <.omp_outlined..7+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.25 to 8.50 cycles (3.32x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 460 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00
cycles	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.88
Overall L1	28.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

16% of peak load performance is reached (16.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a2740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4c20 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4cb0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X23, <4ef7a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X23, [X23, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4a27e4 <.omp_outlined..7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c27b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c47c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #137	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c37d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X21, #63, 4a27f4 <.omp_outlined..7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2828 <.omp_outlined..7+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c27f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c3810>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X22, #63, 4a2834 <.omp_outlined..7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2864 <.omp_outlined..7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4c2838>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4840>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #187	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c3850>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X20, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4a2890 <.omp_outlined..7+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6f0 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a28b0 <.omp_outlined..7+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2908 <.omp_outlined..7+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ef90c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #336	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2980 <.omp_outlined..7+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
LDR X23, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ef988>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #360	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ef998>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4c0 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 4a2a18 <.omp_outlined..7+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a2a08 <.omp_outlined..7+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f990 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa20>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #408	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a2a94 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X11, X10, X28, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2a94 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X12, X26, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X11, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4efa98>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #432	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 4a2b64 <.omp_outlined..7+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2bfc <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a2b20 <.omp_outlined..7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a2bfc <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a2bc0 <.omp_outlined..7+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..7#0x4a2740–	0.4	0.15
▼Loop 1749 - csr_matop.c:540-548 - exec–	0.28	0.09
○Loop 1750 - csr_matop.c:540-541 - exec	0	0.01
○Loop 1746 - csr_matop.c:476-476 - exec	0.08	0.02
○Loop 1751 - csr_matop.c:380-527 - exec	0.02	0.01
○Loop 1753 - csr_matop.c:380-500 - exec	0.02	0
○Loop 1754 - csr_matop.c:483-485 - exec	0	0
▼Loop 1747 - csr_matop.c:553-560 - exec–	0	0
○Loop 1748 - csr_matop.c:553-554 - exec	0	0
○Loop 1752 - csr_matop.c:380-513 - exec	0	0

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Code clean check

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code