OV - exec - Function .omp_outlined..30#0x47cf20

	Function: .omp_outlined..30#0x47cf20	Module: exec	Source: ams.c:3662-3682	Coverage: 31.14%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x47cf20 SUB	SP, SP, #160

0x47cf24 STP	X29, X30, [SP, #64]

0x47cf28 STP	X28, X27, [SP, #80]

0x47cf2c STP	X26, X25, [SP, #96]

0x47cf30 STP	X24, X23, [SP, #112]

0x47cf34 STP	X22, X21, [SP, #128]

0x47cf38 STP	X20, X19, [SP, #144]

0x47cf3c ADD	X29, SP, #64

0x47cf40 LDR	X8, [X2]

0x47cf44 SUBS	X19, X8, #1

0x47cf48 B.LT	47cff4

0x47cf4c LDR	X8, [X29, #152]

0x47cf50 LDP	X10, X9, [X29, #128]

0x47cf54 LDP	X12, X11, [X29, #112]

0x47cf58 MOVZ	W2, #34

0x47cf5c LDP	X14, X13, [X29, #96]

0x47cf60 LDR	X15, [X6]

0x47cf64 SUB	X6, X29, #24

0x47cf68 LDR	W1, [X0]

0x47cf6c ADRP	X0,

0x47cf70 ADD	X0, X0, #928

0x47cf74 LDR	X21, [X3]

0x47cf78 SUB	X3, X29, #28

0x47cf7c LDR	X22, [X4]

0x47cf80 SUB	X4, X29, #8

0x47cf84 LDR	X24, [X7]

0x47cf88 MOVZ	W7, #1

0x47cf8c LDR	X8, [X8]

0x47cf90 LDR	X25, [X14]

0x47cf94 LDR	X26, [X13]

0x47cf98 LDR	X27, [X12]

0x47cf9c LDR	X28, [X11]

0x47cfa0 LDR	X20, [X10]

0x47cfa4 MOVZ	W10, #1

0x47cfa8 LDR	X23, [X9]

0x47cfac STR	X5, [SP, #24]

0x47cfb0 SUB	X5, X29, #16

0x47cfb4 STP	X19, XZR, [X29, #1008]

0x47cfb8 STUR	WZR, [X29, #484]

0x47cfbc STR	W1, [SP, #32]

0x47cfc0 STUR	X10, [X29, #488]

0x47cfc4 STR	X10, [SP]

0x47cfc8 STP	X8, X15, [SP, #8]

0x47cfcc BL	40f550

0x47cfd0 LDP	X8, X9, [X29, #1008]

0x47cfd4 CMP	X8, X19

0x47cfd8 CSEL	X10, X8, X19, #11

0x47cfdc CMP	X9, X10

0x47cfe0 B.LE	47d014

  (1375) 0x47cfe4 LDR	W1, [SP, #32]

  (1375) 0x47cfe8 ADRP	X0,

  (1375) 0x47cfec ADD	X0, X0, #952

  (1375) 0x47cff0 BL	40f410

  (1375) 0x47cff4 LDP	X20, X19, [SP, #144]

  (1375) 0x47cff8 LDP	X22, X21, [SP, #128]

  (1375) 0x47cffc LDP	X24, X23, [SP, #112]

  (1375) 0x47d000 LDP	X26, X25, [SP, #96]

  (1375) 0x47d004 LDP	X28, X27, [SP, #80]

  (1375) 0x47d008 LDP	X29, X30, [SP, #64]

  (1375) 0x47d00c ADD	SP, SP, #160

  (1375) 0x47d010 RET

  (1375) 0x47d014 LDP	X3, X2, [SP, #16]

  (1375) 0x47d018 LDR	X8, [X29, #144]

  (1375) 0x47d01c LDR	X4, [SP, #8]

  (1375) 0x47d020 ADD	X10, X10, #1

  (1375) 0x47d024 ADD	X11, X24, #16

  (1375) 0x47d028 ADD	X12, X21, #16

  (1375) 0x47d02c ADD	X13, X27, #16

  (1375) 0x47d030 ADD	X14, X28, #16

  (1375) 0x47d034 LDR	D0, [X2]

  (1375) 0x47d038 B	47d06c

0x47d03c HINT	#0

  (1375) 0x47d040 LDR	D1, [X8]

  (1375) 0x47d044 FMUL	D0, D0, D1

  (1375) 0x47d048 LDR	D1, [X4, X9,LSL #3]

  (1375) 0x47d04c FDIV	D0, D0, D1

  (1375) 0x47d050 LDR	D1, [X23, X9,LSL #3]

  (1375) 0x47d054 FADD	D0, D1, D0

  (1375) 0x47d058 STR	D0, [X23, X9,LSL #3]

  (1375) 0x47d05c LDR	D0, [X2]

  (1375) 0x47d060 ORR	X9, XZR, X15

  (1375) 0x47d064 CMP	X15, X10

  (1375) 0x47d068 B.EQ	47cfe4

  (1375) 0x47d06c LDR	X16, [X22, X9,LSL #3]

  (1375) 0x47d070 LDR	D1, [X21, X16,LSL #3]

  (1375) 0x47d074 FCMP	D1, D0

  (1375) 0x47d078 B.EQ	47d0e0

  (1375) 0x47d07c LDR	D0, [X3, X9,LSL #3]

  (1375) 0x47d080 ADD	X15, X9, #1

  (1375) 0x47d084 LDR	X17, [X22, X15,LSL #3]

  (1375) 0x47d088 CMP	X17, X16

  (1375) 0x47d08c B.LE	47d158

  (1375) 0x47d090 SUB	W18, W17, W16

  (1375) 0x47d094 ANDS	X0, X18, #4160

  (1375) 0x47d098 B.EQ	47d0f4

  (1375) 0x47d09c ORR	X18, XZR, X16

    (1379) 0x47d0a0 LDR	X1, [X24, X18,LSL #3]

    (1379) 0x47d0a4 LDR	D1, [X21, X18,LSL #3]

    (1379) 0x47d0a8 ADD	X18, X18, #1

    (1379) 0x47d0ac SUBS	X0, X0, #1

    (1379) 0x47d0b0 LDR	D2, [X25, X1,LSL #3]

    (1379) 0x47d0b4 FMSUB	D0, D1, D2, D0

    (1379) 0x47d0b8 B.NE	47d0a0

  (1375) 0x47d0bc ORN	X16, XZR, X16

  (1375) 0x47d0c0 ADD	X16, X17, X16

  (1375) 0x47d0c4 CMP	X16, #3

  (1375) 0x47d0c8 B.CS	47d108

  (1375) 0x47d0cc B	47d158

0x47d0d0 HINT	#0

0x47d0d4 HINT	#0

0x47d0d8 HINT	#0

0x47d0dc HINT	#0

(1374) 0x47d0e0 ADD	X15, X9, #1

(1374) 0x47d0e4 ORR	X9, XZR, X15

(1374) 0x47d0e8 CMP	X15, X10

(1374) 0x47d0ec B.NE	47d06c

(1374) 0x47d0f0 B	47cfe4

  (1375) 0x47d0f4 ORR	X18, XZR, X16

  (1375) 0x47d0f8 ORN	X16, XZR, X16

  (1375) 0x47d0fc ADD	X16, X17, X16

  (1375) 0x47d100 CMP	X16, #3

  (1375) 0x47d104 B.CC	47d158

  (1375) 0x47d108 SUB	X16, X17, X18

  (1375) 0x47d10c UBFM	X18, X18, #61, #60

  (1375) 0x47d110 ADD	X17, X11, X18

  (1375) 0x47d114 ADD	X18, X12, X18

  (1375) 0x47d118 HINT	#0

  (1375) 0x47d11c HINT	#0

    (1378) 0x47d120 LDP	X0, X1, [X17, #1008]

    (1378) 0x47d124 LDP	D2, D3, [X18, #1008]

    (1378) 0x47d128 SUBS	X16, X16, #4

    (1378) 0x47d12c LDR	D1, [X25, X0,LSL #3]

    (1378) 0x47d130 FMSUB	D0, D2, D1, D0

    (1378) 0x47d134 LDR	D1, [X25, X1,LSL #3]

    (1378) 0x47d138 FMSUB	D0, D3, D1, D0

    (1378) 0x47d13c LDP	X0, X1, [X17], #32

    (1378) 0x47d140 LDR	D2, [X25, X0,LSL #3]

    (1378) 0x47d144 LDP	D1, D3, [X18], #32

    (1378) 0x47d148 FMSUB	D0, D1, D2, D0

    (1378) 0x47d14c LDR	D1, [X25, X1,LSL #3]

    (1378) 0x47d150 FMSUB	D0, D3, D1, D0

    (1378) 0x47d154 B.NE	47d120

  (1375) 0x47d158 LDR	X17, [X26, X9,LSL #3]

  (1375) 0x47d15c LDR	X16, [X26, X15,LSL #3]

  (1375) 0x47d160 CMP	X16, X17

  (1375) 0x47d164 B.LE	47d040

  (1375) 0x47d168 SUB	W18, W16, W17

  (1375) 0x47d16c ANDS	X0, X18, #4160

  (1375) 0x47d170 B.EQ	47d1b0

  (1375) 0x47d174 ORR	X18, XZR, X17

  (1375) 0x47d178 HINT	#0

  (1375) 0x47d17c HINT	#0

    (1377) 0x47d180 LDR	X1, [X27, X18,LSL #3]

    (1377) 0x47d184 LDR	D1, [X28, X18,LSL #3]

    (1377) 0x47d188 ADD	X18, X18, #1

    (1377) 0x47d18c SUBS	X0, X0, #1

    (1377) 0x47d190 LDR	D2, [X20, X1,LSL #3]

    (1377) 0x47d194 FMSUB	D0, D1, D2, D0

    (1377) 0x47d198 B.NE	47d180

  (1375) 0x47d19c ORN	X17, XZR, X17

  (1375) 0x47d1a0 ADD	X17, X16, X17

  (1375) 0x47d1a4 CMP	X17, #3

  (1375) 0x47d1a8 B.CC	47d040

  (1375) 0x47d1ac B	47d1c4

  (1375) 0x47d1b0 ORR	X18, XZR, X17

  (1375) 0x47d1b4 ORN	X17, XZR, X17

  (1375) 0x47d1b8 ADD	X17, X16, X17

  (1375) 0x47d1bc CMP	X17, #3

  (1375) 0x47d1c0 B.CC	47d040

  (1375) 0x47d1c4 SUB	X16, X16, X18

  (1375) 0x47d1c8 UBFM	X18, X18, #61, #60

  (1375) 0x47d1cc ADD	X17, X13, X18

  (1375) 0x47d1d0 ADD	X18, X14, X18

  (1375) 0x47d1d4 HINT	#0

  (1375) 0x47d1d8 HINT	#0

  (1375) 0x47d1dc HINT	#0

    (1376) 0x47d1e0 LDP	X0, X1, [X17, #1008]

    (1376) 0x47d1e4 LDP	D2, D3, [X18, #1008]

    (1376) 0x47d1e8 SUBS	X16, X16, #4

    (1376) 0x47d1ec LDR	D1, [X20, X0,LSL #3]

    (1376) 0x47d1f0 FMSUB	D0, D2, D1, D0

    (1376) 0x47d1f4 LDR	D1, [X20, X1,LSL #3]

    (1376) 0x47d1f8 FMSUB	D0, D3, D1, D0

    (1376) 0x47d1fc LDP	X0, X1, [X17], #32

    (1376) 0x47d200 LDR	D2, [X20, X0,LSL #3]

    (1376) 0x47d204 LDP	D1, D3, [X18], #32

    (1376) 0x47d208 FMSUB	D0, D1, D2, D0

    (1376) 0x47d20c LDR	D1, [X20, X1,LSL #3]

    (1376) 0x47d210 FMSUB	D0, D3, D1, D0

    (1376) 0x47d214 B.NE	47d1e0

  (1375) 0x47d218 B	47d040

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 10.50 to 2.63 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 0.50 cycles (21.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (16.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47cf20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47cff4 <.omp_outlined..30+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eef6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #928	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X15, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f550 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X10, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47d014 <.omp_outlined..30+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 0.50 cycles (21.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (16.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47cf20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 47cff4 <.omp_outlined..30+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eef6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #928	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X15, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f550 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X10, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 47d014 <.omp_outlined..30+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..30#0x47cf20–	31.14	11.8
▼Loop 1374 - ams.c:3662-3682 - exec–	0	0
▼Loop 1375 - ams.c:3662-3682 - exec–	2.25	0.73
○Loop 1378 - ams.c:3672-3675 - exec	26.35	8.59
○Loop 1379 - ams.c:3672-3675 - exec	2.54	0.83
○Loop 1377 - ams.c:3677-3680 - exec	0	0
○Loop 1376 - ams.c:3677-3680 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code