OV - exec - Function .omp_outlined..22#0x4380e0

	Function: .omp_outlined..22#0x4380e0	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage: 4.84%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x4380e0 SUB	SP, SP, #464

0x4380e4 STP	X29, X30, [SP, #368]

0x4380e8 STP	X28, X27, [SP, #384]

0x4380ec STP	X26, X25, [SP, #400]

0x4380f0 STP	X24, X23, [SP, #416]

0x4380f4 STP	X22, X21, [SP, #432]

0x4380f8 STP	X20, X19, [SP, #448]

0x4380fc ADD	X29, SP, #368

0x438100 LDR	X8, [X29, #376]

0x438104 STUR	X7, [X29, #432]

0x438108 LDR	X0, [X2]

0x43810c ORR	X22, XZR, X6

0x438110 ORR	X26, XZR, X5

0x438114 ORR	X21, XZR, X4

0x438118 STR	X8, [SP, #128]

0x43811c ORR	X24, XZR, X3

0x438120 ORR	X25, XZR, X2

0x438124 LDR	X8, [X29, #368]

0x438128 STR	X8, [SP, #120]

0x43812c LDR	X8, [X29, #360]

0x438130 STR	X8, [SP, #112]

0x438134 LDR	X8, [X29, #352]

0x438138 STR	X8, [SP, #104]

0x43813c LDR	X8, [X29, #344]

0x438140 STR	X8, [SP, #96]

0x438144 LDR	X8, [X29, #336]

0x438148 STR	X8, [SP, #88]

0x43814c LDR	X8, [X29, #328]

0x438150 STR	X8, [SP, #80]

0x438154 LDR	X8, [X29, #320]

0x438158 STR	X8, [SP, #72]

0x43815c LDR	X8, [X29, #312]

0x438160 STR	X8, [SP, #64]

0x438164 LDP	X8, X9, [X29, #296]

0x438168 STP	X8, X9, [X29, #984]

0x43816c LDP	X8, X9, [X29, #280]

0x438170 STP	X8, X9, [X29, #952]

0x438174 LDR	X8, [X29, #272]

0x438178 STR	X8, [SP, #56]

0x43817c LDR	X8, [X29, #264]

0x438180 STR	X8, [SP, #152]

0x438184 LDP	X8, X9, [X29, #248]

0x438188 STP	X8, X9, [X29, #968]

0x43818c LDP	X8, X9, [X29, #232]

0x438190 STP	X8, X9, [X29, #912]

0x438194 LDP	X8, X9, [X29, #216]

0x438198 STP	X8, X9, [X29, #896]

0x43819c LDP	X8, X9, [X29, #200]

0x4381a0 STP	X8, X9, [X29, #880]

0x4381a4 LDR	X8, [X29, #192]

0x4381a8 STR	X8, [SP, #144]

0x4381ac LDP	X9, X8, [X29, #176]

0x4381b0 STUR	X8, [X29, #496]

0x4381b4 LDR	X8, [X29, #168]

0x4381b8 STP	X8, X9, [X29, #864]

0x4381bc LDR	X8, [X29, #160]

0x4381c0 STUR	X8, [X29, #416]

0x4381c4 LDR	X8, [X29, #152]

0x4381c8 STR	X8, [SP, #136]

0x4381cc LDP	X9, X8, [X29, #136]

0x4381d0 LDP	X28, X27, [X29, #96]

0x4381d4 STUR	X8, [X29, #488]

0x4381d8 LDR	X8, [X29, #128]

0x4381dc STP	X8, X9, [X29, #848]

0x4381e0 LDP	X23, X8, [X29, #112]

0x4381e4 STUR	X8, [X29, #424]

0x4381e8 CBZ	X0, 438224

0x4381ec MOVZ	W1, #8

0x4381f0 BL	4ae430

0x4381f4 ORR	X19, XZR, X0

0x4381f8 LDR	X0, [X24]

0x4381fc CBZ	X0, 438230

0x438200 MOVZ	W1, #8

0x438204 BL	4ae430

0x438208 ORR	X20, XZR, X0

0x43820c LDR	X0, [X21]

0x438210 CBZ	X0, 43823c

0x438214 MOVZ	W1, #8

0x438218 BL	4ae430

0x43821c ORR	X21, XZR, X0

0x438220 B	438240

0x438224 ORR	X19, XZR, XZR

0x438228 LDR	X0, [X24]

0x43822c CBNZ	X0, 438200

0x438230 ORR	X20, XZR, XZR

0x438234 LDR	X0, [X21]

0x438238 CBNZ	X0, 438214

0x43823c ORR	X21, XZR, XZR

0x438240 LDR	X8, [X26]

0x438244 LDR	X9, [X22]

0x438248 MOVZ	W1, #8

0x43824c CMP	X8, X9

0x438250 CSEL	X0, X8, X9, #12

0x438254 BL	4ae430

0x438258 LDR	X8, [X25]

0x43825c ORR	X22, XZR, X0

0x438260 CMP	X8, #1

0x438264 B.LT	438294

0x438268 ORR	X8, XZR, XZR

0x43826c MOVN	X9, #0

0x438270 HINT	#0

0x438274 HINT	#0

0x438278 HINT	#0

0x43827c HINT	#0

(1274) 0x438280 STR	X9, [X19, X8,LSL #3]

(1274) 0x438284 ADD	X8, X8, #1

(1274) 0x438288 LDR	X10, [X25]

(1274) 0x43828c CMP	X8, X10

(1274) 0x438290 B.LT	438280

0x438294 LDR	X8, [X24]

0x438298 CMP	X8, #1

0x43829c B.LT	4382bc

0x4382a0 ORR	X8, XZR, XZR

0x4382a4 MOVN	X9, #0

(1273) 0x4382a8 STR	X9, [X20, X8,LSL #3]

(1273) 0x4382ac ADD	X8, X8, #1

(1273) 0x4382b0 LDR	X10, [X24]

(1273) 0x4382b4 CMP	X8, X10

(1273) 0x4382b8 B.LT	4382a8

0x4382bc BL	4b05e0

0x4382c0 ORR	X24, XZR, X0

0x4382c4 BL	4b05c0

0x4382c8 LDR	X9, [X27]

0x4382cc SUB	X11, X0, #1

0x4382d0 CMP	X24, X11

0x4382d4 SDIV	X10, X9, X0

0x4382d8 MADD	X8, X10, X24, XZR

0x4382dc ADD	X10, X10, X8

0x4382e0 CSEL	X9, X9, X10, #0

0x4382e4 CMP	X8, X9

0x4382e8 B.GE	438bd8

0x4382ec LDUR	X10, [X29, #432]

0x4382f0 LDUR	X12, [X29, #488]

0x4382f4 LDR	X11, [X28]

0x4382f8 CNTW	X26, ALL

0x4382fc PTRUE	P0.D, ALL

0x438300 LDR	X10, [X10]

0x438304 LDR	X13, [X12]

0x438308 LDR	X12, [SP, #136]

0x43830c LDR	X15, [X12]

0x438310 LDUR	X12, [X29, #496]

0x438314 LDR	X10, [X10, X11,LSL #3]

0x438318 LDR	X11, [X23]

0x43831c LDR	X16, [X12]

0x438320 LDR	X12, [SP, #144]

0x438324 STUR	X11, [X29, #432]

0x438328 LDUR	X11, [X29, #424]

0x43832c ADD	X25, X8, X10

0x438330 LDUR	X8, [X29, #464]

0x438334 ADD	X9, X9, X10

0x438338 LDR	X10, [X11]

0x43833c LDR	X8, [X8]

0x438340 LDR	X12, [X12]

0x438344 LDUR	X11, [X29, #336]

0x438348 LDR	X14, [X11]

0x43834c LDUR	X11, [X29, #344]

0x438350 LDR	X1, [X11]

0x438354 LDUR	X11, [X29, #416]

0x438358 LDR	X11, [X11]

0x43835c STP	X11, X10, [X29, #928]

0x438360 LDUR	X11, [X29, #352]

0x438364 LDR	X17, [X11]

0x438368 LDUR	X11, [X29, #360]

0x43836c LDR	X2, [X11]

0x438370 LDUR	X11, [X29, #368]

0x438374 LDR	X3, [X11]

0x438378 LDUR	X11, [X29, #376]

0x43837c LDR	X4, [X11]

0x438380 LDUR	X11, [X29, #384]

0x438384 LDR	X5, [X11]

0x438388 LDUR	X11, [X29, #392]

0x43838c LDR	X6, [X11]

0x438390 LDUR	X11, [X29, #400]

0x438394 LDR	X23, [X11]

0x438398 LDUR	X11, [X29, #408]

0x43839c LDR	X24, [X11]

0x4383a0 LDUR	X11, [X29, #456]

0x4383a4 LDR	X11, [X11]

0x4383a8 STP	X9, X11, [X29, #912]

0x4383ac STR	X8, [SP, #48]

0x4383b0 ADD	X9, X15, #8

0x4383b4 LDUR	X8, [X29, #472]

0x4383b8 LDR	X8, [X8]

0x4383bc STUR	X8, [X29, #392]

0x4383c0 LDUR	X8, [X29, #480]

0x4383c4 LDR	X30, [X8]

0x4383c8 LDR	X8, [SP, #152]

0x4383cc LDR	X8, [X8]

0x4383d0 STUR	X8, [X29, #384]

0x4383d4 ADD	X8, X13, #8

0x4383d8 STP	X12, X15, [SP, #32]

0x4383dc STP	X16, X13, [SP, #160]

0x4383e0 STP	X8, X9, [SP, #16]

0x4383e4 ADD	X9, X12, #8

0x4383e8 ADD	X8, X16, #8

0x4383ec STP	X8, X9, [SP]

0x4383f0 STP	X2, X1, [X29, #880]

0x4383f4 STP	X4, X3, [X29, #864]

0x4383f8 STP	X6, X5, [X29, #848]

0x4383fc STP	X24, X23, [SP, #176]

0x438400 B	438414

  (1261) 0x438404 LDUR	X8, [X29, #400]

  (1261) 0x438408 ADD	X25, X25, #1

  (1261) 0x43840c CMP	X25, X8

  (1261) 0x438410 B.GE	438bd8

  (1261) 0x438414 LDUR	X8, [X29, #432]

  (1261) 0x438418 LDR	X12, [X8, X25,LSL #3]

  (1261) 0x43841c LDUR	X8, [X29, #424]

  (1261) 0x438420 ADD	X13, X12, #1

  (1261) 0x438424 LDR	X8, [X8, X12,LSL #3]

  (1261) 0x438428 LDR	X10, [X14, X12,LSL #3]

  (1261) 0x43842c LDR	X11, [X14, X13,LSL #3]

  (1261) 0x438430 ADD	X9, X11, X8

  (1261) 0x438434 SUB	X9, X9, X10

  (1261) 0x438438 CMP	X8, X9

  (1261) 0x43843c B.GE	4384d8

  (1261) 0x438440 SUB	W16, W11, W10

  (1261) 0x438444 ADD	X15, X10, #1

  (1261) 0x438448 TBZ	W16, #0, 438474

  (1261) 0x43844c LDR	X16, [X28]

  (1261) 0x438450 LDR	X18, [SP, #168]

  (1261) 0x438454 LDR	X16, [X1, X16,LSL #3]

  (1261) 0x438458 STR	XZR, [X18, X10,LSL #3]

  (1261) 0x43845c LDR	X18, [SP, #40]

  (1261) 0x438460 LDR	X16, [X16, X8,LSL #3]

  (1261) 0x438464 ADD	X8, X8, #1

  (1261) 0x438468 STR	X10, [X21, X16,LSL #3]

  (1261) 0x43846c STR	X16, [X18, X10,LSL #3]

  (1261) 0x438470 ORR	X10, XZR, X15

  (1261) 0x438474 CMP	X11, X15

  (1261) 0x438478 B.EQ	4384d8

  (1261) 0x43847c LDP	X16, X11, [SP, #16]

  (1261) 0x438480 UBFM	X15, X10, #61, #60

  (1261) 0x438484 ADD	X11, X11, X15

  (1261) 0x438488 ADD	X16, X16, X15

    (1268) 0x43848c LDR	X15, [X28]

    (1268) 0x438490 UBFM	X0, X8, #61, #60

    (1268) 0x438494 ADD	X8, X8, #2

    (1268) 0x438498 CMP	X9, X8

    (1268) 0x43849c LDR	X15, [X1, X15,LSL #3]

    (1268) 0x4384a0 LDR	X15, [X15, X0]

    (1268) 0x4384a4 STR	X10, [X21, X15,LSL #3]

    (1268) 0x4384a8 STP	XZR, XZR, [X16, #1016]

    (1268) 0x4384ac STUR	X15, [X11, #504]

    (1268) 0x4384b0 ADD	X16, X16, #16

    (1268) 0x4384b4 LDR	X15, [X28]

    (1268) 0x4384b8 LDR	X15, [X1, X15,LSL #3]

    (1268) 0x4384bc ADD	X15, X15, X0

    (1268) 0x4384c0 ADD	X0, X10, #1

    (1268) 0x4384c4 ADD	X10, X10, #2

    (1268) 0x4384c8 LDR	X15, [X15, #8]

    (1268) 0x4384cc STR	X0, [X21, X15,LSL #3]

    (1268) 0x4384d0 STR	X15, [X11], #16

    (1268) 0x4384d4 B.NE	43848c

  (1261) 0x4384d8 LDUR	X8, [X29, #416]

  (1261) 0x4384dc LDR	X11, [X17, X13,LSL #3]

  (1261) 0x4384e0 LDR	X10, [X17, X12,LSL #3]

  (1261) 0x4384e4 LDR	X8, [X8, X12,LSL #3]

  (1261) 0x4384e8 ADD	X9, X11, X8

  (1261) 0x4384ec SUB	X9, X9, X10

  (1261) 0x4384f0 CMP	X8, X9

  (1261) 0x4384f4 B.GE	438590

  (1261) 0x4384f8 SUB	W16, W11, W10

  (1261) 0x4384fc ADD	X15, X10, #1

  (1261) 0x438500 TBZ	W16, #0, 43852c

  (1261) 0x438504 LDR	X16, [X28]

  (1261) 0x438508 LDR	X18, [SP, #160]

  (1261) 0x43850c LDR	X16, [X2, X16,LSL #3]

  (1261) 0x438510 STR	XZR, [X18, X10,LSL #3]

  (1261) 0x438514 LDR	X18, [SP, #32]

  (1261) 0x438518 LDR	X16, [X16, X8,LSL #3]

  (1261) 0x43851c ADD	X8, X8, #1

  (1261) 0x438520 STR	X10, [X22, X16,LSL #3]

  (1261) 0x438524 STR	X16, [X18, X10,LSL #3]

  (1261) 0x438528 ORR	X10, XZR, X15

  (1261) 0x43852c CMP	X11, X15

  (1261) 0x438530 B.EQ	438590

  (1261) 0x438534 LDP	X16, X11, [SP]

  (1261) 0x438538 UBFM	X15, X10, #61, #60

  (1261) 0x43853c ADD	X11, X11, X15

  (1261) 0x438540 ADD	X16, X16, X15

    (1267) 0x438544 LDR	X15, [X28]

    (1267) 0x438548 UBFM	X0, X8, #61, #60

    (1267) 0x43854c ADD	X8, X8, #2

    (1267) 0x438550 CMP	X9, X8

    (1267) 0x438554 LDR	X15, [X2, X15,LSL #3]

    (1267) 0x438558 LDR	X15, [X15, X0]

    (1267) 0x43855c STR	X10, [X22, X15,LSL #3]

    (1267) 0x438560 STP	XZR, XZR, [X16, #1016]

    (1267) 0x438564 STUR	X15, [X11, #504]

    (1267) 0x438568 ADD	X16, X16, #16

    (1267) 0x43856c LDR	X15, [X28]

    (1267) 0x438570 LDR	X15, [X2, X15,LSL #3]

    (1267) 0x438574 ADD	X15, X15, X0

    (1267) 0x438578 ADD	X0, X10, #1

    (1267) 0x43857c ADD	X10, X10, #2

    (1267) 0x438580 LDR	X15, [X15, #8]

    (1267) 0x438584 STR	X0, [X22, X15,LSL #3]

    (1267) 0x438588 STR	X15, [X11], #16

    (1267) 0x43858c B.NE	438544

  (1261) 0x438590 LDR	X8, [X3, X12,LSL #3]

  (1261) 0x438594 LDR	X9, [X3, X13,LSL #3]

  (1261) 0x438598 B	4385a4

0x43859c HINT	#0

    (1266) 0x4385a0 ADD	X8, X8, #1

    (1266) 0x4385a4 CMP	X8, X9

    (1266) 0x4385a8 B.GE	4385e0

    (1266) 0x4385ac LDR	X10, [X4, X8,LSL #3]

    (1266) 0x4385b0 LDR	X15, [X28]

    (1266) 0x4385b4 LDR	X11, [X5, X10,LSL #3]

    (1266) 0x4385b8 SUB	X15, X15, #1

    (1266) 0x4385bc CMP	X11, X15

    (1266) 0x4385c0 B.NE	4385a0

    (1266) 0x4385c4 STR	X12, [X19, X10,LSL #3]

    (1266) 0x4385c8 LDR	X9, [X3, X13,LSL #3]

    (1266) 0x4385cc B	4385a0

0x4385d0 HINT	#0

0x4385d4 HINT	#0

0x4385d8 HINT	#0

0x4385dc HINT	#0

  (1261) 0x4385e0 LDR	X8, [X6, X12,LSL #3]

  (1261) 0x4385e4 LDR	X9, [X6, X13,LSL #3]

  (1261) 0x4385e8 B	4385f0

    (1265) 0x4385ec ADD	X8, X8, #1

    (1265) 0x4385f0 CMP	X8, X9

    (1265) 0x4385f4 B.GE	438620

    (1265) 0x4385f8 LDR	X10, [X23, X8,LSL #3]

    (1265) 0x4385fc LDR	X15, [X28]

    (1265) 0x438600 LDR	X11, [X24, X10,LSL #3]

    (1265) 0x438604 SUB	X15, X15, #1

    (1265) 0x438608 CMP	X11, X15

    (1265) 0x43860c B.NE	4385ec

    (1265) 0x438610 STR	X12, [X20, X10,LSL #3]

    (1265) 0x438614 LDR	X9, [X6, X13,LSL #3]

    (1265) 0x438618 B	4385ec

0x43861c HINT	#0

  (1261) 0x438620 LDUR	X8, [X29, #408]

  (1261) 0x438624 MOVI	D2, #0

  (1261) 0x438628 LDR	X10, [X8, X12,LSL #3]

  (1261) 0x43862c LDR	X7, [X8, X13,LSL #3]

  (1261) 0x438630 ADD	X9, X10, #1

  (1261) 0x438634 STUR	X10, [X29, #456]

  (1261) 0x438638 CMP	X9, X7

  (1261) 0x43863c B.GE	4388a4

  (1261) 0x438640 LDP	X10, X11, [X29, #952]

  (1261) 0x438644 LDR	X8, [SP, #56]

  (1261) 0x438648 MOVI	D1, #0

  (1261) 0x43864c MOVI	D2, #0

  (1261) 0x438650 LDR	X6, [X11]

  (1261) 0x438654 LDR	X11, [SP, #152]

  (1261) 0x438658 LDR	X8, [X8]

  (1261) 0x43865c LDR	X10, [X10]

  (1261) 0x438660 LDR	X26, [X11]

  (1261) 0x438664 LDR	X11, [SP, #136]

  (1261) 0x438668 LDR	X2, [X11]

  (1261) 0x43866c LDUR	X11, [X29, #488]

  (1261) 0x438670 LDR	X27, [X11]

  (1261) 0x438674 LDR	X11, [SP, #144]

  (1261) 0x438678 LDR	X4, [X11]

  (1261) 0x43867c LDUR	X11, [X29, #496]

  (1261) 0x438680 ADD	X5, X27, #8

  (1261) 0x438684 LDR	X24, [X11]

  (1261) 0x438688 ADD	X11, X2, #8

  (1261) 0x43868c STUR	X11, [X29, #480]

  (1261) 0x438690 ADD	X11, X24, #8

  (1261) 0x438694 STUR	X11, [X29, #472]

  (1261) 0x438698 ADD	X11, X4, #8

  (1261) 0x43869c STUR	X11, [X29, #464]

  (1261) 0x4386a0 LDR	X18, [SP, #48]

  (1261) 0x4386a4 B	4386cc

    (1262) 0x4386a8 LDR	D3, [X26, X9,LSL #3]

    (1262) 0x4386ac FADD	D1, D1, D3

    (1262) 0x4386b0 HINT	#0

    (1262) 0x4386b4 HINT	#0

    (1262) 0x4386b8 HINT	#0

    (1262) 0x4386bc HINT	#0

    (1262) 0x4386c0 ADD	X9, X9, #1

    (1262) 0x4386c4 CMP	X9, X7

    (1262) 0x4386c8 B.EQ	4388c0

    (1262) 0x4386cc LDR	X23, [X18, X9,LSL #3]

    (1262) 0x4386d0 LDR	X11, [X19, X23,LSL #3]

    (1262) 0x4386d4 CMP	X11, X12

    (1262) 0x4386d8 B.NE	438708

    (1262) 0x4386dc ADD	X11, X23, #1

    (1262) 0x4386e0 LDR	X16, [X14, X23,LSL #3]

    (1262) 0x4386e4 LDR	X0, [X14, X11,LSL #3]

    (1262) 0x4386e8 CMP	X0, X16

    (1262) 0x4386ec B.LE	4387d8

    (1262) 0x4386f0 SUB	W15, W0, W16

    (1262) 0x4386f4 ADD	X1, X16, #1

    (1262) 0x4386f8 TBNZ	W15, #0, 438730

    (1262) 0x4386fc CMP	X0, X1

    (1262) 0x438700 B.NE	438764

    (1262) 0x438704 B	4387d8

    (1262) 0x438708 LDR	X11, [X8, X23,LSL #3]

    (1262) 0x43870c CMN	X11, #3

    (1262) 0x438710 B.EQ	4386c0

    (1262) 0x438714 CMP	X10, #1

    (1262) 0x438718 B.EQ	4386a8

    (1262) 0x43871c LDR	X11, [X6, X12,LSL #3]

    (1262) 0x438720 LDR	X15, [X6, X23,LSL #3]

    (1262) 0x438724 CMP	X11, X15

    (1262) 0x438728 B.EQ	4386a8

    (1262) 0x43872c B	4386c0

    (1262) 0x438730 LDR	X15, [X2, X16,LSL #3]

    (1262) 0x438734 LDR	D0, [X26, X9,LSL #3]

    (1262) 0x438738 LDR	D3, [X27, X16,LSL #3]

    (1262) 0x43873c ORR	X16, XZR, X1

    (1262) 0x438740 FMUL	D0, D0, D3

    (1262) 0x438744 LDR	X15, [X21, X15,LSL #3]

    (1262) 0x438748 LDR	D3, [X27, X15,LSL #3]

    (1262) 0x43874c FADD	D2, D2, D0

    (1262) 0x438750 FADD	D1, D1, D0

    (1262) 0x438754 FADD	D3, D0, D3

    (1262) 0x438758 STR	D3, [X27, X15,LSL #3]

    (1262) 0x43875c CMP	X0, X1

    (1262) 0x438760 B.EQ	4387d8

    (1262) 0x438764 LDUR	X3, [X29, #480]

    (1262) 0x438768 UBFM	X15, X16, #61, #60

    (1262) 0x43876c SUB	X0, X0, X16

    (1262) 0x438770 ADD	X1, X5, X15

    (1262) 0x438774 ADD	X3, X3, X15

    (1262) 0x438778 HINT	#0

    (1262) 0x43877c HINT	#0

      (1264) 0x438780 LDUR	X15, [X3, #504]

      (1264) 0x438784 LDR	D0, [X26, X9,LSL #3]

      (1264) 0x438788 LDUR	D3, [X1, #504]

      (1264) 0x43878c SUBS	X0, X0, #2

      (1264) 0x438790 FMUL	D0, D0, D3

      (1264) 0x438794 LDR	X15, [X21, X15,LSL #3]

      (1264) 0x438798 LDR	D3, [X27, X15,LSL #3]

      (1264) 0x43879c FADD	D2, D2, D0

      (1264) 0x4387a0 FADD	D1, D1, D0

      (1264) 0x4387a4 FADD	D3, D0, D3

      (1264) 0x4387a8 STR	D3, [X27, X15,LSL #3]

      (1264) 0x4387ac LDR	X15, [X3], #16

      (1264) 0x4387b0 LDR	D0, [X26, X9,LSL #3]

      (1264) 0x4387b4 LDR	D3, [X1], #16

      (1264) 0x4387b8 FMUL	D0, D0, D3

      (1264) 0x4387bc LDR	X15, [X21, X15,LSL #3]

      (1264) 0x4387c0 LDR	D3, [X27, X15,LSL #3]

      (1264) 0x4387c4 FADD	D2, D2, D0

      (1264) 0x4387c8 FADD	D1, D1, D0

      (1264) 0x4387cc FADD	D3, D0, D3

      (1264) 0x4387d0 STR	D3, [X27, X15,LSL #3]

      (1264) 0x4387d4 B.NE	438780

    (1262) 0x4387d8 LDR	X16, [X17, X23,LSL #3]

    (1262) 0x4387dc LDR	X11, [X17, X11,LSL #3]

    (1262) 0x4387e0 CMP	X11, X16

    (1262) 0x4387e4 B.LE	4386c0

    (1262) 0x4387e8 SUB	W15, W11, W16

    (1262) 0x4387ec ADD	X0, X16, #1

    (1262) 0x4387f0 TBNZ	W15, #0, 438800

    (1262) 0x4387f4 CMP	X11, X0

    (1262) 0x4387f8 B.EQ	4386c0

    (1262) 0x4387fc B	438834

    (1262) 0x438800 LDR	X15, [X4, X16,LSL #3]

    (1262) 0x438804 LDR	D0, [X26, X9,LSL #3]

    (1262) 0x438808 LDR	D3, [X24, X16,LSL #3]

    (1262) 0x43880c ORR	X16, XZR, X0

    (1262) 0x438810 FMUL	D0, D0, D3

    (1262) 0x438814 LDR	X15, [X22, X15,LSL #3]

    (1262) 0x438818 LDR	D3, [X24, X15,LSL #3]

    (1262) 0x43881c FADD	D2, D2, D0

    (1262) 0x438820 FADD	D1, D1, D0

    (1262) 0x438824 FADD	D3, D0, D3

    (1262) 0x438828 STR	D3, [X24, X15,LSL #3]

    (1262) 0x43882c CMP	X11, X0

    (1262) 0x438830 B.EQ	4386c0

    (1262) 0x438834 LDP	X1, X0, [X29, #976]

    (1262) 0x438838 UBFM	X15, X16, #61, #60

    (1262) 0x43883c SUB	X11, X11, X16

    (1262) 0x438840 ADD	X0, X0, X15

    (1262) 0x438844 ADD	X1, X1, X15

      (1263) 0x438848 LDUR	X15, [X1, #504]

      (1263) 0x43884c LDR	D0, [X26, X9,LSL #3]

      (1263) 0x438850 LDUR	D3, [X0, #504]

      (1263) 0x438854 SUBS	X11, X11, #2

      (1263) 0x438858 FMUL	D0, D0, D3

      (1263) 0x43885c LDR	X15, [X22, X15,LSL #3]

      (1263) 0x438860 LDR	D3, [X24, X15,LSL #3]

      (1263) 0x438864 FADD	D2, D2, D0

      (1263) 0x438868 FADD	D1, D1, D0

      (1263) 0x43886c FADD	D3, D0, D3

      (1263) 0x438870 STR	D3, [X24, X15,LSL #3]

      (1263) 0x438874 LDR	X15, [X1], #16

      (1263) 0x438878 LDR	D0, [X26, X9,LSL #3]

      (1263) 0x43887c LDR	D3, [X0], #16

      (1263) 0x438880 FMUL	D0, D0, D3

      (1263) 0x438884 LDR	X15, [X22, X15,LSL #3]

      (1263) 0x438888 LDR	D3, [X24, X15,LSL #3]

      (1263) 0x43888c FADD	D2, D2, D0

      (1263) 0x438890 FADD	D1, D1, D0

      (1263) 0x438894 FADD	D3, D0, D3

      (1263) 0x438898 STR	D3, [X24, X15,LSL #3]

      (1263) 0x43889c B.NE	438848

    (1262) 0x4388a0 B	4386c0

  (1261) 0x4388a4 MOVI	D1, #0

  (1261) 0x4388a8 LDUR	X9, [X29, #392]

  (1261) 0x4388ac LDR	X8, [X9, X12,LSL #3]

  (1261) 0x4388b0 LDR	X9, [X9, X13,LSL #3]

  (1261) 0x4388b4 CMP	X8, X9

  (1261) 0x4388b8 B.LT	4388ec

  (1261) 0x4388bc B	438a78

  (1261) 0x4388c0 LDP	X2, X1, [X29, #880]

  (1261) 0x4388c4 LDP	X4, X3, [X29, #864]

  (1261) 0x4388c8 LDP	X6, X5, [X29, #848]

  (1261) 0x4388cc CNTW	X26, ALL

  (1261) 0x4388d0 LDP	X24, X23, [SP, #176]

  (1261) 0x4388d4 LDUR	X10, [X29, #456]

  (1261) 0x4388d8 LDUR	X9, [X29, #392]

  (1261) 0x4388dc LDR	X8, [X9, X12,LSL #3]

  (1261) 0x4388e0 LDR	X9, [X9, X13,LSL #3]

  (1261) 0x4388e4 CMP	X8, X9

  (1261) 0x4388e8 B.GE	438a78

(1258) 0x4388ec STUR	X25, [X29, #464]

(1258) 0x4388f0 LDR	X0, [X28]

(1258) 0x4388f4 LDP	X10, X11, [SP, #64]

(1258) 0x4388f8 LDR	X16, [X11]

(1258) 0x4388fc LDR	X11, [SP, #120]

(1258) 0x438900 LDR	X10, [X10]

(1258) 0x438904 LDR	X6, [X11]

(1258) 0x438908 LDUR	X11, [X29, #440]

(1258) 0x43890c LDR	X7, [X11]

(1258) 0x438910 LDR	X11, [SP, #128]

(1258) 0x438914 LDR	X11, [X11]

(1258) 0x438918 STUR	X11, [X29, #480]

(1258) 0x43891c LDUR	X11, [X29, #448]

(1258) 0x438920 LDR	X11, [X11]

(1258) 0x438924 STUR	X11, [X29, #472]

(1258) 0x438928 LDP	X11, X18, [SP, #104]

(1258) 0x43892c LDR	X26, [X11]

(1258) 0x438930 LDR	X11, [SP, #80]

(1258) 0x438934 LDR	X3, [X18]

(1258) 0x438938 LDR	X27, [X11]

(1258) 0x43893c LDR	X11, [SP, #88]

(1258) 0x438940 LDR	X15, [X11]

(1258) 0x438944 LDR	X11, [SP, #96]

(1258) 0x438948 LDR	X11, [X11]

(1258) 0x43894c ADD	X1, X15, #8

(1258) 0x438950 B	438974

0x438954 HINT	#0

0x438958 HINT	#0

0x43895c HINT	#0

  (1259) 0x438960 LDR	D3, [X26, X8,LSL #3]

  (1259) 0x438964 FADD	D1, D1, D3

  (1259) 0x438968 ADD	X8, X8, #1

  (1259) 0x43896c CMP	X8, X9

  (1259) 0x438970 B.EQ	438a60

  (1259) 0x438974 ADD	X15, X16, X8,LSL #3

  (1259) 0x438978 CBZ	X30, 438984

  (1259) 0x43897c LDR	X15, [X15]

  (1259) 0x438980 ADD	X15, X10, X15,LSL #3

  (1259) 0x438984 LDR	X15, [X15]

  (1259) 0x438988 TBNZ	X15, #63, 438a20

  (1259) 0x43898c LDR	X2, [X20, X15,LSL #3]

  (1259) 0x438990 CMP	X2, X12

  (1259) 0x438994 B.NE	438a20

  (1259) 0x438998 LDR	X4, [X1, X15,LSL #3]

  (1259) 0x43899c CMP	X4, #1

  (1259) 0x4389a0 B.LT	438968

  (1259) 0x4389a4 LDR	X2, [X27, X15,LSL #3]

  (1259) 0x4389a8 LDUR	X15, [X29, #496]

  (1259) 0x4389ac LDR	X5, [X11, X0,LSL #3]

  (1259) 0x4389b0 ORR	X24, XZR, X30

  (1259) 0x4389b4 ORR	X23, XZR, X20

  (1259) 0x4389b8 ADD	X4, X4, X2

  (1259) 0x4389bc LDR	X25, [X15]

  (1259) 0x4389c0 LDUR	X15, [X29, #488]

  (1259) 0x4389c4 LDR	X15, [X15]

    (1260) 0x4389c8 LDR	X18, [X5, X2,LSL #3]

    (1260) 0x4389cc LDR	D0, [X26, X8,LSL #3]

    (1260) 0x4389d0 LDR	D3, [X3, X2,LSL #3]

    (1260) 0x4389d4 ADD	X2, X2, #1

    (1260) 0x4389d8 ORN	X20, XZR, X18

    (1260) 0x4389dc ADD	X30, X22, X18,LSL #3

    (1260) 0x4389e0 CMP	X18, #0

    (1260) 0x4389e4 ADD	X20, X21, X20,LSL #3

    (1260) 0x4389e8 FMUL	D0, D0, D3

    (1260) 0x4389ec CSEL	X18, X20, X30, #11

    (1260) 0x4389f0 CSEL	X20, X15, X25, #11

    (1260) 0x4389f4 CMP	X2, X4

    (1260) 0x4389f8 LDR	X18, [X18]

    (1260) 0x4389fc FADD	D2, D2, D0

    (1260) 0x438a00 FADD	D1, D1, D0

    (1260) 0x438a04 LDR	D3, [X20, X18,LSL #3]

    (1260) 0x438a08 FADD	D3, D0, D3

    (1260) 0x438a0c STR	D3, [X20, X18,LSL #3]

    (1260) 0x438a10 B.LT	4389c8

  (1259) 0x438a14 ORR	X20, XZR, X23

  (1259) 0x438a18 ORR	X30, XZR, X24

  (1259) 0x438a1c B	438968

  (1259) 0x438a20 LDR	X18, [X6, X15,LSL #3]

  (1259) 0x438a24 CMN	X18, #3

  (1259) 0x438a28 B.EQ	438968

  (1259) 0x438a2c CMP	X7, #1

  (1259) 0x438a30 B.EQ	438960

  (1259) 0x438a34 LDUR	X18, [X29, #480]

  (1259) 0x438a38 LDR	X15, [X18, X15,LSL #3]

  (1259) 0x438a3c LDUR	X18, [X29, #472]

  (1259) 0x438a40 LDR	X18, [X18, X12,LSL #3]

  (1259) 0x438a44 CMP	X15, X18

  (1259) 0x438a48 B.EQ	438960

  (1259) 0x438a4c B	438968

0x438a50 HINT	#0

0x438a54 HINT	#0

0x438a58 HINT	#0

0x438a5c HINT	#0

(1258) 0x438a60 LDP	X2, X1, [X29, #880]

(1258) 0x438a64 LDP	X4, X3, [X29, #864]

(1258) 0x438a68 LDP	X6, X5, [X29, #848]

(1258) 0x438a6c CNTW	X26, ALL

(1258) 0x438a70 LDP	X24, X23, [SP, #176]

(1258) 0x438a74 LDP	X10, X25, [X29, #968]

  (1261) 0x438a78 LDUR	X8, [X29, #384]

  (1261) 0x438a7c LDR	D3, [X8, X10,LSL #3]

  (1261) 0x438a80 FMUL	D2, D2, D3

  (1261) 0x438a84 FCMP	D2, #0

  (1261) 0x438a88 B.EQ	438a94

  (1261) 0x438a8c FNEG	D0, D1

  (1261) 0x438a90 FDIV	D0, D0, D2

  (1261) 0x438a94 LDR	X16, [X14, X12,LSL #3]

  (1261) 0x438a98 LDR	X8, [X14, X13,LSL #3]

  (1261) 0x438a9c SUBS	X11, X8, X16

  (1261) 0x438aa0 B.LE	438b34

  (1261) 0x438aa4 ORR	X9, XZR, X16

  (1261) 0x438aa8 CMP	X11, X26

  (1261) 0x438aac B.CC	438b08

  (1261) 0x438ab0 UDIV	X9, X11, X26

  (1261) 0x438ab4 LDR	X0, [SP, #168]

  (1261) 0x438ab8 UBFM	X18, X16, #61, #60

  (1261) 0x438abc ORR	X10, XZR, XZR

  (1261) 0x438ac0 DUP	Z1.D, Z0.D[0]

  (1261) 0x438ac4 MADD	X15, X9, X26, XZR

  (1261) 0x438ac8 ADD	X9, X16, X15

  (1261) 0x438acc ADD	X16, X0, X18

  (1261) 0x438ad0 ADDVL	X18, X18, #1

  (1261) 0x438ad4 SUB	X11, X11, X15

  (1261) 0x438ad8 ADD	X0, X0, X18

  (1261) 0x438adc HINT	#0

    (1272) 0x438ae0 LD1D	{Z2.D}, P0/Z, [X16, X10,LSL #3]

    (1272) 0x438ae4 LD1D	{Z3.D}, P0/Z, [X0, X10,LSL #3]

    (1272) 0x438ae8 FMUL	Z2.D, Z1.D, Z2.D

    (1272) 0x438aec FMUL	Z3.D, Z1.D, Z3.D

    (1272) 0x438af0 ST1D	{Z2.D}, P0, [X16, X10,LSL #3]

    (1272) 0x438af4 ST1D	{Z3.D}, P0, [X0, X10,LSL #3]

    (1272) 0x438af8 ADD	X10, X10, X26

    (1272) 0x438afc CMP	X15, X10

    (1272) 0x438b00 B.NE	438ae0

  (1261) 0x438b04 CBZ	X11, 438b34

  (1261) 0x438b08 LDR	X10, [SP, #168]

  (1261) 0x438b0c SUB	X8, X8, X9

  (1261) 0x438b10 ADD	X9, X10, X9,LSL #3

  (1261) 0x438b14 HINT	#0

  (1261) 0x438b18 HINT	#0

  (1261) 0x438b1c HINT	#0

    (1271) 0x438b20 LDR	D1, [X9]

    (1271) 0x438b24 SUBS	X8, X8, #1

    (1271) 0x438b28 FMUL	D1, D0, D1

    (1271) 0x438b2c STR	D1, [X9], #8

    (1271) 0x438b30 B.NE	438b20

  (1261) 0x438b34 LDR	X15, [X17, X12,LSL #3]

  (1261) 0x438b38 LDR	X8, [X17, X13,LSL #3]

  (1261) 0x438b3c SUBS	X11, X8, X15

  (1261) 0x438b40 B.LE	438404

  (1261) 0x438b44 ORR	X9, XZR, X15

  (1261) 0x438b48 CMP	X11, X26

  (1261) 0x438b4c B.CC	438ba8

  (1261) 0x438b50 UDIV	X9, X11, X26

  (1261) 0x438b54 LDR	X16, [SP, #160]

  (1261) 0x438b58 ORR	X10, XZR, XZR

  (1261) 0x438b5c DUP	Z1.D, Z0.D[0]

  (1261) 0x438b60 MADD	X12, X9, X26, XZR

  (1261) 0x438b64 ADD	X9, X15, X12

  (1261) 0x438b68 UBFM	X15, X15, #61, #60

  (1261) 0x438b6c SUB	X11, X11, X12

  (1261) 0x438b70 ADD	X13, X16, X15

  (1261) 0x438b74 ADDVL	X15, X15, #1

  (1261) 0x438b78 ADD	X15, X16, X15

  (1261) 0x438b7c HINT	#0

    (1270) 0x438b80 LD1D	{Z2.D}, P0/Z, [X13, X10,LSL #3]

    (1270) 0x438b84 LD1D	{Z3.D}, P0/Z, [X15, X10,LSL #3]

    (1270) 0x438b88 FMUL	Z2.D, Z1.D, Z2.D

    (1270) 0x438b8c FMUL	Z3.D, Z1.D, Z3.D

    (1270) 0x438b90 ST1D	{Z2.D}, P0, [X13, X10,LSL #3]

    (1270) 0x438b94 ST1D	{Z3.D}, P0, [X15, X10,LSL #3]

    (1270) 0x438b98 ADD	X10, X10, X26

    (1270) 0x438b9c CMP	X12, X10

    (1270) 0x438ba0 B.NE	438b80

  (1261) 0x438ba4 CBZ	X11, 438404

  (1261) 0x438ba8 LDR	X10, [SP, #160]

  (1261) 0x438bac SUB	X8, X8, X9

  (1261) 0x438bb0 ADD	X9, X10, X9,LSL #3

  (1261) 0x438bb4 HINT	#0

  (1261) 0x438bb8 HINT	#0

  (1261) 0x438bbc HINT	#0

    (1269) 0x438bc0 LDR	D1, [X9]

    (1269) 0x438bc4 SUBS	X8, X8, #1

    (1269) 0x438bc8 FMUL	D1, D0, D1

    (1269) 0x438bcc STR	D1, [X9], #8

    (1269) 0x438bd0 B.NE	438bc0

  (1261) 0x438bd4 B	438404

0x438bd8 ORR	X0, XZR, X19

0x438bdc BL	4ae530

0x438be0 ORR	X0, XZR, X20

0x438be4 BL	4ae530

0x438be8 ORR	X0, XZR, X21

0x438bec BL	4ae530

0x438bf0 ORR	X0, XZR, X22

0x438bf4 LDP	X20, X19, [SP, #448]

0x438bf8 LDP	X22, X21, [SP, #432]

0x438bfc LDP	X24, X23, [SP, #416]

0x438c00 LDP	X26, X25, [SP, #400]

0x438c04 LDP	X28, X27, [SP, #384]

0x438c08 LDP	X29, X30, [SP, #368]

0x438c0c ADD	SP, SP, #464

0x438c10 B	4ae530

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 45.00 to 2.50 cycles (18.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 45.00 to 4.50 cycles (10.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 560 bytes.

General properties

nb instructions	219
loop length	876
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	45.00	45.00	45.00	23.00	23.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	45.00	45.00	45.00	23.00	23.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	45.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.00 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4380e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 438224 <.omp_outlined..22+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 438230 <.omp_outlined..22+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43823c <.omp_outlined..22+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 438240 <.omp_outlined..22+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 438200 <.omp_outlined..22+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 438214 <.omp_outlined..22+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 438294 <.omp_outlined..22+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4382bc <.omp_outlined..22+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438bd8 <.omp_outlined..22+0xaf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X10, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X1, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X4, X3, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X5, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 438414 <.omp_outlined..22+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 45.00 to 4.50 cycles (10.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 560 bytes.

General properties

nb instructions	219
loop length	876
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	45.00	45.00	45.00	23.00	23.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	45.00	45.00	45.00	23.00	23.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	45.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.00 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4380e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 438224 <.omp_outlined..22+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 438230 <.omp_outlined..22+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43823c <.omp_outlined..22+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 438240 <.omp_outlined..22+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 438200 <.omp_outlined..22+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 438214 <.omp_outlined..22+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 438294 <.omp_outlined..22+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4382bc <.omp_outlined..22+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 438bd8 <.omp_outlined..22+0xaf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X10, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X1, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X4, X3, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X5, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 438414 <.omp_outlined..22+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..22#0x4380e0–	4.84	1.83
○Loop 1274 - par_multi_interp.c:1760-1761 - exec	3.6	1.17
○Loop 1273 - par_multi_interp.c:1762-1763 - exec	0	0
▼Loop 1258 - par_multi_interp.c:1774-1876 - exec–	0	0
▼Loop 1261 - par_multi_interp.c:1774-1876 - exec–	0.16	0.05
▼Loop 1262 - par_multi_interp.c:1811-1837 - exec–	0.69	0.23
○Loop 1264 - par_multi_interp.c:1816-1822 - exec	0.03	0.01
○Loop 1263 - par_multi_interp.c:1824-1830 - exec	0	0
○Loop 1266 - par_multi_interp.c:1799-1803 - exec	0.34	0.11
○Loop 1268 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 1271 - par_multi_interp.c:1873-1874 - exec	0	0.01
○Loop 1270 - par_multi_interp.c:1876-1876 - exec	0	0
○Loop 1269 - par_multi_interp.c:1875-1876 - exec	0	0
○Loop 1272 - par_multi_interp.c:1874-1874 - exec	0	0
○Loop 1267 - par_multi_interp.c:1792-1797 - exec	0	0
○Loop 1265 - par_multi_interp.c:1805-1809 - exec	0	0
▼Loop 1259 - par_multi_interp.c:1840-1867 - exec–	0	0
○Loop 1260 - par_multi_interp.c:1851-1860 - exec	0	0

Report Configuration

Code clean check

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code