OV - exec - Function .omp_outlined..20#0x46a650

	Function: .omp_outlined..20#0x46a650	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage: 1.84%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x46a650 SUB	SP, SP, #384

0x46a654 STP	X29, X30, [SP, #288]

0x46a658 STP	X28, X27, [SP, #304]

0x46a65c STP	X26, X25, [SP, #320]

0x46a660 STP	X24, X23, [SP, #336]

0x46a664 STP	X22, X21, [SP, #352]

0x46a668 STP	X20, X19, [SP, #368]

0x46a66c ADD	X29, SP, #288

0x46a670 LDP	X8, X9, [X29, #112]

0x46a674 ORR	X22, XZR, X7

0x46a678 ORR	X24, XZR, X6

0x46a67c STR	X0, [SP, #16]

0x46a680 STP	X8, X9, [X29, #968]

0x46a684 ORR	X28, XZR, X5

0x46a688 ORR	X25, XZR, X4

0x46a68c ORR	X19, XZR, X3

0x46a690 ORR	X26, XZR, X2

0x46a694 BL	4b05e0

0x46a698 LDR	X2, [X26]

0x46a69c ORR	X27, XZR, X0

0x46a6a0 SUB	X0, X29, #16

0x46a6a4 SUB	X1, X29, #24

0x46a6a8 BL	4b0600

0x46a6ac LDR	X8, [X19]

0x46a6b0 CMP	X8, #1

0x46a6b4 B.LE	46a6f8

0x46a6b8 LDR	X10, [X28]

0x46a6bc LDR	X9, [X25]

0x46a6c0 LDP	X13, X8, [X29, #96]

0x46a6c4 MADD	X11, X10, X27, XZR

0x46a6c8 LDR	X15, [X24]

0x46a6cc LDR	X13, [X13]

0x46a6d0 LDR	X8, [X8]

0x46a6d4 UBFM	X14, X11, #61, #60

0x46a6d8 ADD	X26, X9, X14

0x46a6dc LDR	X9, [X22]

0x46a6e0 ADD	X20, X13, X14

0x46a6e4 MADD	X12, X9, X27, XZR

0x46a6e8 UBFM	X16, X12, #61, #60

0x46a6ec ADD	X23, X15, X16

0x46a6f0 ADD	X21, X8, X16

0x46a6f4 B	46a718

0x46a6f8 LDR	X10, [X28]

0x46a6fc LDR	X9, [X22]

0x46a700 ORR	X21, XZR, XZR

0x46a704 ORR	X20, XZR, XZR

0x46a708 ORR	X23, XZR, XZR

0x46a70c ORR	X26, XZR, XZR

0x46a710 MADD	X11, X10, X27, XZR

0x46a714 MADD	X12, X9, X27, XZR

0x46a718 LDUR	X13, [X29, #456]

0x46a71c CMP	X10, #0

0x46a720 LDR	X8, [X29, #128]

0x46a724 LDR	X13, [X13]

0x46a728 ADD	X11, X13, X11,LSL #3

0x46a72c CSEL	X24, XZR, X11, #0

0x46a730 LDUR	X11, [X29, #464]

0x46a734 CMP	X9, #0

0x46a738 LDR	X11, [X11]

0x46a73c ADD	X11, X11, X12,LSL #3

0x46a740 CSEL	X25, XZR, X11, #0

0x46a744 CMP	X10, #1

0x46a748 B.LT	46a778

0x46a74c ORR	X9, XZR, XZR

0x46a750 MOVN	X10, #0

0x46a754 HINT	#0

0x46a758 HINT	#0

0x46a75c HINT	#0

(1187) 0x46a760 STR	X10, [X24, X9,LSL #3]

(1187) 0x46a764 ADD	X9, X9, #1

(1187) 0x46a768 LDR	X11, [X28]

(1187) 0x46a76c CMP	X9, X11

(1187) 0x46a770 B.LT	46a760

0x46a774 LDR	X9, [X22]

0x46a778 LDR	X10, [X29, #256]

0x46a77c LDR	X11, [X29, #208]

0x46a780 CMP	X9, #1

0x46a784 LDR	X9, [X29, #144]

0x46a788 STUR	X19, [X29, #424]

0x46a78c STR	X10, [SP, #80]

0x46a790 LDR	X10, [X29, #248]

0x46a794 STR	X9, [SP, #112]

0x46a798 LDR	X9, [X29, #136]

0x46a79c STUR	X10, [X29, #392]

0x46a7a0 LDR	X10, [X29, #240]

0x46a7a4 STR	X9, [SP, #96]

0x46a7a8 STR	X10, [SP, #56]

0x46a7ac LDR	X10, [X29, #232]

0x46a7b0 STUR	X10, [X29, #384]

0x46a7b4 LDR	X10, [X29, #224]

0x46a7b8 STR	X10, [SP, #48]

0x46a7bc LDR	X10, [X29, #216]

0x46a7c0 STUR	X10, [X29, #464]

0x46a7c4 LDR	X10, [X29, #200]

0x46a7c8 STP	X10, X11, [X29, #912]

0x46a7cc LDR	X10, [X29, #192]

0x46a7d0 STR	X10, [SP, #40]

0x46a7d4 LDR	X10, [X29, #184]

0x46a7d8 STUR	X10, [X29, #456]

0x46a7dc LDR	X10, [X29, #176]

0x46a7e0 STR	X10, [SP, #104]

0x46a7e4 LDR	X10, [X29, #168]

0x46a7e8 STR	X10, [SP, #32]

0x46a7ec LDR	X10, [X29, #160]

0x46a7f0 STR	X10, [SP, #24]

0x46a7f4 LDR	X10, [X29, #152]

0x46a7f8 STR	X10, [SP, #120]

0x46a7fc B.LT	46a81c

0x46a800 ORR	X9, XZR, XZR

0x46a804 MOVN	X10, #0

(1186) 0x46a808 STR	X10, [X25, X9,LSL #3]

(1186) 0x46a80c ADD	X9, X9, #1

(1186) 0x46a810 LDR	X11, [X22]

(1186) 0x46a814 CMP	X9, X11

(1186) 0x46a818 B.LT	46a808

0x46a81c LDR	X8, [X8]

0x46a820 STP	XZR, XZR, [X29, #984]

0x46a824 ADD	X9, X27, #1

0x46a828 STUR	X22, [X29, #432]

0x46a82c LDR	X22, [X8, X27,LSL #3]

0x46a830 LDR	X30, [X8, X9,LSL #3]

0x46a834 LDUR	X8, [X29, #424]

0x46a838 STR	X28, [SP, #88]

0x46a83c STR	X9, [SP, #8]

0x46a840 LDR	X8, [X8]

0x46a844 STUR	X30, [X29, #416]

0x46a848 CMP	X8, #1

0x46a84c B.NE	46ab84

0x46a850 CMP	X22, X30

0x46a854 B.GE	46b130

0x46a858 LDR	X8, [SP, #96]

0x46a85c ORR	X18, XZR, X22

0x46a860 LDR	X8, [X8]

0x46a864 STUR	X8, [X29, #448]

0x46a868 LDR	X8, [SP, #112]

0x46a86c LDR	X8, [X8]

0x46a870 STUR	X8, [X29, #440]

0x46a874 LDR	X8, [SP, #120]

0x46a878 LDR	X8, [X8]

0x46a87c STR	X8, [SP, #144]

0x46a880 LDR	X8, [SP, #24]

0x46a884 LDR	X11, [X8]

0x46a888 LDR	X8, [SP, #32]

0x46a88c LDR	X12, [X8]

0x46a890 LDR	X8, [SP, #104]

0x46a894 LDR	X13, [X8]

0x46a898 LDR	X8, [SP, #40]

0x46a89c LDR	X14, [X8]

0x46a8a0 LDUR	X8, [X29, #400]

0x46a8a4 LDR	X15, [X8]

0x46a8a8 LDUR	X8, [X29, #408]

0x46a8ac LDR	X16, [X8]

0x46a8b0 LDR	X8, [SP, #48]

0x46a8b4 LDR	X17, [X8]

0x46a8b8 LDR	X8, [SP, #56]

0x46a8bc LDR	X0, [X8]

0x46a8c0 B	46a8d0

    (1179) 0x46a8c4 ADD	X18, X18, #1

    (1179) 0x46a8c8 CMP	X18, X30

    (1179) 0x46a8cc B.EQ	46b130

    (1179) 0x46a8d0 LDUR	X8, [X29, #448]

    (1179) 0x46a8d4 LDP	X2, X1, [X29, #984]

    (1179) 0x46a8d8 LDR	X10, [X8, X18,LSL #3]

    (1179) 0x46a8dc LDUR	X8, [X29, #440]

    (1179) 0x46a8e0 STR	X1, [X8, X18,LSL #3]

    (1179) 0x46a8e4 LDUR	X8, [X29, #432]

    (1179) 0x46a8e8 LDR	X8, [X8]

    (1179) 0x46a8ec CBZ	X8, 46a8fc

    (1179) 0x46a8f0 LDUR	X8, [X29, #472]

    (1179) 0x46a8f4 LDR	X9, [SP, #144]

    (1179) 0x46a8f8 STR	X8, [X9, X18,LSL #3]

    (1179) 0x46a8fc ADD	X3, X10, #1

    (1179) 0x46a900 LDR	X5, [X11, X10,LSL #3]

    (1179) 0x46a904 LDR	X8, [X11, X3,LSL #3]

    (1179) 0x46a908 CMP	X5, X8

    (1179) 0x46a90c B.GE	46aa70

    (1179) 0x46a910 LDUR	X8, [X29, #456]

    (1179) 0x46a914 STUR	X10, [X29, #376]

    (1179) 0x46a918 LDR	X6, [X8]

    (1179) 0x46a91c LDUR	X8, [X29, #400]

    (1179) 0x46a920 LDR	X7, [X8]

    (1179) 0x46a924 LDUR	X8, [X29, #408]

    (1179) 0x46a928 LDR	X30, [X8]

    (1179) 0x46a92c B	46a950

0x46a930 HINT	#0

0x46a934 HINT	#0

0x46a938 HINT	#0

0x46a93c HINT	#0

      (1181) 0x46a940 LDR	X8, [X11, X3,LSL #3]

      (1181) 0x46a944 ADD	X5, X5, #1

      (1181) 0x46a948 CMP	X5, X8

      (1181) 0x46a94c B.GE	46aa68

      (1181) 0x46a950 LDR	X27, [X12, X5,LSL #3]

      (1181) 0x46a954 LDR	X8, [X13, X27,LSL #3]

      (1181) 0x46a958 CMP	X8, #1

      (1181) 0x46a95c B.LT	46a984

      (1181) 0x46a960 LDR	X8, [X6, X27,LSL #3]

      (1181) 0x46a964 LDR	X9, [X24, X8,LSL #3]

      (1181) 0x46a968 CMP	X9, X1

      (1181) 0x46a96c B.GE	46a984

      (1181) 0x46a970 LDUR	X9, [X29, #480]

      (1181) 0x46a974 STR	X9, [X24, X8,LSL #3]

      (1181) 0x46a978 LDUR	X8, [X29, #480]

      (1181) 0x46a97c ADD	X8, X8, #1

      (1181) 0x46a980 STUR	X8, [X29, #480]

      (1181) 0x46a984 ADD	X28, X27, #1

      (1181) 0x46a988 LDR	X10, [X11, X27,LSL #3]

      (1181) 0x46a98c LDR	X8, [X11, X28,LSL #3]

      (1181) 0x46a990 CMP	X10, X8

      (1181) 0x46a994 B.GE	46aa00

      (1181) 0x46a998 LDUR	X9, [X29, #456]

      (1181) 0x46a99c LDR	X9, [X9]

      (1181) 0x46a9a0 B	46a9b0

        (1183) 0x46a9a4 ADD	X10, X10, #1

        (1183) 0x46a9a8 CMP	X10, X8

        (1183) 0x46a9ac B.GE	46aa00

        (1183) 0x46a9b0 LDR	X4, [X12, X10,LSL #3]

        (1183) 0x46a9b4 LDR	X19, [X13, X4,LSL #3]

        (1183) 0x46a9b8 CMP	X19, #1

        (1183) 0x46a9bc B.LT	46a9a4

        (1183) 0x46a9c0 LDR	X4, [X9, X4,LSL #3]

        (1183) 0x46a9c4 CMP	X4, X18

        (1183) 0x46a9c8 B.EQ	46a9a4

        (1183) 0x46a9cc LDR	X19, [X24, X4,LSL #3]

        (1183) 0x46a9d0 CMP	X19, X1

        (1183) 0x46a9d4 B.GE	46a9a4

        (1183) 0x46a9d8 LDUR	X8, [X29, #480]

        (1183) 0x46a9dc STR	X8, [X24, X4,LSL #3]

        (1183) 0x46a9e0 LDUR	X8, [X29, #480]

        (1183) 0x46a9e4 ADD	X8, X8, #1

        (1183) 0x46a9e8 STUR	X8, [X29, #480]

        (1183) 0x46a9ec LDR	X8, [X11, X28,LSL #3]

        (1183) 0x46a9f0 B	46a9a4

0x46a9f4 HINT	#0

0x46a9f8 HINT	#0

0x46a9fc HINT	#0

      (1181) 0x46aa00 LDR	X10, [X14, X27,LSL #3]

      (1181) 0x46aa04 LDR	X9, [X14, X28,LSL #3]

      (1181) 0x46aa08 CMP	X10, X9

      (1181) 0x46aa0c B.GE	46a940

      (1181) 0x46aa10 LDUR	X8, [X29, #464]

      (1181) 0x46aa14 LDR	X8, [X8]

      (1181) 0x46aa18 B	46aa2c

0x46aa1c HINT	#0

        (1182) 0x46aa20 ADD	X10, X10, #1

        (1182) 0x46aa24 CMP	X10, X9

        (1182) 0x46aa28 B.GE	46a940

        (1182) 0x46aa2c LDR	X4, [X7, X10,LSL #3]

        (1182) 0x46aa30 LDR	X19, [X30, X4,LSL #3]

        (1182) 0x46aa34 CMP	X19, #1

        (1182) 0x46aa38 B.LT	46aa20

        (1182) 0x46aa3c LDR	X4, [X8, X4,LSL #3]

        (1182) 0x46aa40 LDR	X19, [X25, X4,LSL #3]

        (1182) 0x46aa44 CMP	X19, X2

        (1182) 0x46aa48 B.GE	46aa20

        (1182) 0x46aa4c LDUR	X9, [X29, #472]

        (1182) 0x46aa50 STR	X9, [X25, X4,LSL #3]

        (1182) 0x46aa54 LDUR	X9, [X29, #472]

        (1182) 0x46aa58 ADD	X9, X9, #1

        (1182) 0x46aa5c STUR	X9, [X29, #472]

        (1182) 0x46aa60 LDR	X9, [X14, X28,LSL #3]

        (1182) 0x46aa64 B	46aa20

    (1179) 0x46aa68 LDUR	X30, [X29, #416]

    (1179) 0x46aa6c LDUR	X10, [X29, #376]

    (1179) 0x46aa70 LDR	X4, [X14, X10,LSL #3]

    (1179) 0x46aa74 LDR	X8, [X14, X3,LSL #3]

    (1179) 0x46aa78 CMP	X4, X8

    (1179) 0x46aa7c B.GE	46a8c4

  (1180) 0x46aa80 LDUR	X8, [X29, #464]

  (1180) 0x46aa84 LDR	X5, [X8]

  (1180) 0x46aa88 LDUR	X8, [X29, #384]

  (1180) 0x46aa8c LDR	X6, [X8]

  (1180) 0x46aa90 LDUR	X8, [X29, #392]

  (1180) 0x46aa94 LDR	X7, [X8]

  (1180) 0x46aa98 B	46aab0

0x46aa9c HINT	#0

  (1180) 0x46aaa0 LDR	X8, [X14, X3,LSL #3]

  (1180) 0x46aaa4 ADD	X4, X4, #1

  (1180) 0x46aaa8 CMP	X4, X8

  (1180) 0x46aaac B.GE	46a8c4

  (1180) 0x46aab0 LDR	X28, [X15, X4,LSL #3]

  (1180) 0x46aab4 LDR	X8, [X16, X28,LSL #3]

  (1180) 0x46aab8 CMP	X8, #1

  (1180) 0x46aabc B.LT	46aae4

  (1180) 0x46aac0 LDR	X8, [X5, X28,LSL #3]

  (1180) 0x46aac4 LDR	X9, [X25, X8,LSL #3]

  (1180) 0x46aac8 CMP	X9, X2

  (1180) 0x46aacc B.GE	46aae4

  (1180) 0x46aad0 LDUR	X9, [X29, #472]

  (1180) 0x46aad4 STR	X9, [X25, X8,LSL #3]

  (1180) 0x46aad8 LDUR	X8, [X29, #472]

  (1180) 0x46aadc ADD	X8, X8, #1

  (1180) 0x46aae0 STUR	X8, [X29, #472]

  (1180) 0x46aae4 ADD	X27, X28, #1

  (1180) 0x46aae8 LDR	X8, [X17, X28,LSL #3]

  (1180) 0x46aaec LDR	X9, [X17, X27,LSL #3]

  (1180) 0x46aaf0 B	46ab04

0x46aaf4 HINT	#0

0x46aaf8 HINT	#0

0x46aafc HINT	#0

(1185) 0x46ab00 ADD	X8, X8, #1

  (1180) 0x46ab04 CMP	X8, X9

  (1180) 0x46ab08 B.GE	46ab40

(1185) 0x46ab0c LDR	X10, [X6, X8,LSL #3]

(1185) 0x46ab10 CMP	X10, X18

(1185) 0x46ab14 B.EQ	46ab00

(1185) 0x46ab18 LDR	X19, [X24, X10,LSL #3]

(1185) 0x46ab1c CMP	X19, X1

(1185) 0x46ab20 B.GE	46ab00

(1185) 0x46ab24 LDUR	X9, [X29, #480]

(1185) 0x46ab28 STR	X9, [X24, X10,LSL #3]

(1185) 0x46ab2c LDUR	X9, [X29, #480]

(1185) 0x46ab30 ADD	X9, X9, #1

(1185) 0x46ab34 STUR	X9, [X29, #480]

(1185) 0x46ab38 LDR	X9, [X17, X27,LSL #3]

(1185) 0x46ab3c B	46ab00

  (1180) 0x46ab40 LDR	X8, [X0, X28,LSL #3]

  (1180) 0x46ab44 LDR	X9, [X0, X27,LSL #3]

  (1180) 0x46ab48 B	46ab50

    (1184) 0x46ab4c ADD	X8, X8, #1

    (1184) 0x46ab50 CMP	X8, X9

    (1184) 0x46ab54 B.GE	46aaa0

    (1184) 0x46ab58 LDR	X10, [X7, X8,LSL #3]

    (1184) 0x46ab5c LDR	X19, [X25, X10,LSL #3]

    (1184) 0x46ab60 CMP	X19, X2

    (1184) 0x46ab64 B.GE	46ab4c

    (1184) 0x46ab68 LDUR	X9, [X29, #472]

    (1184) 0x46ab6c STR	X9, [X25, X10,LSL #3]

    (1184) 0x46ab70 LDUR	X9, [X29, #472]

    (1184) 0x46ab74 ADD	X9, X9, #1

    (1184) 0x46ab78 STUR	X9, [X29, #472]

    (1184) 0x46ab7c LDR	X9, [X0, X27,LSL #3]

    (1184) 0x46ab80 B	46ab4c

0x46ab84 CMP	X22, X30

0x46ab88 B.GE	46b130

0x46ab8c LDR	X8, [SP, #96]

0x46ab90 ADD	X9, X20, #8

0x46ab94 ORR	X2, XZR, XZR

0x46ab98 ORR	X3, XZR, XZR

0x46ab9c MOVZ	W4, #1

0x46aba0 LDR	X8, [X8]

0x46aba4 ORR	X5, XZR, X22

0x46aba8 STUR	X8, [X29, #376]

0x46abac LDR	X8, [SP, #112]

0x46abb0 LDR	X8, [X8]

0x46abb4 STR	X8, [SP, #144]

0x46abb8 LDR	X8, [SP, #120]

0x46abbc LDR	X8, [X8]

0x46abc0 STR	X8, [SP, #128]

0x46abc4 LDR	X8, [SP, #24]

0x46abc8 LDR	X11, [X8]

0x46abcc LDR	X8, [SP, #32]

0x46abd0 LDR	X12, [X8]

0x46abd4 LDR	X8, [SP, #104]

0x46abd8 LDR	X13, [X8]

0x46abdc LDR	X8, [SP, #40]

0x46abe0 LDR	X14, [X8]

0x46abe4 LDUR	X8, [X29, #400]

0x46abe8 LDR	X8, [X8]

0x46abec STUR	X8, [X29, #448]

0x46abf0 ADD	X8, X21, #8

0x46abf4 STP	X8, X9, [SP, #64]

0x46abf8 LDUR	X8, [X29, #408]

0x46abfc LDR	X8, [X8]

0x46ac00 STUR	X8, [X29, #440]

0x46ac04 LDR	X8, [SP, #48]

0x46ac08 LDR	X1, [X8]

0x46ac0c LDR	X8, [SP, #56]

0x46ac10 LDR	X6, [X8]

0x46ac14 B	46ac2c

0x46ac18 HINT	#0

0x46ac1c HINT	#0

    (1169) 0x46ac20 ADD	X5, X5, #1

    (1169) 0x46ac24 CMP	X5, X16

    (1169) 0x46ac28 B.EQ	46b130

    (1169) 0x46ac2c LDUR	X8, [X29, #376]

    (1169) 0x46ac30 LDR	X9, [SP, #144]

    (1169) 0x46ac34 ORR	X7, XZR, X3

    (1169) 0x46ac38 ORR	X30, XZR, X2

    (1169) 0x46ac3c LDR	X15, [X8, X5,LSL #3]

    (1169) 0x46ac40 LDUR	X8, [X29, #480]

    (1169) 0x46ac44 STR	X8, [X9, X5,LSL #3]

    (1169) 0x46ac48 LDUR	X8, [X29, #432]

    (1169) 0x46ac4c LDR	X8, [X8]

    (1169) 0x46ac50 CBZ	X8, 46ac60

    (1169) 0x46ac54 LDUR	X8, [X29, #472]

    (1169) 0x46ac58 LDR	X9, [SP, #128]

    (1169) 0x46ac5c STR	X8, [X9, X5,LSL #3]

    (1169) 0x46ac60 ADD	X16, X15, #1

    (1169) 0x46ac64 LDR	X10, [X11, X15,LSL #3]

    (1169) 0x46ac68 ORR	X3, XZR, X7

    (1169) 0x46ac6c ORR	X2, XZR, X30

    (1169) 0x46ac70 LDR	X8, [X11, X16,LSL #3]

    (1169) 0x46ac74 CMP	X10, X8

    (1169) 0x46ac78 B.GE	46ae04

    (1169) 0x46ac7c STR	X15, [SP, #136]

    (1169) 0x46ac80 LDUR	X8, [X29, #456]

    (1169) 0x46ac84 LDP	X9, X15, [X29, #912]

    (1169) 0x46ac88 ORR	X2, XZR, X30

    (1169) 0x46ac8c ORR	X3, XZR, X7

    (1169) 0x46ac90 LDR	X8, [X8]

    (1169) 0x46ac94 LDR	X9, [X9]

    (1169) 0x46ac98 LDR	X0, [X15]

    (1169) 0x46ac9c B	46acb0

      (1175) 0x46aca0 LDR	X15, [X11, X16,LSL #3]

      (1175) 0x46aca4 ADD	X10, X10, #1

      (1175) 0x46aca8 CMP	X10, X15

      (1175) 0x46acac B.GE	46ae00

      (1175) 0x46acb0 LDR	X27, [X12, X10,LSL #3]

      (1175) 0x46acb4 LDR	X15, [X13, X27,LSL #3]

      (1175) 0x46acb8 CMP	X15, #1

      (1175) 0x46acbc B.LT	46ace4

      (1175) 0x46acc0 LDR	X15, [X8, X27,LSL #3]

      (1175) 0x46acc4 LDR	X17, [X24, X15,LSL #3]

      (1175) 0x46acc8 SUBS	X17, X17, X30

      (1175) 0x46accc B.GE	46ad00

      (1175) 0x46acd0 STR	X2, [X24, X15,LSL #3]

      (1175) 0x46acd4 SUB	X15, X2, X30

      (1175) 0x46acd8 MOVZ	W17, #2

      (1175) 0x46acdc ADD	X2, X2, #1

      (1175) 0x46ace0 STR	X17, [X20, X15,LSL #3]

      (1175) 0x46ace4 ADD	X28, X27, #1

      (1175) 0x46ace8 LDR	X17, [X11, X27,LSL #3]

      (1175) 0x46acec LDR	X15, [X11, X28,LSL #3]

      (1175) 0x46acf0 CMP	X17, X15

      (1175) 0x46acf4 B.LT	46ad20

      (1175) 0x46acf8 B	46ad8c

0x46acfc HINT	#0

      (1175) 0x46ad00 LDR	X15, [X20, X17,LSL #3]

      (1175) 0x46ad04 ADD	X15, X15, #2

      (1175) 0x46ad08 STR	X15, [X20, X17,LSL #3]

      (1175) 0x46ad0c ADD	X28, X27, #1

      (1175) 0x46ad10 LDR	X17, [X11, X27,LSL #3]

      (1175) 0x46ad14 LDR	X15, [X11, X28,LSL #3]

      (1175) 0x46ad18 CMP	X17, X15

      (1175) 0x46ad1c B.GE	46ad8c

      (1175) 0x46ad20 LDUR	X15, [X29, #456]

      (1175) 0x46ad24 LDR	X15, [X15]

      (1175) 0x46ad28 B	46ad50

        (1177) 0x46ad2c LDR	X18, [X20, X19,LSL #3]

        (1177) 0x46ad30 ADD	X18, X18, #1

        (1177) 0x46ad34 STR	X18, [X20, X19,LSL #3]

        (1177) 0x46ad38 HINT	#0

        (1177) 0x46ad3c HINT	#0

        (1177) 0x46ad40 LDR	X18, [X11, X28,LSL #3]

        (1177) 0x46ad44 ADD	X17, X17, #1

        (1177) 0x46ad48 CMP	X17, X18

        (1177) 0x46ad4c B.GE	46ad8c

        (1177) 0x46ad50 LDR	X18, [X12, X17,LSL #3]

        (1177) 0x46ad54 LDR	X19, [X13, X18,LSL #3]

        (1177) 0x46ad58 CMP	X19, #1

        (1177) 0x46ad5c B.LT	46ad40

        (1177) 0x46ad60 LDR	X18, [X15, X18,LSL #3]

        (1177) 0x46ad64 CMP	X18, X5

        (1177) 0x46ad68 B.EQ	46ad40

        (1177) 0x46ad6c LDR	X19, [X24, X18,LSL #3]

        (1177) 0x46ad70 SUBS	X19, X19, X30

        (1177) 0x46ad74 B.GE	46ad2c

        (1177) 0x46ad78 STR	X2, [X24, X18,LSL #3]

        (1177) 0x46ad7c SUB	X18, X2, X30

        (1177) 0x46ad80 ADD	X2, X2, #1

        (1177) 0x46ad84 STR	X4, [X20, X18,LSL #3]

        (1177) 0x46ad88 B	46ad40

      (1175) 0x46ad8c LDR	X17, [X14, X27,LSL #3]

      (1175) 0x46ad90 LDR	X15, [X14, X28,LSL #3]

      (1175) 0x46ad94 CMP	X17, X15

      (1175) 0x46ad98 B.GE	46aca0

      (1175) 0x46ad9c LDUR	X15, [X29, #464]

      (1175) 0x46ada0 LDR	X15, [X15]

      (1175) 0x46ada4 B	46adc4

        (1176) 0x46ada8 LDR	X18, [X21, X19,LSL #3]

        (1176) 0x46adac ADD	X18, X18, #1

        (1176) 0x46adb0 STR	X18, [X21, X19,LSL #3]

        (1176) 0x46adb4 LDR	X18, [X14, X28,LSL #3]

        (1176) 0x46adb8 ADD	X17, X17, #1

        (1176) 0x46adbc CMP	X17, X18

        (1176) 0x46adc0 B.GE	46aca0

        (1176) 0x46adc4 LDR	X18, [X9, X17,LSL #3]

        (1176) 0x46adc8 LDR	X19, [X0, X18,LSL #3]

        (1176) 0x46adcc CMP	X19, #1

        (1176) 0x46add0 B.LT	46adb4

        (1176) 0x46add4 LDR	X18, [X15, X18,LSL #3]

        (1176) 0x46add8 LDR	X19, [X25, X18,LSL #3]

        (1176) 0x46addc SUBS	X19, X19, X7

        (1176) 0x46ade0 B.GE	46ada8

        (1176) 0x46ade4 STR	X3, [X25, X18,LSL #3]

        (1176) 0x46ade8 SUB	X18, X3, X7

        (1176) 0x46adec ADD	X3, X3, #1

        (1176) 0x46adf0 STR	X4, [X21, X18,LSL #3]

        (1176) 0x46adf4 B	46adb4

0x46adf8 HINT	#0

0x46adfc HINT	#0

    (1169) 0x46ae00 LDR	X15, [SP, #136]

    (1169) 0x46ae04 LDR	X8, [X14, X15,LSL #3]

    (1169) 0x46ae08 LDR	X9, [X14, X16,LSL #3]

    (1169) 0x46ae0c CMP	X8, X9

    (1169) 0x46ae10 B.GE	46af80

    (1169) 0x46ae14 LDUR	X9, [X29, #464]

    (1169) 0x46ae18 LDP	X10, X15, [X29, #896]

    (1169) 0x46ae1c LDR	X9, [X9]

    (1169) 0x46ae20 LDR	X10, [X10]

    (1169) 0x46ae24 LDR	X17, [X15]

    (1169) 0x46ae28 B	46ae3c

      (1172) 0x46ae2c LDR	X15, [X14, X16,LSL #3]

      (1172) 0x46ae30 ADD	X8, X8, #1

      (1172) 0x46ae34 CMP	X8, X15

      (1172) 0x46ae38 B.GE	46af80

      (1172) 0x46ae3c LDUR	X15, [X29, #448]

      (1172) 0x46ae40 LDR	X27, [X15, X8,LSL #3]

      (1172) 0x46ae44 LDUR	X15, [X29, #440]

      (1172) 0x46ae48 LDR	X15, [X15, X27,LSL #3]

      (1172) 0x46ae4c CMP	X15, #1

      (1172) 0x46ae50 B.LT	46ae78

      (1172) 0x46ae54 LDR	X15, [X9, X27,LSL #3]

      (1172) 0x46ae58 LDR	X18, [X25, X15,LSL #3]

      (1172) 0x46ae5c SUBS	X18, X18, X7

      (1172) 0x46ae60 B.GE	46aea0

      (1172) 0x46ae64 STR	X3, [X25, X15,LSL #3]

      (1172) 0x46ae68 SUB	X15, X3, X7

      (1172) 0x46ae6c MOVZ	W18, #2

      (1172) 0x46ae70 ADD	X3, X3, #1

      (1172) 0x46ae74 STR	X18, [X21, X15,LSL #3]

      (1172) 0x46ae78 LDR	X15, [X1, X27,LSL #3]

      (1172) 0x46ae7c ADD	X0, X27, #1

      (1172) 0x46ae80 LDR	X18, [X1, X0,LSL #3]

      (1172) 0x46ae84 CMP	X15, X18

      (1172) 0x46ae88 B.LT	46aee0

      (1172) 0x46ae8c B	46af18

0x46ae90 HINT	#0

0x46ae94 HINT	#0

0x46ae98 HINT	#0

0x46ae9c HINT	#0

      (1172) 0x46aea0 LDR	X15, [X21, X18,LSL #3]

      (1172) 0x46aea4 ADD	X15, X15, #2

      (1172) 0x46aea8 STR	X15, [X21, X18,LSL #3]

      (1172) 0x46aeac LDR	X15, [X1, X27,LSL #3]

      (1172) 0x46aeb0 ADD	X0, X27, #1

      (1172) 0x46aeb4 LDR	X18, [X1, X0,LSL #3]

      (1172) 0x46aeb8 CMP	X15, X18

      (1172) 0x46aebc B.LT	46aee0

      (1172) 0x46aec0 B	46af18

        (1174) 0x46aec4 LDR	X18, [X20, X19,LSL #3]

        (1174) 0x46aec8 ADD	X18, X18, #1

        (1174) 0x46aecc STR	X18, [X20, X19,LSL #3]

        (1174) 0x46aed0 ADD	X15, X15, #1

        (1174) 0x46aed4 LDR	X18, [X1, X0,LSL #3]

        (1174) 0x46aed8 CMP	X15, X18

        (1174) 0x46aedc B.GE	46af18

        (1174) 0x46aee0 LDR	X18, [X10, X15,LSL #3]

        (1174) 0x46aee4 CMP	X18, X5

        (1174) 0x46aee8 B.EQ	46aed0

        (1174) 0x46aeec LDR	X19, [X24, X18,LSL #3]

        (1174) 0x46aef0 SUBS	X19, X19, X30

        (1174) 0x46aef4 B.GE	46aec4

        (1174) 0x46aef8 STR	X2, [X24, X18,LSL #3]

        (1174) 0x46aefc SUB	X18, X2, X30

        (1174) 0x46af00 ADD	X2, X2, #1

        (1174) 0x46af04 ADD	X15, X15, #1

        (1174) 0x46af08 STR	X4, [X20, X18,LSL #3]

        (1174) 0x46af0c LDR	X18, [X1, X0,LSL #3]

        (1174) 0x46af10 CMP	X15, X18

        (1174) 0x46af14 B.LT	46aee0

      (1172) 0x46af18 LDR	X15, [X6, X27,LSL #3]

      (1172) 0x46af1c LDR	X18, [X6, X0,LSL #3]

      (1172) 0x46af20 CMP	X15, X18

      (1172) 0x46af24 B.LT	46af4c

      (1172) 0x46af28 B	46ae2c

        (1173) 0x46af2c STR	X3, [X25, X18,LSL #3]

        (1173) 0x46af30 SUB	X18, X3, X7

        (1173) 0x46af34 ADD	X3, X3, #1

        (1173) 0x46af38 ADD	X15, X15, #1

        (1173) 0x46af3c STR	X4, [X21, X18,LSL #3]

        (1173) 0x46af40 LDR	X18, [X6, X0,LSL #3]

        (1173) 0x46af44 CMP	X15, X18

        (1173) 0x46af48 B.GE	46ae2c

        (1173) 0x46af4c LDR	X18, [X17, X15,LSL #3]

        (1173) 0x46af50 LDR	X19, [X25, X18,LSL #3]

        (1173) 0x46af54 SUBS	X19, X19, X7

        (1173) 0x46af58 B.LT	46af2c

        (1173) 0x46af5c LDR	X18, [X21, X19,LSL #3]

        (1173) 0x46af60 ADD	X15, X15, #1

        (1173) 0x46af64 ADD	X18, X18, #1

        (1173) 0x46af68 STR	X18, [X21, X19,LSL #3]

        (1173) 0x46af6c LDR	X18, [X6, X0,LSL #3]

        (1173) 0x46af70 CMP	X15, X18

        (1173) 0x46af74 B.LT	46af4c

      (1172) 0x46af78 B	46ae2c

0x46af7c HINT	#0

    (1169) 0x46af80 CMP	X2, X30

    (1169) 0x46af84 B.LE	46afc8

    (1169) 0x46af88 SUB	W8, W2, W30

    (1169) 0x46af8c ORR	X9, XZR, X30

    (1169) 0x46af90 TBZ	W8, #0, 46afbc

    (1169) 0x46af94 LDUR	X9, [X29, #424]

    (1169) 0x46af98 LDR	X8, [X20]

    (1169) 0x46af9c LDR	X9, [X9]

    (1169) 0x46afa0 CMP	X8, X9

    (1169) 0x46afa4 B.LT	46afb4

    (1169) 0x46afa8 LDUR	X8, [X29, #480]

    (1169) 0x46afac ADD	X8, X8, #1

    (1169) 0x46afb0 STUR	X8, [X29, #480]

    (1169) 0x46afb4 ADD	X9, X30, #1

    (1169) 0x46afb8 STR	XZR, [X20]

    (1169) 0x46afbc ADD	X8, X30, #1

    (1169) 0x46afc0 CMP	X2, X8

    (1169) 0x46afc4 B.NE	46b0a0

    (1169) 0x46afc8 LDP	X16, X17, [X29, #928]

    (1169) 0x46afcc CMP	X3, X7

    (1169) 0x46afd0 B.LE	46ac20

    (1169) 0x46afd4 SUB	W8, W3, W7

    (1169) 0x46afd8 ORR	X9, XZR, X7

    (1169) 0x46afdc TBZ	W8, #0, 46b004

    (1169) 0x46afe0 LDR	X8, [X21]

    (1169) 0x46afe4 LDR	X9, [X17]

    (1169) 0x46afe8 CMP	X8, X9

    (1169) 0x46afec B.LT	46affc

    (1169) 0x46aff0 LDUR	X8, [X29, #472]

    (1169) 0x46aff4 ADD	X8, X8, #1

    (1169) 0x46aff8 STUR	X8, [X29, #472]

    (1169) 0x46affc ADD	X9, X7, #1

    (1169) 0x46b000 STR	XZR, [X21]

    (1169) 0x46b004 ADD	X8, X7, #1

    (1169) 0x46b008 CMP	X3, X8

    (1169) 0x46b00c B.EQ	46ac20

    (1169) 0x46b010 LDR	X10, [SP, #64]

    (1169) 0x46b014 SUB	X8, X3, X9

    (1169) 0x46b018 SUB	X10, X10, X7,LSL #3

    (1169) 0x46b01c ADD	X9, X10, X9,LSL #3

    (1169) 0x46b020 B	46b030

      (1178) 0x46b024 STR	XZR, [X9], #16

      (1178) 0x46b028 SUBS	X8, X8, #2

      (1178) 0x46b02c B.EQ	46ac20

      (1178) 0x46b030 LDUR	X10, [X9, #504]

      (1178) 0x46b034 LDR	X15, [X17]

      (1178) 0x46b038 CMP	X10, X15

      (1178) 0x46b03c B.GE	46b060

      (1178) 0x46b040 STUR	XZR, [X9, #504]

      (1178) 0x46b044 LDR	X10, [X9]

      (1178) 0x46b048 LDR	X15, [X17]

      (1178) 0x46b04c CMP	X10, X15

      (1178) 0x46b050 B.LT	46b024

      (1178) 0x46b054 B	46b080

0x46b058 HINT	#0

0x46b05c HINT	#0

      (1178) 0x46b060 LDUR	X10, [X29, #472]

      (1178) 0x46b064 ADD	X10, X10, #1

      (1178) 0x46b068 STUR	X10, [X29, #472]

      (1178) 0x46b06c STUR	XZR, [X9, #504]

      (1178) 0x46b070 LDR	X10, [X9]

      (1178) 0x46b074 LDR	X15, [X17]

      (1178) 0x46b078 CMP	X10, X15

      (1178) 0x46b07c B.LT	46b024

      (1178) 0x46b080 LDUR	X10, [X29, #472]

      (1178) 0x46b084 ADD	X10, X10, #1

      (1178) 0x46b088 STUR	X10, [X29, #472]

      (1178) 0x46b08c B	46b024

0x46b090 HINT	#0

0x46b094 HINT	#0

0x46b098 HINT	#0

0x46b09c HINT	#0

  (1171) 0x46b0a0 LDR	X10, [SP, #72]

  (1171) 0x46b0a4 LDUR	X16, [X29, #424]

  (1171) 0x46b0a8 SUB	X8, X2, X9

  (1171) 0x46b0ac SUB	X10, X10, X30,LSL #3

  (1171) 0x46b0b0 ADD	X9, X10, X9,LSL #3

  (1171) 0x46b0b4 B	46b0cc

0x46b0b8 HINT	#0

0x46b0bc HINT	#0

  (1171) 0x46b0c0 STR	XZR, [X9], #16

  (1171) 0x46b0c4 SUBS	X8, X8, #2

  (1171) 0x46b0c8 B.EQ	46afc8

  (1171) 0x46b0cc LDUR	X10, [X9, #504]

  (1171) 0x46b0d0 LDR	X15, [X16]

  (1171) 0x46b0d4 CMP	X10, X15

  (1171) 0x46b0d8 B.GE	46b100

  (1171) 0x46b0dc STUR	XZR, [X9, #504]

  (1171) 0x46b0e0 LDR	X10, [X9]

  (1171) 0x46b0e4 LDR	X15, [X16]

  (1171) 0x46b0e8 CMP	X10, X15

  (1171) 0x46b0ec B.LT	46b0c0

  (1171) 0x46b0f0 B	46b120

0x46b0f4 HINT	#0

0x46b0f8 HINT	#0

0x46b0fc HINT	#0

(1170) 0x46b100 LDUR	X10, [X29, #480]

(1170) 0x46b104 ADD	X10, X10, #1

(1170) 0x46b108 STUR	X10, [X29, #480]

(1170) 0x46b10c STUR	XZR, [X9, #504]

(1170) 0x46b110 LDR	X10, [X9]

(1170) 0x46b114 LDR	X15, [X16]

(1170) 0x46b118 CMP	X10, X15

(1170) 0x46b11c B.LT	46b0c0

  (1171) 0x46b120 LDUR	X10, [X29, #480]

  (1171) 0x46b124 ADD	X10, X10, #1

  (1171) 0x46b128 STUR	X10, [X29, #480]

  (1171) 0x46b12c B	46b0c0

0x46b130 LDR	X19, [SP, #88]

0x46b134 LDR	X8, [SP, #112]

0x46b138 SUB	X0, X29, #32

0x46b13c SUB	X2, X29, #40

0x46b140 LDR	X9, [X19]

0x46b144 LDR	X8, [X8]

0x46b148 UBFM	X9, X9, #61, #60

0x46b14c ADD	X1, X8, X9

0x46b150 LDR	X8, [SP, #120]

0x46b154 LDR	X8, [X8]

0x46b158 ADD	X3, X8, X9

0x46b15c LDR	X8, [SP, #80]

0x46b160 LDR	X4, [X8]

0x46b164 BL	4b1270

0x46b168 LDR	X8, [X19]

0x46b16c LDUR	X12, [X29, #432]

0x46b170 CMP	X8, #1

0x46b174 B.LT	46b198

0x46b178 ORR	X11, XZR, X19

0x46b17c ORR	X8, XZR, XZR

0x46b180 MOVN	X9, #0

(1168) 0x46b184 STR	X9, [X24, X8,LSL #3]

(1168) 0x46b188 ADD	X8, X8, #1

(1168) 0x46b18c LDR	X10, [X11]

(1168) 0x46b190 CMP	X8, X10

(1168) 0x46b194 B.LT	46b184

0x46b198 LDP	X8, X28, [X29, #264]

0x46b19c STUR	X8, [X29, #448]

0x46b1a0 LDR	X8, [X12]

0x46b1a4 CMP	X8, #1

0x46b1a8 B.LT	46b1d4

0x46b1ac ORR	X8, XZR, XZR

0x46b1b0 MOVN	X9, #0

0x46b1b4 HINT	#0

0x46b1b8 HINT	#0

0x46b1bc HINT	#0

(1167) 0x46b1c0 STR	X9, [X25, X8,LSL #3]

(1167) 0x46b1c4 ADD	X8, X8, #1

(1167) 0x46b1c8 LDR	X10, [X12]

(1167) 0x46b1cc CMP	X8, X10

(1167) 0x46b1d0 B.LT	46b1c0

0x46b1d4 LDR	X8, [SP, #16]

0x46b1d8 ADRP	X0,

0x46b1dc ADD	X0, X0, #592

0x46b1e0 LDR	W27, [X8]

0x46b1e4 ORR	W1, WZR, W27

0x46b1e8 BL	40f900

0x46b1ec ORR	W1, WZR, W27

0x46b1f0 ADRP	X0,

0x46b1f4 ADD	X0, X0, #616

0x46b1f8 BL	40f4c0

0x46b1fc CBZ	W0, 46b25c

0x46b200 LDR	X8, [SP, #112]

0x46b204 LDR	X10, [SP, #88]

0x46b208 LDR	X9, [X8]

0x46b20c LDR	X8, [X10]

0x46b210 LDR	X9, [X9, X8,LSL #3]

0x46b214 CBZ	X9, 46b230

0x46b218 UBFM	X0, X9, #61, #60

0x46b21c ORR	X19, XZR, X10

0x46b220 BL	4ae3c0

0x46b224 LDUR	X8, [X29, #448]

0x46b228 STR	X0, [X8]

0x46b22c LDR	X8, [X19]

0x46b230 LDR	X9, [SP, #120]

0x46b234 LDR	X9, [X9]

0x46b238 LDR	X8, [X9, X8,LSL #3]

0x46b23c CBZ	X8, 46b24c

0x46b240 UBFM	X0, X8, #61, #60

0x46b244 BL	4ae3c0

0x46b248 STR	X0, [X28]

0x46b24c ORR	W1, WZR, W27

0x46b250 ADRP	X0,

0x46b254 ADD	X0, X0, #616

0x46b258 BL	40f990

0x46b25c ORR	W1, WZR, W27

0x46b260 ADRP	X0,

0x46b264 ADD	X0, X0, #640

0x46b268 BL	40f900

0x46b26c LDUR	X30, [X29, #416]

0x46b270 ORR	X9, XZR, X22

0x46b274 SUB	X8, X30, #1

0x46b278 CMP	X22, X8

0x46b27c B.GE	46b318

0x46b280 LDP	X10, X9, [SP, #104]

0x46b284 ORN	X11, XZR, X22

0x46b288 UBFM	X14, X22, #61, #60

0x46b28c ADD	X11, X11, X30

0x46b290 LDR	X12, [X9]

0x46b294 LDR	X9, [SP, #120]

0x46b298 LDR	X10, [X10]

0x46b29c LDR	X13, [X9]

0x46b2a0 LDR	X9, [SP, #96]

0x46b2a4 ADD	X12, X12, X14

0x46b2a8 LDR	X9, [X9]

0x46b2ac ADD	X13, X13, X14

0x46b2b0 ADD	X9, X9, X14

0x46b2b4 MOVZ	W14, #2

0x46b2b8 B	46b2e8

0x46b2bc HINT	#0

(1166) 0x46b2c0 LDUR	X16, [X29, #480]

(1166) 0x46b2c4 ADD	X9, X9, #8

(1166) 0x46b2c8 SUBS	X11, X11, #1

(1166) 0x46b2cc ADD	X15, X16, X15

(1166) 0x46b2d0 STR	X15, [X12], #8

(1166) 0x46b2d4 LDUR	X15, [X29, #472]

(1166) 0x46b2d8 LDR	X16, [X13]

(1166) 0x46b2dc ADD	X15, X16, X15

(1166) 0x46b2e0 STR	X15, [X13], #8

(1166) 0x46b2e4 B.EQ	46b314

(1166) 0x46b2e8 LDP	X15, X16, [X12]

(1166) 0x46b2ec CMP	X16, X15

(1166) 0x46b2f0 B.NE	46b2c0

(1166) 0x46b2f4 LDP	X17, X15, [X13]

(1166) 0x46b2f8 CMP	X15, X17

(1166) 0x46b2fc ORR	X15, XZR, X16

(1166) 0x46b300 B.NE	46b2c0

(1166) 0x46b304 LDR	X15, [X9]

(1166) 0x46b308 STR	X14, [X10, X15,LSL #3]

(1166) 0x46b30c LDR	X15, [X12]

(1166) 0x46b310 B	46b2c0

0x46b314 ORR	X9, XZR, X8

0x46b318 CMP	X22, X30

0x46b31c B.GE	46bcc0

0x46b320 LDR	X8, [SP, #112]

0x46b324 LDUR	X10, [X29, #480]

0x46b328 LDR	X13, [SP, #8]

0x46b32c LDR	X11, [X8]

0x46b330 LDR	X8, [X11, X9,LSL #3]

0x46b334 ADD	X8, X8, X10

0x46b338 LDR	X10, [SP, #120]

0x46b33c STR	X8, [X11, X9,LSL #3]

0x46b340 LDUR	X8, [X29, #472]

0x46b344 LDR	X10, [X10]

0x46b348 LDR	X12, [X10, X9,LSL #3]

0x46b34c ADD	X8, X12, X8

0x46b350 UBFM	X12, X13, #60, #59

0x46b354 STR	X8, [X10, X9,LSL #3]

0x46b358 LDR	X10, [SP, #80]

0x46b35c LDR	X11, [X11, X9,LSL #3]

0x46b360 LDR	X10, [X10]

0x46b364 LDR	X12, [X10, X12]

0x46b368 CMP	X12, X11

0x46b36c B.NE	46b3a0

0x46b370 UBFM	X11, X13, #63, #62

0x46b374 UBFM	X11, X11, #61, #60

0x46b378 ORR	X11, X11, #4157

0x46b37c LDR	X10, [X10, X11]

0x46b380 CMP	X10, X8

0x46b384 B.NE	46b3a0

0x46b388 LDP	X10, X8, [SP, #96]

0x46b38c LDR	X10, [X10]

0x46b390 LDR	X8, [X8]

0x46b394 LDR	X9, [X10, X9,LSL #3]

0x46b398 MOVZ	W10, #2

0x46b39c STR	X10, [X8, X9,LSL #3]

0x46b3a0 LDUR	X8, [X29, #424]

0x46b3a4 STUR	X28, [X29, #432]

0x46b3a8 LDR	X8, [X8]

0x46b3ac CMP	X8, #1

0x46b3b0 B.NE	46b6e0

0x46b3b4 LDP	X8, X11, [SP, #96]

0x46b3b8 LDP	X9, X10, [SP, #24]

0x46b3bc LDP	X12, X15, [SP, #40]

0x46b3c0 LDP	X13, X14, [X29, #912]

0x46b3c4 LDR	X16, [SP, #56]

0x46b3c8 LDR	X8, [X8]

0x46b3cc LDR	X9, [X9]

0x46b3d0 LDR	X10, [X10]

0x46b3d4 LDR	X11, [X11]

0x46b3d8 LDR	X12, [X12]

0x46b3dc LDR	X13, [X13]

0x46b3e0 LDR	X14, [X14]

0x46b3e4 LDR	X15, [X15]

0x46b3e8 LDR	X16, [X16]

0x46b3ec B	46b40c

0x46b3f0 HINT	#0

0x46b3f4 HINT	#0

0x46b3f8 HINT	#0

0x46b3fc HINT	#0

    (1159) 0x46b400 ADD	X22, X22, #1

    (1159) 0x46b404 CMP	X22, X30

    (1159) 0x46b408 B.EQ	46bcc0

    (1159) 0x46b40c LDR	X1, [X8, X22,LSL #3]

    (1159) 0x46b410 LDP	X18, X17, [X29, #984]

    (1159) 0x46b414 ADD	X0, X1, #1

    (1159) 0x46b418 LDR	X2, [X9, X1,LSL #3]

    (1159) 0x46b41c LDR	X3, [X9, X0,LSL #3]

    (1159) 0x46b420 CMP	X2, X3

    (1159) 0x46b424 B.GE	46b5a0

    (1159) 0x46b428 LDP	X4, X3, [X29, #960]

    (1159) 0x46b42c LDP	X5, X6, [X29, #912]

    (1159) 0x46b430 LDR	X3, [X3]

    (1159) 0x46b434 LDR	X4, [X4]

    (1159) 0x46b438 LDR	X5, [X5]

    (1159) 0x46b43c LDR	X6, [X6]

    (1159) 0x46b440 B	46b454

      (1162) 0x46b444 LDR	X7, [X9, X0,LSL #3]

      (1162) 0x46b448 ADD	X2, X2, #1

      (1162) 0x46b44c CMP	X2, X7

      (1162) 0x46b450 B.GE	46b5a0

      (1162) 0x46b454 LDR	X19, [X10, X2,LSL #3]

      (1162) 0x46b458 LDR	X7, [X11, X19,LSL #3]

      (1162) 0x46b45c CMP	X7, #1

      (1162) 0x46b460 B.LT	46b490

      (1162) 0x46b464 LDR	X7, [X3, X19,LSL #3]

      (1162) 0x46b468 LDR	X20, [X24, X7,LSL #3]

      (1162) 0x46b46c CMP	X20, X17

      (1162) 0x46b470 B.GE	46b490

      (1162) 0x46b474 LDUR	X20, [X29, #480]

      (1162) 0x46b478 STR	X20, [X24, X7,LSL #3]

      (1162) 0x46b47c LDUR	X20, [X29, #480]

      (1162) 0x46b480 STR	X7, [X4, X20,LSL #3]

      (1162) 0x46b484 LDUR	X7, [X29, #480]

      (1162) 0x46b488 ADD	X7, X7, #1

      (1162) 0x46b48c STUR	X7, [X29, #480]

      (1162) 0x46b490 ADD	X7, X19, #1

      (1162) 0x46b494 LDR	X20, [X9, X19,LSL #3]

      (1162) 0x46b498 LDR	X23, [X9, X7,LSL #3]

      (1162) 0x46b49c CMP	X20, X23

      (1162) 0x46b4a0 B.GE	46b524

      (1162) 0x46b4a4 LDP	X26, X21, [X29, #960]

      (1162) 0x46b4a8 LDR	X21, [X21]

      (1162) 0x46b4ac LDR	X26, [X26]

      (1162) 0x46b4b0 B	46b4cc

0x46b4b4 HINT	#0

0x46b4b8 HINT	#0

0x46b4bc HINT	#0

        (1164) 0x46b4c0 ADD	X20, X20, #1

        (1164) 0x46b4c4 CMP	X20, X23

        (1164) 0x46b4c8 B.GE	46b520

        (1164) 0x46b4cc LDR	X27, [X10, X20,LSL #3]

        (1164) 0x46b4d0 LDR	X28, [X11, X27,LSL #3]

        (1164) 0x46b4d4 CMP	X28, #1

        (1164) 0x46b4d8 B.LT	46b4c0

        (1164) 0x46b4dc LDR	X27, [X21, X27,LSL #3]

        (1164) 0x46b4e0 CMP	X27, X22

        (1164) 0x46b4e4 B.EQ	46b4c0

        (1164) 0x46b4e8 LDR	X28, [X24, X27,LSL #3]

        (1164) 0x46b4ec CMP	X28, X17

        (1164) 0x46b4f0 B.GE	46b4c0

        (1164) 0x46b4f4 LDUR	X23, [X29, #480]

        (1164) 0x46b4f8 STR	X23, [X24, X27,LSL #3]

        (1164) 0x46b4fc LDUR	X23, [X29, #480]

        (1164) 0x46b500 STR	X27, [X26, X23,LSL #3]

        (1164) 0x46b504 LDUR	X23, [X29, #480]

        (1164) 0x46b508 ADD	X23, X23, #1

        (1164) 0x46b50c STUR	X23, [X29, #480]

        (1164) 0x46b510 LDR	X23, [X9, X7,LSL #3]

        (1164) 0x46b514 B	46b4c0

0x46b518 HINT	#0

0x46b51c HINT	#0

      (1162) 0x46b520 LDUR	X28, [X29, #432]

      (1162) 0x46b524 LDR	X19, [X12, X19,LSL #3]

      (1162) 0x46b528 LDR	X23, [X12, X7,LSL #3]

      (1162) 0x46b52c CMP	X19, X23

      (1162) 0x46b530 B.GE	46b444

      (1162) 0x46b534 LDUR	X20, [X29, #464]

      (1162) 0x46b538 LDR	X21, [X28]

      (1162) 0x46b53c LDR	X20, [X20]

      (1162) 0x46b540 B	46b550

        (1163) 0x46b544 ADD	X19, X19, #1

        (1163) 0x46b548 CMP	X19, X23

        (1163) 0x46b54c B.GE	46b444

        (1163) 0x46b550 LDR	X26, [X5, X19,LSL #3]

        (1163) 0x46b554 LDR	X27, [X6, X26,LSL #3]

        (1163) 0x46b558 CMP	X27, #1

        (1163) 0x46b55c B.LT	46b544

        (1163) 0x46b560 LDR	X26, [X20, X26,LSL #3]

        (1163) 0x46b564 LDR	X27, [X25, X26,LSL #3]

        (1163) 0x46b568 CMP	X27, X18

        (1163) 0x46b56c B.GE	46b544

        (1163) 0x46b570 LDUR	X23, [X29, #472]

        (1163) 0x46b574 STR	X23, [X25, X26,LSL #3]

        (1163) 0x46b578 LDUR	X23, [X29, #472]

        (1163) 0x46b57c STR	X26, [X21, X23,LSL #3]

        (1163) 0x46b580 LDUR	X23, [X29, #472]

        (1163) 0x46b584 ADD	X23, X23, #1

        (1163) 0x46b588 STUR	X23, [X29, #472]

        (1163) 0x46b58c LDR	X23, [X12, X7,LSL #3]

        (1163) 0x46b590 B	46b544

0x46b594 HINT	#0

0x46b598 HINT	#0

0x46b59c HINT	#0

    (1159) 0x46b5a0 LDR	X1, [X12, X1,LSL #3]

    (1159) 0x46b5a4 LDR	X2, [X12, X0,LSL #3]

    (1159) 0x46b5a8 CMP	X1, X2

    (1159) 0x46b5ac B.GE	46b400

  (1160) 0x46b5b0 LDUR	X2, [X29, #464]

  (1160) 0x46b5b4 LDP	X4, X5, [X29, #896]

  (1160) 0x46b5b8 LDR	X3, [X28]

  (1160) 0x46b5bc LDR	X2, [X2]

  (1160) 0x46b5c0 LDR	X4, [X4]

  (1160) 0x46b5c4 LDR	X5, [X5]

  (1160) 0x46b5c8 B	46b5dc

  (1160) 0x46b5cc LDR	X6, [X12, X0,LSL #3]

  (1160) 0x46b5d0 ADD	X1, X1, #1

  (1160) 0x46b5d4 CMP	X1, X6

  (1160) 0x46b5d8 B.GE	46b400

  (1160) 0x46b5dc LDR	X7, [X13, X1,LSL #3]

  (1160) 0x46b5e0 LDR	X6, [X14, X7,LSL #3]

  (1160) 0x46b5e4 CMP	X6, #1

  (1160) 0x46b5e8 B.LT	46b618

  (1160) 0x46b5ec LDR	X6, [X2, X7,LSL #3]

  (1160) 0x46b5f0 LDR	X19, [X25, X6,LSL #3]

  (1160) 0x46b5f4 CMP	X19, X18

  (1160) 0x46b5f8 B.GE	46b618

  (1160) 0x46b5fc LDUR	X19, [X29, #472]

  (1160) 0x46b600 STR	X19, [X25, X6,LSL #3]

  (1160) 0x46b604 LDUR	X19, [X29, #472]

  (1160) 0x46b608 STR	X6, [X3, X19,LSL #3]

  (1160) 0x46b60c LDUR	X6, [X29, #472]

  (1160) 0x46b610 ADD	X6, X6, #1

  (1160) 0x46b614 STUR	X6, [X29, #472]

  (1160) 0x46b618 ADD	X6, X7, #1

  (1160) 0x46b61c LDR	X19, [X15, X7,LSL #3]

  (1160) 0x46b620 LDR	X21, [X15, X6,LSL #3]

  (1160) 0x46b624 CMP	X19, X21

  (1160) 0x46b628 B.GE	46b688

(1161) 0x46b62c LDUR	X20, [X29, #448]

(1161) 0x46b630 LDR	X20, [X20]

(1161) 0x46b634 B	46b64c

0x46b638 HINT	#0

0x46b63c HINT	#0

(1161) 0x46b640 ADD	X19, X19, #1

(1161) 0x46b644 CMP	X19, X21

(1161) 0x46b648 B.GE	46b688

(1161) 0x46b64c LDR	X23, [X4, X19,LSL #3]

(1161) 0x46b650 CMP	X23, X22

(1161) 0x46b654 B.EQ	46b640

(1161) 0x46b658 LDR	X26, [X24, X23,LSL #3]

(1161) 0x46b65c CMP	X26, X17

(1161) 0x46b660 B.GE	46b640

(1161) 0x46b664 LDUR	X21, [X29, #480]

(1161) 0x46b668 STR	X21, [X24, X23,LSL #3]

(1161) 0x46b66c LDUR	X21, [X29, #480]

(1161) 0x46b670 STR	X23, [X20, X21,LSL #3]

(1161) 0x46b674 LDUR	X21, [X29, #480]

(1161) 0x46b678 ADD	X21, X21, #1

(1161) 0x46b67c STUR	X21, [X29, #480]

(1161) 0x46b680 LDR	X21, [X15, X6,LSL #3]

(1161) 0x46b684 B	46b640

  (1160) 0x46b688 LDR	X7, [X16, X7,LSL #3]

  (1160) 0x46b68c LDR	X20, [X16, X6,LSL #3]

  (1160) 0x46b690 CMP	X7, X20

  (1160) 0x46b694 B.GE	46b5cc

  (1160) 0x46b698 LDR	X19, [X28]

  (1160) 0x46b69c B	46b6ac

    (1165) 0x46b6a0 ADD	X7, X7, #1

    (1165) 0x46b6a4 CMP	X7, X20

    (1165) 0x46b6a8 B.GE	46b5cc

    (1165) 0x46b6ac LDR	X21, [X5, X7,LSL #3]

    (1165) 0x46b6b0 LDR	X23, [X25, X21,LSL #3]

    (1165) 0x46b6b4 CMP	X23, X18

    (1165) 0x46b6b8 B.GE	46b6a0

    (1165) 0x46b6bc LDUR	X20, [X29, #472]

    (1165) 0x46b6c0 STR	X20, [X25, X21,LSL #3]

    (1165) 0x46b6c4 LDUR	X20, [X29, #472]

    (1165) 0x46b6c8 STR	X21, [X19, X20,LSL #3]

    (1165) 0x46b6cc LDUR	X20, [X29, #472]

    (1165) 0x46b6d0 ADD	X20, X20, #1

    (1165) 0x46b6d4 STUR	X20, [X29, #472]

    (1165) 0x46b6d8 LDR	X20, [X16, X6,LSL #3]

    (1165) 0x46b6dc B	46b6a0

0x46b6e0 LDR	X8, [SP, #96]

0x46b6e4 LDP	X12, X13, [X29, #984]

0x46b6e8 MOVZ	W4, #1

0x46b6ec LDR	X8, [X8]

0x46b6f0 STUR	X8, [X29, #376]

0x46b6f4 LDR	X8, [SP, #24]

0x46b6f8 LDR	X9, [X8]

0x46b6fc LDR	X8, [SP, #32]

0x46b700 LDR	X10, [X8]

0x46b704 LDR	X8, [SP, #104]

0x46b708 LDR	X11, [X8]

0x46b70c LDR	X8, [SP, #40]

0x46b710 LDR	X14, [X8]

0x46b714 ADD	X8, X26, #8

0x46b718 STR	X8, [SP, #136]

0x46b71c LDUR	X8, [X29, #400]

0x46b720 LDR	X8, [X8]

0x46b724 STUR	X8, [X29, #440]

0x46b728 ADD	X8, X20, #8

0x46b72c STR	X8, [SP, #128]

0x46b730 ADD	X8, X23, #8

0x46b734 STR	X8, [SP, #120]

0x46b738 LDUR	X8, [X29, #408]

0x46b73c LDR	X0, [X8]

0x46b740 ADD	X8, X21, #8

0x46b744 STR	X8, [SP, #112]

0x46b748 LDR	X8, [SP, #48]

0x46b74c LDR	X2, [X8]

0x46b750 LDR	X8, [SP, #56]

0x46b754 LDR	X5, [X8]

0x46b758 B	46b76c

0x46b75c HINT	#0

    (1149) 0x46b760 ADD	X22, X22, #1

    (1149) 0x46b764 CMP	X22, X19

    (1149) 0x46b768 B.EQ	46bcc0

    (1149) 0x46b76c LDUR	X8, [X29, #376]

    (1149) 0x46b770 ORR	X6, XZR, X12

    (1149) 0x46b774 ORR	X7, XZR, X13

    (1149) 0x46b778 LDR	X15, [X8, X22,LSL #3]

    (1149) 0x46b77c ADD	X30, X15, #1

    (1149) 0x46b780 LDR	X17, [X9, X15,LSL #3]

    (1149) 0x46b784 LDR	X8, [X9, X30,LSL #3]

    (1149) 0x46b788 CMP	X17, X8

    (1149) 0x46b78c B.GE	46b948

    (1149) 0x46b790 LDUR	X8, [X29, #456]

    (1149) 0x46b794 ORR	X13, XZR, X7

    (1149) 0x46b798 ORR	X12, XZR, X6

    (1149) 0x46b79c STR	X15, [SP, #144]

    (1149) 0x46b7a0 LDR	X18, [X8]

    (1149) 0x46b7a4 LDUR	X8, [X29, #400]

    (1149) 0x46b7a8 LDR	X1, [X8]

    (1149) 0x46b7ac LDUR	X8, [X29, #408]

    (1149) 0x46b7b0 LDR	X8, [X8]

    (1149) 0x46b7b4 B	46b7d0

0x46b7b8 HINT	#0

0x46b7bc HINT	#0

      (1155) 0x46b7c0 LDR	X15, [X9, X30,LSL #3]

      (1155) 0x46b7c4 ADD	X17, X17, #1

      (1155) 0x46b7c8 CMP	X17, X15

      (1155) 0x46b7cc B.GE	46b940

      (1155) 0x46b7d0 LDR	X28, [X10, X17,LSL #3]

      (1155) 0x46b7d4 LDR	X15, [X11, X28,LSL #3]

      (1155) 0x46b7d8 CMP	X15, #1

      (1155) 0x46b7dc B.LT	46b808

      (1155) 0x46b7e0 LDR	X15, [X18, X28,LSL #3]

      (1155) 0x46b7e4 LDR	X16, [X24, X15,LSL #3]

      (1155) 0x46b7e8 SUBS	X16, X16, X7

      (1155) 0x46b7ec B.GE	46b820

      (1155) 0x46b7f0 SUB	X16, X13, X7

      (1155) 0x46b7f4 STR	X13, [X24, X15,LSL #3]

      (1155) 0x46b7f8 ADD	X13, X13, #1

      (1155) 0x46b7fc STR	X15, [X26, X16,LSL #3]

      (1155) 0x46b800 MOVZ	W15, #2

      (1155) 0x46b804 STR	X15, [X20, X16,LSL #3]

      (1155) 0x46b808 ADD	X3, X28, #1

      (1155) 0x46b80c LDR	X27, [X9, X28,LSL #3]

      (1155) 0x46b810 LDR	X15, [X9, X3,LSL #3]

      (1155) 0x46b814 CMP	X27, X15

      (1155) 0x46b818 B.LT	46b840

      (1155) 0x46b81c B	46b8c0

      (1155) 0x46b820 LDR	X15, [X20, X16,LSL #3]

      (1155) 0x46b824 ADD	X15, X15, #2

      (1155) 0x46b828 STR	X15, [X20, X16,LSL #3]

      (1155) 0x46b82c ADD	X3, X28, #1

      (1155) 0x46b830 LDR	X27, [X9, X28,LSL #3]

      (1155) 0x46b834 LDR	X15, [X9, X3,LSL #3]

      (1155) 0x46b838 CMP	X27, X15

      (1155) 0x46b83c B.GE	46b8c0

      (1155) 0x46b840 LDUR	X15, [X29, #456]

      (1155) 0x46b844 LDR	X15, [X15]

      (1155) 0x46b848 B	46b870

        (1157) 0x46b84c LDR	X16, [X20, X19,LSL #3]

        (1157) 0x46b850 ADD	X16, X16, #1

        (1157) 0x46b854 STR	X16, [X20, X19,LSL #3]

        (1157) 0x46b858 HINT	#0

        (1157) 0x46b85c HINT	#0

        (1157) 0x46b860 LDR	X16, [X9, X3,LSL #3]

        (1157) 0x46b864 ADD	X27, X27, #1

        (1157) 0x46b868 CMP	X27, X16

        (1157) 0x46b86c B.GE	46b8c0

        (1157) 0x46b870 LDR	X16, [X10, X27,LSL #3]

        (1157) 0x46b874 LDR	X19, [X11, X16,LSL #3]

        (1157) 0x46b878 CMP	X19, #1

        (1157) 0x46b87c B.LT	46b860

        (1157) 0x46b880 LDR	X16, [X15, X16,LSL #3]

        (1157) 0x46b884 CMP	X16, X22

        (1157) 0x46b888 B.EQ	46b860

        (1157) 0x46b88c LDR	X19, [X24, X16,LSL #3]

        (1157) 0x46b890 SUBS	X19, X19, X7

        (1157) 0x46b894 B.GE	46b84c

        (1157) 0x46b898 SUB	X19, X13, X7

        (1157) 0x46b89c STR	X13, [X24, X16,LSL #3]

        (1157) 0x46b8a0 ADD	X13, X13, #1

        (1157) 0x46b8a4 STR	X16, [X26, X19,LSL #3]

        (1157) 0x46b8a8 STR	X4, [X20, X19,LSL #3]

        (1157) 0x46b8ac B	46b860

0x46b8b0 HINT	#0

0x46b8b4 HINT	#0

0x46b8b8 HINT	#0

0x46b8bc HINT	#0

      (1155) 0x46b8c0 LDR	X27, [X14, X28,LSL #3]

      (1155) 0x46b8c4 LDR	X15, [X14, X3,LSL #3]

      (1155) 0x46b8c8 CMP	X27, X15

      (1155) 0x46b8cc B.GE	46b7c0

      (1155) 0x46b8d0 LDUR	X15, [X29, #464]

      (1155) 0x46b8d4 LDR	X15, [X15]

      (1155) 0x46b8d8 B	46b8fc

0x46b8dc HINT	#0

        (1156) 0x46b8e0 LDR	X16, [X21, X19,LSL #3]

        (1156) 0x46b8e4 ADD	X16, X16, #1

        (1156) 0x46b8e8 STR	X16, [X21, X19,LSL #3]

        (1156) 0x46b8ec LDR	X16, [X14, X3,LSL #3]

        (1156) 0x46b8f0 ADD	X27, X27, #1

        (1156) 0x46b8f4 CMP	X27, X16

        (1156) 0x46b8f8 B.GE	46b7c0

        (1156) 0x46b8fc LDR	X16, [X1, X27,LSL #3]

        (1156) 0x46b900 LDR	X19, [X8, X16,LSL #3]

        (1156) 0x46b904 CMP	X19, #1

        (1156) 0x46b908 B.LT	46b8ec

        (1156) 0x46b90c LDR	X16, [X15, X16,LSL #3]

        (1156) 0x46b910 LDR	X19, [X25, X16,LSL #3]

        (1156) 0x46b914 SUBS	X19, X19, X6

        (1156) 0x46b918 B.GE	46b8e0

        (1156) 0x46b91c SUB	X19, X12, X6

        (1156) 0x46b920 STR	X12, [X25, X16,LSL #3]

        (1156) 0x46b924 ADD	X12, X12, #1

        (1156) 0x46b928 STR	X16, [X23, X19,LSL #3]

        (1156) 0x46b92c STR	X4, [X21, X19,LSL #3]

        (1156) 0x46b930 B	46b8ec

0x46b934 HINT	#0

0x46b938 HINT	#0

0x46b93c HINT	#0

    (1149) 0x46b940 LDUR	X28, [X29, #432]

    (1149) 0x46b944 LDR	X15, [SP, #144]

    (1149) 0x46b948 LDR	X8, [X14, X15,LSL #3]

    (1149) 0x46b94c LDR	X15, [X14, X30,LSL #3]

    (1149) 0x46b950 CMP	X8, X15

    (1149) 0x46b954 B.GE	46bae0

    (1149) 0x46b958 LDUR	X16, [X29, #384]

    (1149) 0x46b95c LDUR	X15, [X29, #464]

    (1149) 0x46b960 LDR	X17, [X16]

    (1149) 0x46b964 LDUR	X16, [X29, #392]

    (1149) 0x46b968 LDR	X15, [X15]

    (1149) 0x46b96c LDR	X18, [X16]

    (1149) 0x46b970 B	46b990

0x46b974 HINT	#0

0x46b978 HINT	#0

0x46b97c HINT	#0

      (1152) 0x46b980 LDR	X16, [X14, X30,LSL #3]

      (1152) 0x46b984 ADD	X8, X8, #1

      (1152) 0x46b988 CMP	X8, X16

      (1152) 0x46b98c B.GE	46bae0

      (1152) 0x46b990 LDUR	X16, [X29, #440]

      (1152) 0x46b994 LDR	X3, [X16, X8,LSL #3]

      (1152) 0x46b998 LDR	X16, [X0, X3,LSL #3]

      (1152) 0x46b99c CMP	X16, #1

      (1152) 0x46b9a0 B.LT	46b9cc

      (1152) 0x46b9a4 LDR	X16, [X15, X3,LSL #3]

      (1152) 0x46b9a8 LDR	X1, [X25, X16,LSL #3]

      (1152) 0x46b9ac SUBS	X1, X1, X6

      (1152) 0x46b9b0 B.GE	46b9e4

      (1152) 0x46b9b4 SUB	X1, X12, X6

      (1152) 0x46b9b8 STR	X12, [X25, X16,LSL #3]

      (1152) 0x46b9bc ADD	X12, X12, #1

      (1152) 0x46b9c0 STR	X16, [X23, X1,LSL #3]

      (1152) 0x46b9c4 MOVZ	W16, #2

      (1152) 0x46b9c8 STR	X16, [X21, X1,LSL #3]

      (1152) 0x46b9cc LDR	X27, [X2, X3,LSL #3]

      (1152) 0x46b9d0 ADD	X1, X3, #1

      (1152) 0x46b9d4 LDR	X16, [X2, X1,LSL #3]

      (1152) 0x46b9d8 CMP	X27, X16

      (1152) 0x46b9dc B.LT	46ba24

      (1152) 0x46b9e0 B	46ba60

      (1152) 0x46b9e4 LDR	X16, [X21, X1,LSL #3]

      (1152) 0x46b9e8 ADD	X16, X16, #2

      (1152) 0x46b9ec STR	X16, [X21, X1,LSL #3]

      (1152) 0x46b9f0 LDR	X27, [X2, X3,LSL #3]

      (1152) 0x46b9f4 ADD	X1, X3, #1

      (1152) 0x46b9f8 LDR	X16, [X2, X1,LSL #3]

      (1152) 0x46b9fc CMP	X27, X16

      (1152) 0x46ba00 B.LT	46ba24

      (1152) 0x46ba04 B	46ba60

        (1154) 0x46ba08 LDR	X16, [X20, X19,LSL #3]

        (1154) 0x46ba0c ADD	X16, X16, #1

        (1154) 0x46ba10 STR	X16, [X20, X19,LSL #3]

        (1154) 0x46ba14 ADD	X27, X27, #1

        (1154) 0x46ba18 LDR	X16, [X2, X1,LSL #3]

        (1154) 0x46ba1c CMP	X27, X16

        (1154) 0x46ba20 B.GE	46ba60

        (1154) 0x46ba24 LDR	X16, [X17, X27,LSL #3]

        (1154) 0x46ba28 CMP	X16, X22

        (1154) 0x46ba2c B.EQ	46ba14

        (1154) 0x46ba30 LDR	X19, [X24, X16,LSL #3]

        (1154) 0x46ba34 SUBS	X19, X19, X7

        (1154) 0x46ba38 B.GE	46ba08

        (1154) 0x46ba3c SUB	X19, X13, X7

        (1154) 0x46ba40 STR	X13, [X24, X16,LSL #3]

        (1154) 0x46ba44 ADD	X13, X13, #1

        (1154) 0x46ba48 ADD	X27, X27, #1

        (1154) 0x46ba4c STR	X16, [X26, X19,LSL #3]

        (1154) 0x46ba50 STR	X4, [X20, X19,LSL #3]

        (1154) 0x46ba54 LDR	X16, [X2, X1,LSL #3]

        (1154) 0x46ba58 CMP	X27, X16

        (1154) 0x46ba5c B.LT	46ba24

      (1152) 0x46ba60 LDR	X3, [X5, X3,LSL #3]

      (1152) 0x46ba64 LDR	X16, [X5, X1,LSL #3]

      (1152) 0x46ba68 CMP	X3, X16

      (1152) 0x46ba6c B.LT	46baa4

      (1152) 0x46ba70 B	46b980

0x46ba74 HINT	#0

0x46ba78 HINT	#0

0x46ba7c HINT	#0

        (1153) 0x46ba80 SUB	X19, X12, X6

        (1153) 0x46ba84 STR	X12, [X25, X16,LSL #3]

        (1153) 0x46ba88 ADD	X12, X12, #1

        (1153) 0x46ba8c ADD	X3, X3, #1

        (1153) 0x46ba90 STR	X16, [X23, X19,LSL #3]

        (1153) 0x46ba94 STR	X4, [X21, X19,LSL #3]

        (1153) 0x46ba98 LDR	X16, [X5, X1,LSL #3]

        (1153) 0x46ba9c CMP	X3, X16

        (1153) 0x46baa0 B.GE	46b980

        (1153) 0x46baa4 LDR	X16, [X18, X3,LSL #3]

        (1153) 0x46baa8 LDR	X19, [X25, X16,LSL #3]

        (1153) 0x46baac SUBS	X19, X19, X6

        (1153) 0x46bab0 B.LT	46ba80

        (1153) 0x46bab4 LDR	X16, [X21, X19,LSL #3]

        (1153) 0x46bab8 ADD	X3, X3, #1

        (1153) 0x46babc ADD	X16, X16, #1

        (1153) 0x46bac0 STR	X16, [X21, X19,LSL #3]

        (1153) 0x46bac4 LDR	X16, [X5, X1,LSL #3]

        (1153) 0x46bac8 CMP	X3, X16

        (1153) 0x46bacc B.LT	46baa4

      (1152) 0x46bad0 B	46b980

0x46bad4 HINT	#0

0x46bad8 HINT	#0

0x46badc HINT	#0

    (1149) 0x46bae0 LDP	X19, X27, [X29, #928]

    (1149) 0x46bae4 CMP	X13, X7

    (1149) 0x46bae8 B.LE	46bb38

    (1149) 0x46baec LDUR	X8, [X29, #448]

    (1149) 0x46baf0 SUB	W15, W13, W7

    (1149) 0x46baf4 ORR	X17, XZR, X7

    (1149) 0x46baf8 LDR	X8, [X8]

    (1149) 0x46bafc TBZ	W15, #0, 46bb2c

    (1149) 0x46bb00 LDR	X15, [X20]

    (1149) 0x46bb04 LDR	X16, [X27]

    (1149) 0x46bb08 CMP	X15, X16

    (1149) 0x46bb0c B.LT	46bb24

    (1149) 0x46bb10 LDUR	X16, [X29, #480]

    (1149) 0x46bb14 LDR	X15, [X26]

    (1149) 0x46bb18 ADD	X17, X16, #1

    (1149) 0x46bb1c STUR	X17, [X29, #480]

    (1149) 0x46bb20 STR	X15, [X8, X16,LSL #3]

    (1149) 0x46bb24 ADD	X17, X7, #1

    (1149) 0x46bb28 STR	XZR, [X20]

    (1149) 0x46bb2c ADD	X15, X7, #1

    (1149) 0x46bb30 CMP	X13, X15

    (1149) 0x46bb34 B.NE	46bc20

    (1149) 0x46bb38 CMP	X12, X6

    (1149) 0x46bb3c B.LE	46b760

    (1149) 0x46bb40 LDR	X8, [X28]

    (1149) 0x46bb44 SUB	W15, W12, W6

    (1149) 0x46bb48 ORR	X17, XZR, X6

    (1149) 0x46bb4c TBZ	W15, #0, 46bb7c

    (1149) 0x46bb50 LDR	X15, [X21]

    (1149) 0x46bb54 LDR	X16, [X27]

    (1149) 0x46bb58 CMP	X15, X16

    (1149) 0x46bb5c B.LT	46bb74

    (1149) 0x46bb60 LDUR	X16, [X29, #472]

    (1149) 0x46bb64 LDR	X15, [X23]

    (1149) 0x46bb68 ADD	X17, X16, #1

    (1149) 0x46bb6c STUR	X17, [X29, #472]

    (1149) 0x46bb70 STR	X15, [X8, X16,LSL #3]

    (1149) 0x46bb74 ADD	X17, X6, #1

    (1149) 0x46bb78 STR	XZR, [X21]

    (1149) 0x46bb7c ADD	X15, X6, #1

    (1149) 0x46bb80 CMP	X12, X15

    (1149) 0x46bb84 B.EQ	46b760

    (1149) 0x46bb88 SUB	X15, X12, X17

    (1149) 0x46bb8c UBFM	X16, X17, #61, #60

    (1149) 0x46bb90 LDP	X18, X17, [SP, #112]

    (1149) 0x46bb94 SUB	X16, X16, X6,LSL #3

    (1149) 0x46bb98 ADD	X17, X17, X16

    (1149) 0x46bb9c ADD	X18, X18, X16

    (1149) 0x46bba0 B	46bbb4

      (1158) 0x46bba4 STR	XZR, [X18], #16

      (1158) 0x46bba8 SUBS	X15, X15, #2

      (1158) 0x46bbac ADD	X17, X17, #16

      (1158) 0x46bbb0 B.EQ	46b760

      (1158) 0x46bbb4 LDUR	X16, [X18, #504]

      (1158) 0x46bbb8 LDR	X1, [X27]

      (1158) 0x46bbbc CMP	X16, X1

      (1158) 0x46bbc0 B.GE	46bbe0

      (1158) 0x46bbc4 STUR	XZR, [X18, #504]

      (1158) 0x46bbc8 LDR	X16, [X18]

      (1158) 0x46bbcc LDR	X1, [X27]

      (1158) 0x46bbd0 CMP	X16, X1

      (1158) 0x46bbd4 B.LT	46bba4

      (1158) 0x46bbd8 B	46bc08

0x46bbdc HINT	#0

      (1158) 0x46bbe0 LDUR	X1, [X29, #472]

      (1158) 0x46bbe4 LDUR	X16, [X17, #504]

      (1158) 0x46bbe8 ADD	X3, X1, #1

      (1158) 0x46bbec STUR	X3, [X29, #472]

      (1158) 0x46bbf0 STR	X16, [X8, X1,LSL #3]

      (1158) 0x46bbf4 STUR	XZR, [X18, #504]

      (1158) 0x46bbf8 LDR	X16, [X18]

      (1158) 0x46bbfc LDR	X1, [X27]

      (1158) 0x46bc00 CMP	X16, X1

      (1158) 0x46bc04 B.LT	46bba4

      (1158) 0x46bc08 LDUR	X1, [X29, #472]

      (1158) 0x46bc0c LDR	X16, [X17]

      (1158) 0x46bc10 ADD	X3, X1, #1

      (1158) 0x46bc14 STUR	X3, [X29, #472]

      (1158) 0x46bc18 STR	X16, [X8, X1,LSL #3]

      (1158) 0x46bc1c B	46bba4

  (1151) 0x46bc20 SUB	X15, X13, X17

  (1151) 0x46bc24 UBFM	X16, X17, #61, #60

  (1151) 0x46bc28 LDP	X18, X17, [SP, #128]

  (1151) 0x46bc2c SUB	X16, X16, X7,LSL #3

  (1151) 0x46bc30 ADD	X17, X17, X16

  (1151) 0x46bc34 ADD	X18, X18, X16

  (1151) 0x46bc38 B	46bc50

0x46bc3c HINT	#0

  (1151) 0x46bc40 STR	XZR, [X18], #16

  (1151) 0x46bc44 SUBS	X15, X15, #2

  (1151) 0x46bc48 ADD	X17, X17, #16

  (1151) 0x46bc4c B.EQ	46bb38

  (1151) 0x46bc50 LDUR	X16, [X18, #504]

  (1151) 0x46bc54 LDR	X1, [X27]

  (1151) 0x46bc58 CMP	X16, X1

  (1151) 0x46bc5c B.GE	46bc80

  (1151) 0x46bc60 STUR	XZR, [X18, #504]

  (1151) 0x46bc64 LDR	X16, [X18]

  (1151) 0x46bc68 LDR	X1, [X27]

  (1151) 0x46bc6c CMP	X16, X1

  (1151) 0x46bc70 B.LT	46bc40

  (1151) 0x46bc74 B	46bca8

0x46bc78 HINT	#0

0x46bc7c HINT	#0

(1150) 0x46bc80 LDUR	X1, [X29, #480]

(1150) 0x46bc84 LDUR	X16, [X17, #504]

(1150) 0x46bc88 ADD	X3, X1, #1

(1150) 0x46bc8c STUR	X3, [X29, #480]

(1150) 0x46bc90 STR	X16, [X8, X1,LSL #3]

(1150) 0x46bc94 STUR	XZR, [X18, #504]

(1150) 0x46bc98 LDR	X16, [X18]

(1150) 0x46bc9c LDR	X1, [X27]

(1150) 0x46bca0 CMP	X16, X1

(1150) 0x46bca4 B.LT	46bc40

  (1151) 0x46bca8 LDUR	X1, [X29, #480]

  (1151) 0x46bcac LDR	X16, [X17]

  (1151) 0x46bcb0 ADD	X3, X1, #1

  (1151) 0x46bcb4 STUR	X3, [X29, #480]

  (1151) 0x46bcb8 STR	X16, [X8, X1,LSL #3]

  (1151) 0x46bcbc B	46bc40

0x46bcc0 LDP	X20, X19, [SP, #368]

0x46bcc4 LDP	X22, X21, [SP, #352]

0x46bcc8 LDP	X24, X23, [SP, #336]

0x46bccc LDP	X26, X25, [SP, #320]

0x46bcd0 LDP	X28, X27, [SP, #304]

0x46bcd4 LDP	X29, X30, [SP, #288]

0x46bcd8 ADD	SP, SP, #384

0x46bcdc RET

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 75.17 to 9.40 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 75.17 to 4.50 cycles (16.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1516 bytes. The binary function is storing 488 bytes.

General properties

nb instructions	439
loop length	1756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

45.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50
cycles	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.13
Overall L1	75.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 75.17 cycles. At this rate:

21% of peak load performance is reached (20.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46a650

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 46a6f8 <.omp_outlined..20+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X15, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46a718 <.omp_outlined..20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X24, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X25, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46a778 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X19, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 46a81c <.omp_outlined..20+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X22, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46ab84 <.omp_outlined..20+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a8d0 <.omp_outlined..20+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46ac2c <.omp_outlined..20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X19, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4b1270 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46b198 <.omp_outlined..20+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X28, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46b1d4 <.omp_outlined..20+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ee1d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee1f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4c0 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 46b25c <.omp_outlined..20+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 46b230 <.omp_outlined..20+0xbe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae3c0 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46b24c <.omp_outlined..20+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae3c0 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee250>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f990 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee260>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b318 <.omp_outlined..20+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORN X11, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46b2e8 <.omp_outlined..20+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46bcc0 <.omp_outlined..20+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b3a0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X11, X13, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, X11, #4157	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b3a0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b6e0 <.omp_outlined..20+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46b40c <.omp_outlined..20+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46b76c <.omp_outlined..20+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 75.17 to 4.50 cycles (16.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1516 bytes. The binary function is storing 488 bytes.

General properties

nb instructions	439
loop length	1756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

45.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50
cycles	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.13
Overall L1	75.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 75.17 cycles. At this rate:

21% of peak load performance is reached (20.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 46a650

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 46a6f8 <.omp_outlined..20+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X15, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46a718 <.omp_outlined..20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X24, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X25, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46a778 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X19, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 46a81c <.omp_outlined..20+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X22, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46ab84 <.omp_outlined..20+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46a8d0 <.omp_outlined..20+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b130 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46ac2c <.omp_outlined..20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X19, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4b1270 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46b198 <.omp_outlined..20+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X28, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 46b1d4 <.omp_outlined..20+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ee1d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee1f0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4c0 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 46b25c <.omp_outlined..20+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 46b230 <.omp_outlined..20+0xbe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae3c0 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46b24c <.omp_outlined..20+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae3c0 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee250>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #616	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f990 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee260>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #640	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46b318 <.omp_outlined..20+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORN X11, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 46b2e8 <.omp_outlined..20+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 46bcc0 <.omp_outlined..20+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b3a0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X11, X13, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, X11, #4157	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b3a0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46b6e0 <.omp_outlined..20+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46b40c <.omp_outlined..20+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46b76c <.omp_outlined..20+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x46a650–	1.84	0.7
○Loop 1187 - par_strength.c:1691-1693 - exec	0.33	0.11
○Loop 1168 - par_strength.c:1951-1953 - exec	0.03	0.01
○Loop 1166 - par_strength.c:1978-1984 - exec	0.02	0.01
○Loop 1186 - par_strength.c:1695-1697 - exec	0	0
▼Loop 1161 - par_strength.c:2000-2083 - exec–	0	0
▼Loop 1160 - par_strength.c:2000-2083 - exec–	0	0
○Loop 1165 - par_strength.c:2076-2083 - exec	0	0
▼Loop 1159 - par_strength.c:2000-2053 - exec–	0	0.01
▼Loop 1162 - par_strength.c:2011-2048 - exec–	0.1	0.03
○Loop 1164 - par_strength.c:2024-2034 - exec	0.64	0.21
○Loop 1163 - par_strength.c:2038-2048 - exec	0	0
▼Loop 1170 - par_strength.c:1806-1941 - exec–	0	0
▼Loop 1171 - par_strength.c:1806-1941 - exec–	0	0
▼Loop 1169 - par_strength.c:1806-1941 - exec–	0	0
▼Loop 1175 - par_strength.c:1823-1872 - exec–	0	0
○Loop 1177 - par_strength.c:1840-1854 - exec	0	0
○Loop 1176 - par_strength.c:1858-1872 - exec	0	0
▼Loop 1172 - par_strength.c:1877-1922 - exec–	0	0
○Loop 1173 - par_strength.c:1911-1922 - exec	0	0
○Loop 1174 - par_strength.c:1894-1907 - exec	0	0
○Loop 1178 - par_strength.c:1935-1941 - exec	0	0
○Loop 1167 - par_strength.c:1955-1957 - exec	0	0
▼Loop 1150 - par_strength.c:2095-2230 - exec–	0	0
▼Loop 1151 - par_strength.c:2095-2230 - exec–	0	0
▼Loop 1149 - par_strength.c:2095-2230 - exec–	0	0
▼Loop 1152 - par_strength.c:2163-2211 - exec–	0	0
○Loop 1154 - par_strength.c:2181-2195 - exec	0	0
○Loop 1153 - par_strength.c:2199-2211 - exec	0	0
○Loop 1158 - par_strength.c:2224-2230 - exec	0	0
▼Loop 1155 - par_strength.c:2106-2158 - exec–	0	0
○Loop 1156 - par_strength.c:2143-2158 - exec	0	0
○Loop 1157 - par_strength.c:2124-2139 - exec	0	0
▼Loop 1185 - par_strength.c:1714-1797 - exec–	0	0
▼Loop 1180 - par_strength.c:1714-1797 - exec–	0	0
▼Loop 1179 - par_strength.c:1714-1770 - exec–	0.01	0.01
▼Loop 1181 - par_strength.c:1731-1765 - exec–	0.1	0.03
○Loop 1183 - par_strength.c:1743-1752 - exec	0.62	0.2
○Loop 1182 - par_strength.c:1756-1765 - exec	0	0
○Loop 1184 - par_strength.c:1791-1797 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code